Evaluation Kit for Applications with HybridPACK™2 Modules

Transcription

HybridPACK™
Hybrid Kit for HybridPACK™2
Evaluation Kit for Applications with
HybridPACK™2 Module
Application Note
V2.4, 2014-08-11
System Engineering
Edition 2014-08-11
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Evaluation Kit for Applications with HybridPACK™2 Module
Revision History: 2014-08-11, V2.4
Previous Revision: V2.3
Page
Subjects (major changes since last revision)
36
Figure 29, changed capacitors C875 (from 22uF to 4.5uF) and C876 (from 22uF to 100uF)
48
Figure 3, changed capacitors C875 (from 22uF to 4.5uF) and C876 (from 22uF to 100uF)
Trademarks of Infineon Technologies AG
A-GOLD™, BlueMoon™, COMNEON™, CONVERGATE™, COSIC™, C166™, CROSSAVE™, CanPAK™,
CIPOS™, CoolMOS™, CoolSET™, CONVERPATH™, CORECONTROL™, DAVE™, DUALFALC™, DUSLIC™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, E-GOLD™, EiceDRIVER™,
EUPEC™, ELIC™, EPIC™, FALC™, FCOS™, FLEXISLIC™, GEMINAX™, GOLDMOS™, HITFET™,
HybridPACK™, INCA™, ISAC™, ISOFACE™, IsoPACK™, IWORX™, M-GOLD™, MIPAQ™, ModSTACK™,
MUSLIC™, my-d™, NovalithIC™, OCTALFALC™, OCTAT™, OmniTune™, OmniVia™, OptiMOS™,
OPTIVERSE™, ORIGA™, PROFET™, PRO-SIL™, PrimePACK™, QUADFALC™, RASIC™, ReverSave™,
SatRIC™, SCEPTRE™, SCOUT™, S-GOLD™, SensoNor™, SEROCCO™, SICOFI™, SIEGET™,
SINDRION™, SLIC™, SMARTi™, SmartLEWIS™, SMINT™, SOCRATES™, TEMPFET™, thinQ!™,
TrueNTRY™, TriCore™, TRENCHSTOP™, VINAX™, VINETIC™, VIONTIC™, WildPass™, X-GOLD™, XMM™,
X-PMU™, XPOSYS™, XWAY™.
Other Trademarks
AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is
licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of
Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION.
MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of
Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc.,
USA. muRata™ of MURATA MANUFACTURING CO. OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™
of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™
of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™,
PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™,
WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2009-10-19
Application Note
3
V2.4, 2014-08-11
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
How to Order Hybrid Kit for HybridPACK™2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Board (6ED100HP2-FA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HybridPACK™2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cooling Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
13
13
14
14
15
16
3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
3.8.4
Hybrid Kit for the HybridPACK™2 Evaluation Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Dimensions of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Mode Power Supply (SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IGBT Switch-off Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Protection and Clamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Layers of Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics, Layout and Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
20
21
22
23
23
23
24
25
26
27
29
30
30
31
31
32
32
39
43
45
4
4.1
4.2
4.3
4.4
4.4.1
4.4.1.1
4.4.1.2
4.5
4.6
Hybrid Kit for the HybridPACK™2 Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connector to the Driver Board (K1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration of TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Configuration of TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting Serial/Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
51
55
55
56
56
56
57
58
58
Application Note
4
V2.4, 2014-08-11
Table of Contents
4.7
4.8
4.9
4.10
4.10.1
4.10.2
4.10.3
4.11
4.12
4.12.1
4.12.2
4.12.3
4.12.4
Resolver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Encoder Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR SSC Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Encoder Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Hall Sensor Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Layers for the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics, Layout and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Note
5
58
58
58
59
59
61
61
61
62
62
76
80
90
V2.4, 2014-08-11
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
The Hybrid Kit for HybridPACK™2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram of Hybrid Kit for HybridPACK™2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Dimensions of the Hybrid Kit for HybridPACK™2 (all dimensions are in mm) . . . . . . . . . . . . . . . . 13
HybridPACKTM2 IGBT Six-Pack Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC-Link Capacitor for HybridPACK™2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Example of Water Cooling Element for HybridPACK™2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Water Cooling System Technical Drawings (Part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Water Cooling System Technical Drawings (Part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Driver Board Mounted on the Top of the HybridPACK™2 Module. . . . . . . . . . . . . . . . . . . . . . . . . 19
External Connector on the Driver Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Dimensions of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PCB Mounting Stand-offs of HybridPACK™2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Hybrid Kit for the HybridPACKTM2 Evaluation Driver Board Block Diagram . . . . . . . . . . . . . . . . . 23
Schematic of the Input Logic Block of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximal Switch-off Current at Different DC-Link Voltages (Gate Resistance as a Parameter) . . . 25
Temperature of Gate Resistors vs. Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Desaturation Protection and Active Clamping Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
a) Short Circuit w/o Active Clamp (DC Voltage=275V, Voltage Overshoot=628V)
b) With Active Clamp Function (DC Voltage=400V, Voltage Overshoot=604V) . . . . . . . . . . . . . . 28
Fault Output of a Single Driver IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fault Output During: a) Normal Operation b) Operation under Short Circuit . . . . . . . . . . . . . . . . 29
Characteristics of the Temperature Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Characteristics of the DC Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Copper and Isolation for Layers of Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Schematics Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SMPS - Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
External Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Fault Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
IGBT Driver - Bottom Transistor of Phase U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
IGBT Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DC Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IGBT Module Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Assembly Drawing of the Driver Board (Top) - part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Assembly Drawing of the Driver Board (Top) - part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Assembly Drawing of the Driver Board (Bottom) - part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Assembly Drawing of the Driver Board (Bottom) - part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Driver Board - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Driver Board - Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Driver Board - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Hybrid Kit for the HybridPACK™2 Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Hybrid Kit for the HybridPACK™2 Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Block Diagram of the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External Connector Pin Assignment Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External Connector Pin Assignment Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Overvoltage and Wrong Polarity Protection Circuit (same for Logic Board v1.2 and v1.3b) . . . . . 55
Application Note
6
V2.4, 2014-08-11
List of Figures
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Figure 83
Figure 84
Figure 85
Figure 86
Figure 87
Figure 88
HW Boot Configuration of TC1767 DIP-Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Boot Configuration Switch (SW1) and Serial/Parallel Interface Select Switch (SW2) . . . . . . .
GMR SSC Interface (Logic Board v1.3b only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR SSC Interface - Proposal Using TLE5012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Picture of Possible Physical Implementation of the GMR Sensor . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of the Layers for the Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of the Layers for the Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics Block Overview Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics Block Overview Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Debug Connector (same for Logic Board v1.2 and v1.3b) . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog (same for Logic Board v1.2 and v1.3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolver Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolver Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Level Shifter for Adapting 3.3V to 5V Logic Levels Logic Board v1.2. . . . . . . . . . . . . . . . . . . . . . .
Level Shifter for Adapting 3.3V to 5V Logic Levels Logic Board v1.3b. . . . . . . . . . . . . . . . . . . . . .
Connector to the Driver Board (same for Logic Board v1.2 and v1.3b) . . . . . . . . . . . . . . . . . . . . .
Microcontroller Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Filter Logic Board v1.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Filter Logic Board v1.3b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller TC1767 Pin Assignment Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller TC1767 Pin Assignment Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM (same for Logic Board v1.2 and Logic Board v1.3b) . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Board Temperature Measurement (Logic Board v1.3b only) . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing of the Logic Board v1.2 (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing of the Logic Board v1.3b (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing of the Logic Board v1.2 (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing of the Logic Board v1.3b (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board v1.2 - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board v1.2 - Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board v1.2 - Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board v1.2 - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board v1.3b - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board v1.3b - Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board v1.3b - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Note
7
56
57
59
60
60
61
61
62
63
64
65
65
66
66
67
67
68
68
69
70
71
72
73
74
75
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
V2.4, 2014-08-11
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Key Data of DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Data and Characteristic Values (Typical Values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials for Hybrid Kit for the HybridPACK™2 Evaluation Driver Board . . . . . . . . . . . . . .
External Connection Pin Assignment Logic Board v1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Connector Pin Assignment Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Startup Modes for TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting Serial/Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials for Hybrid Kit for the HybridPACK™2 Logic Board v1.2 . . . . . . . . . . . . . . . . . . . .
Bill of Materials for hybrid Kit for HybridPACK™2 Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . .
Application Note
8
15
20
45
51
54
57
57
90
92
V2.4, 2014-08-11
List of Tables
Application Note
9
V2.4, 2014-08-11
Introduction
1
Introduction
The Hybrid Kit for HybridPACK™2 shown in Figure 1 was developed to support customers during their first
steps in designing applications with HybridPACK™2 IGBT module. The following chapters provide a detailed
description of the main components and their functionality. This information is intended to enable the customers
to re-use and modify the original Hybrid Kit design and qualify their own design for the production, according to
their own specific requirements.
The boards Hybrid Kit for HybridPACKTM2 Evaluation Driver Board (further referred as “Driver Board” ) and
Hybrid Kit for HybridPACKTM2 Logic Board (further referred as “Logic Board”) provided by Infineon
Technologies are subjected to functional testing only.
The current implementation of the Hybrid Kit for HybridPACKTM2 (e.g. electrical schematics) is for reference
only! It does not cover in general all application specific requirements. For specific recommendations on how
to implement designs with HybridPACKTM2 and EiceDRIVER™, please contact your local Infineon sales partner.
More information is available on www.infineon.com.
Due to their purpose the system is not subjected to the same procedures regarding Returned Material Analysis
(RMA), Process Change Notification (PCN) and Product Withdraw (PWD) as regular products.
See Legal Disclaimer and Warnings for further restrictions on Infineon Technologies’ warranty and liability.
1.1
How to Order Hybrid Kit for HybridPACK™2
Hybrid Kit for HybridPACK™2 and Hybrid Kit for HybridPACK™2 Evaluation Driver Board (that can be
ordered separately) have Infineon Technologies SAP numbers and can be ordered via Infineon Sales Partners.
•
SAP ordering number for Hybrid Kit for HybridPACK™2: SP000635950
•
SAP ordering number for Hybrid Kit for HybridPACK™2 Evaluation Driver Board: SP000552868
Information can also be found at the Infineon Technologies web page: www.infineon.com
Figure 1
The Hybrid Kit for HybridPACK™2
Application Note
10
V2.4, 2014-08-11
Introduction
WARNING!
Please always take care of the dead-time settings of the driver (to
avoid short circuit conditions on the IGBT module) and always
have on mind that Hybrid Kit for HybridPACKTM2 inverter has no
breaking chopper or similar hardware protection to absorb the
energy generated during the regenerative breaking of a motor. In
any case user shall ensure that voltage, current and temperature
are monitored properly, e.g. by software or additional supporting
hardware.
Application Note
11
V2.4, 2014-08-11
Design Features
2
Design Features
The Hybrid Kit for HybridPACK™2 is made up of two PCBs (Driver Board and Logic Board) mechanically and
electrically suitable to be used with an IGBT Module HybridPACK™2 (included), a DC-bus capacitor and a cooler.
All these components build a complete main inverter for (H)EV applications up to 80kW.
IGBT driver
1ED020I12-FA
IGBT driver
1ED020I12-FA
Debug
Connector
IGBT driver
1ED020I12-FA
Logic Board
Watchdog
IGBT driver
1ED020I12-FA
IGBT driver
1ED020I12-FA
IGBT driver
1ED020I12-FA
Supply
C
o
n
Logic
DC-Bus Voltage
Measurement
(Isolated)
SMPS
c
IGBT Temp.
Measurement
t
o
r
n
VDC meas.
n
e
Other Sensor
c
FAULT
Signals
t
o
CAN / RS232
Level
Shifter
I, U, V Current
Measurement
r
RST
EEPROM
Encoder
n
e
Temp. IGBT (x3)
Microcontroller
TC1767
C
o VDC, Temp
PWM
Supply
Resolver
Interface
Resolver
6ED100HP1-FA Driver Board
Connector
IGBT Module HybridPACK™2
Current U
CAN RS232
A/D IO Supply
Current V
Current W
Encoder
Resolver
Other Sensor
Figure 2
Block Diagram of Hybrid Kit for HybridPACK™2
Figure 2 show the complete block diagram for the system and the following sections provide an overview of the
single components including main features, key data, pin assignments and mechanical dimensions.
2.1
•
•
•
•
•
Main Features
Complete main inverter for (H)EV applications up to 80kW
Automotive qualified IGBT module HybridPACK™2
– 650V/800A IGBT & Diode chipset
Automotive qualified Driver IC 1ED020I12-FA
– Based on coreless transformer technology
– Up to 1200V and 2A driving capability
– VCE sat - detection
TriCore™ family 32-bit microcontroller TC1767: member of the AUDO FUTURE product family designed for
automotive applications
Possibility of usage of different motor position interfaces: encoder, resolver, GMR (Giant Magneto-Resistance)
or hall sensor
Application Note
12
V2.4, 2014-08-11
Design Features
2.2
Dimensions
Figure 3 shows the dimensions of a complete Hybrid Kit for HybridPACK™2.
98.4
216.0
237.0
75.5
65.0
50.0
47.4
25.0
Figure 3
41.5
Dimensions of the Hybrid Kit for HybridPACK™2 (all dimensions are in mm)
Remark: Logic Board v1.3b is 2mm longer than Logic Board v1.2 (100.4 mm comparing to 98.4 mm).
2.3
Key Components
For detailed technical information about the different components please refer to the different web pages on the
Infineon Internet.
2.3.1
Driver Board (6ED100HP2-FA)
The 6ED100HP2-FA is a six channel IGBT driver board, specially designed for the HybridPACK™2 IGBT module.
The main features and a detailed description of the board, including schematics and layout, can be found in
Chapter 3.
Application Note
13
V2.4, 2014-08-11
Design Features
2.3.2
Logic Board
The Logic Board contains all necessary components for the control of the system. Furthermore it offers the
connections to the motor positioning system (encoder, resolver or GMR) and to the current measurement system.
For a detailed description of the board please refer to Chapter 3.
2.3.3
HybridPACK™2
(see Figure 4) is a power module designed for Full Hybrid Electrical Vehicle (HEV) applications for a power range
up to 80kW. Designed for a junction operation temperature at 150°C, the module accommodates a six-pack
configuration of 3rd generation Trench-Field-Stop IGBT and matching emitter controlled diodes and is rated up to
800A/650V. It is based on Infineon Technologies leading TRENCHSTOPTM IGBT Technology, which offers lowest
conduction and switching losses.
HybridPACK™2 is designed for direct water-cooled inverter systems (temperature of coolant 75°C). The Pin Fin
copper base plate combined with high-performance ceramic substrate and Infineon Technologies enhanced wirebonding process provides unparalleled thermal cycling and power cycling reliability for full hybrid inverter
applications. For a compact inverter design the driver stage PCB can easily be soldered on top of the module. All
power connections are realized with screw terminals.
Figure 4
HybridPACKTM2 IGBT Six-Pack Module
Application Note
14
V2.4, 2014-08-11
Design Features
2.3.4
DC-Link Capacitors
For Hybrid Kit for HybridPACK™2 are used Epcos B25655J4507K and Kemet C4EEGMX6500AAUK as DC bus
capacitors.
2.3.4.1
EPCOS B25655J4507K
The main features of the power electronic capacitor B25655J4507K from Epcos AG (see Figure 5) are shown in
Table 1. Please refer to the Epcos datasheet for further details.
Table 1
Key Data of DC-Link Capacitor
Characteristics
Maximum ratings
Test Data
CR
500 µF ±10%
Vs
600V
VTT
675V DC, 10s
VR
450V DC
î
2kA
Rins ·C
≥ 10000s
WR
50Ws
Is
8kA
tan δ (50 Hz) ≤ 8 · 10-4
Imax
120A
(dV/dt)max
4V/µs
Lself
15nH
(dV/dt)s
16V/µs
-4
tan δ0
2 · 10
Rs
1.0mΩ
Climatic Category
0/110/21(IEC 68-1/2)
Design Data
Tmin
- 40°C
Dimensions l × w × h 237 × 72 × 50 mm
Tmax
+ 110°C
Approx. weight
1.2kg
Impregnation
Resin Filled
Max. Rel. Humidity ≤ 95%
Tstg
- 45 … +110°C Terminals
Flat Copper
Clearance
8 mm
Values after Test Ca, IEC 68-2
Creepage distance
(21 days, 40°C, 93% rel. humidity)
ΔC/C
≤ 5%
Δtanδ
≤ 4 ·10-4
Rins ·C
≥ 3000s
8mm
Plastic Case
Mean Life Expentancy
tLD
15000h
αFQ
300fit
Application Note
15
V2.4, 2014-08-11
Design Features
Figure 5
DC-Link Capacitor for HybridPACK™2 B25655J4507K from EPCOS AG
Application Note
16
V2.4, 2014-08-11
Design Features
2.3.4.2
Kemet C4EEGMX6500AAUK
The power electronic capacitor C4EEGMX6500AAUK (see Figure 6) from KEMET Electronics is a metallized
seal-healing polypropylene capacitor with a non-inductive winding. The plastic case is filled with resin for longterm
humidity protection. Two battery connections and 6 terminals 6mm holes for the connection to the IGBTs.
Electrical perfomance is given on Figure 7, thermal and mechanical characteristics are given in Figure 8 and
drawings are shown in Figure 9.
Figure 6
DC-Link Capacitor for HybridPACK™2 C4EEGMX6500AAUK from KEMET Electronics
Nominal capacitance
C_nom
500 µF
Tolerance
C_tol
± 10 %
Rated DC voltage
U_rated
450 VDC
@105°C
Peak voltage
U_peak
650 VDC
for 10sec
Nominal RMS current
I_max_rms
120 A
@10kHz; T_case <105°C
Max peak current
I_peak
2500 A
@450VDC;dv/dt = 2V/µs
Equivalent Series resistance
ESR
Equivalent Series inductance
ESL
Dissipation factor@1kHz
DF
Max pulse rise time
(dv/dt)max
Min Insulation resistance
Ris
Lifetime
Lexp
FIT
Figure 7
1 mOhm
@ 1kHz
15 nH
0,01 %
@1 kHz
5 V/µs
20 MOhm
15000 hours
FIT
Electrical performance of C4EEGMX6500AAUK
Application Note
@RT ± 5°C
17
500VDC; for120sec
T_hotspot_max >=90°C
300 1/kpcsHours
V2.4, 2014-08-11
Design Features
Thermal characteristics
Operating temperature min/max
-40°C
110°C
Storage temperature min/max
0°C
105°C
Climatic Category
40/105/56
max 60% r.H
IEC 60068-1
Mechanical characteristics
Dimensions
L xW x H
Weight
m
237 x 72 x 50
mm
1,2 Kg
Test method and performances
Voltage test between terminals @ 25°C
Ut-t
675
V/10s
Voltage test terminals to case @ 50Hz
Ut-c
2500
V/1min
Figure 8
Thermal and Mechanical Characterisics of C4EEGMX6500AAUK
Figure 9
Drawings of C4EEGMX6500AAUK
Application Note
18
V2.4, 2014-08-11
Design Features
2.3.5
Cooling Element
For applications requiring higher power or higher operation temperature a usage of water cooling element is
recommended. Figure 10 shows the low cost water cooling system that is included in the Hybrid Kit for
HybridPACK™2 which can be screwed directly to HybridPACK™2 - Figure 11 and Figure 12 are showing the
technical drawings of it.
Figure 10
Example of Water Cooling Element for HybridPACK™2
Application Note
19
V2.4, 2014-08-11
Design Features
Figure 11
Water Cooling System Technical Drawings (Part 1)
Application Note
20
V2.4, 2014-08-11
Design Features
Figure 12
Water Cooling System Technical Drawings (Part 2)
Application Note
21
V2.4, 2014-08-11
Hybrid Kit for the HybridPACK™2 Evaluation Driver Board
3
Figure 13
Driver Board Mounted on the Top of the HybridPACK™2 Module
3.1
Main Features
The Hybrid Kit for HybridPACK™2 Evaluation Driver Board offers the following features:
•
•
•
•
•
•
•
•
Six channel IGBT driver
Electrically and mechanically suitable for 650 V IGBT Module HybridPACK™2
Includes DC/DC power supply
Isolated voltage measurement
Short circuit protection with toff < 6 µs
Undervoltage lockout of IGBT driver IC
Positive logic with 5 V CMOS level for PWM and Fault signals
One fault output signal for each leg and one common for all legs
Important: - if a Driver Board is used as a standalone board (without Logic Board from Hybrid Kit), the resistor
R534 (please refer to Figure 29) should be populated (0R) to connect 2 grounds (“digital” and “analog”). If these
two grounds are not connected one can notice some signal disturbances. If the Driver Board is used together with
the Logic Board (as in a complete Hybrid Kit) the 2 grounds are already connected on the Logic Board (therefore
it is in design of Driver Board the R534 unpopulated) and no modification (soldering) should be taken on a Driver
Board.
Application Note
22
V2.4, 2014-08-11
3.2
Key Data
All values given in the Table 2 (bellow) are typical values, measured at TA = 25 °C
Table 2
Key Data and Characteristic Values (Typical Values)
Parameter
Value
Unit
VSUPPLY – Voltage Supply
+[8...18]
V
VPWM – PWM Signals for Top and Bottom IGBT (Active High)
0 / +5
V
VFAULT – /FAULT Detection Output (Active Low)
0 / +5
V
IFAULT – Max. /FAULT Detection Output Load Current
10
mA
VRST – /RST Input (Active Low)
0 / +5
V
ISUPPLY – Supply Current Consumption (Idle Mode) (VSUPPLY=12V)
260
mA
VOUT – Drive Voltage Level
+15 / -8
V
IG – Maximum Peak Output Current
±10
A
30
W
20
kHz
tPDELAY – Propagation Delay Time
200
ns
tPDISTO – Input to Output Propagation Distortion
15
ns
tMININ – Minimum Pulse Suppression for Turn-on and Turn-off2)
30
ns
VDESAT – Desaturation Reference Level
9
V
dmax – Maximum Duty Cycle
100
%
600
V
PDC/DC – Maximum DC/DC Output Power of SMPS Unit
fS – Maximum PWM Signal Frequency
1)
VCES – Maximum Collector – Emitter Voltage on IGBT
3)
TOP – Operating Temperature (Design Target)
-40…+125 °C
TSTO – Storage Temperature (Design Target)
VIORM – Maximum Repetitive Insulation Voltage
-40…+125 °C
4)
(1ED020I12-FA Driver IC)
5)
VISO – Maximum Insulation Test Voltage (1ED020I12-FA Driver IC)
1)
2)
3)
4)
5)
1420
VPEAK
4500
Vrms
The max. switching frequency for the HybridPACK™2module should be calculated separately. Limiting factors are: max.
DC/DC output power of 4.6W per channel and max. PCB board temperature measured around gate resistors of 105 °C for
used FR4 material. For detailed information see Chapter 3.5.3
Minimum value tMININ given in 1ED020I12-FA IGBT driver datasheet
Maximum ambient temperature strictly depends on load and cooling conditions
1ED020I12-FA datasheet - complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01.Basic Insulation
1ED020I12-FA datasheet - complies with UL 1577
Application Note
23
V2.4, 2014-08-11
3.3
External Connector Pin Assignment
Figure 14 shows the pin assignment for the external connector (K1) on the Driver Board. As connector is used
Samtec MMS-112-01-L-DV. It includes all necessary signals to get the board into the operation, that is, supply,
control and monitoring. If a Driver Board is used as a part of Hybrid Kit the communication with a Logic Board is
done through this connector.
K1
12V
12V
GN D _D IG
GN D _AN A1
VD C
F LTW n
TEMP_I GBT_W
F LTVn
TEMP _IGBT _V
F LTU n
F LTn
1
3
5
7
9
11
13
15
17
19
21
23
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
12V
GN D _D I G
GN D _D IG
12 V
GN D _D I G
V AN A50
+5. 0V
T EMP_I GB T_U
R ST_I N n
PW MWT
PW MWB
PW MVT
PW MVB
PW MU T
PW MU B
MMS-112-01-L-D V
Figure 14
External Connector on the Driver Board
Pins 1 to 6 provide the power supply. The Driver Board must be supplied with an external regulated DC power
supply. The input voltage must be kept between 7V and 18V (nominal 12V) and the current consumption will
depend on different factors (PWM frequency, etc.). Please have on mind that if a Driver Board is used within Hybrid
Kit (together with a Logic Board) the “digital” ground on K1 (pins 4, 5 and 6) is connected to the “digital” ground on
the Logic Board. The same is valid for pins 1, 2 and 3 (+12V). Therefore, in the case of using of a complete Hybrid
Kit, no external 12V power supply needs to be applied to Driver Board additionally - it is already done through Logic
Board.
Pins 7 and 8 provide 5V analogue power supply - pin 7 supplies “analog” ground and pin 8 supplies +5V that is
internally generated on Driver Board (please refer to the Figure 29) and intended to be used as a power supply
for the temperature and DC bus voltage measurements. Although available on the pin 8 of connector K1, the +5V
analogue power supply is not connected to the +5V analogue supply of the Logic Board - on the other side, through
pin 7 on K1 the “analog” grounds on Driver and Logic Board are mutually connected.
To pins 9, 10, 15 and 19 are connected monitoring signals: DC-link voltage measurement and temperature
measurement of the three different phases inside of the IGBT module.
Pins 14 (phase W, top IGBT), 16 (phase W, bottom IGBT), 18 (phase V, top IGBT), 20 (phase V, bottom IGBT),
22 (phase U, top IGBT) and 24 (phase U bottom IGBT) contain the logic signals for controlling the 6 drivers on the
Driver Board. These PWM signals are generated by TriCore TC1767 on the Logic Board in the case that a Driver
Board is used as a part of a Hybrid Kit - if a Driver Board is not used as a part of Hybrid Kit the PWM signals should
be supplied through these pins.
Pins 12 is a Reset signal (to control the IGBT drivers 1ED020I12-FA).
Pins 13, 17, 21 and 23 contain Fault Detection signals - one for each phase and one as logical “AND” combination
of 3 phase fault Detection signals.
Application Note
24
V2.4, 2014-08-11
3.4
Mechanical Dimensions of the Driver Board
max. 19 mm
max. 16.5 mm
216 mm
70m
Figure 15
Dimensions of the Driver Board
The Driver Boards should be fastened by self taping screws and soldered to the auxiliary connectors on top of the
IGBT module. The contact joints (solder points) between PCB and module auxiliary contacts should be
mechanically relieved in order to disburden the solder connection as far as possible. Relieve of the contact points
is carried out by mounting the PCB directly onto the module at the ten mounting stand-offs (see Figure 16) using
self-tapping screws (thread forming with 2.5mm diameter) or similar assembly material. The screws should be
mounted in the sequence showed in Figure 16.
Figure 16
PCB Mounting Stand-offs of HybridPACK™2
Application Note
25
V2.4, 2014-08-11
3.5
Operation of the Driver Board
Figure 17 shows the block structure of the Driver Board. The following chapter describes these blocks in detail.
15V/-8V
15V/-8V
DC LINK
VOLTAGE
MEASUREMENT
SMPS
IGBT
Driver
UT
15V/-8V
15V/-8V (x3)
IGBT
Driver
VT
IGBT
Driver
WT
5V
5V
5V
5V
IGBT
Driver
VB
IGBT
Driver
WB
5V
5V
RESET
FAULT U
LOGIC
FAULT V
FAULT W
5V
RESET
FAULT
FAULT U
FAULT V
FAULT W
IGBT
Driver
UB
IGBT
MODUL
TEMP
(U,V,W)
12V
Connector
INPUT
LOGIC
(PWM)
IGBT MODUL TEMPERATURE (U,V,W)
DC LINK VOLTAGE MEASUREMENT
Figure 17
Hybrid Kit for the HybridPACKTM2 Evaluation Driver Board Block Diagram
3.5.1
Switching Mode Power Supply (SMPS)
The Driver Board has an integrated DC/DC converter which generates the required secondary isolated
unsymmetrical supply voltage of +15/-8V. Top and bottom driver voltages are independently generated by using
one unipolar input voltage of 12V.
An additional supply voltage (5V) is generated and forwarded to the external connector (K1, pin 7 and 8), so if a
Driver Board is used as a standalone board, it can be used to supply external components in the system (current
measurement, motor interface, etc.)
For circuit details please refer to Figure 29.
3.5.2
Input Logic
The Driver Board is a dedicated system for a six-pack HybridPACK™2 IGBT configuration - therefore it is
necessary to use 6 separated PWM signals. The schematics on Figure 18 shows the input logic block with +5V
positive logic. The block is made up of RC filters for each PWM signal in order to reduce noise. Additionally these
signals are pulled-down in order to avoid unwanted switching-on of the drivers. Please have on mind that the
Hybrid Kit for HybridPack™2 does not provide dead time automatically (meaning that hardware alone provides no
dead time) - it is up to the user to generate the PWM signals with the correct dead time (by means of software).
Application Note
26
V2.4, 2014-08-11
PW M_WT
R520
100R
C900
100pF/100V/COG
R521
15k
GND_DIG1
GND_DIG1
PW M_WB
R522
100R
C901
100pF/100V/COG
R523
15k
GND_DIG1
GND_DIG1
PW M_VT
R524
100R
C902
100pF/100V/COG
PWMWT
R525
PWMWB
15k
PWMVT
GND_DIG1
PWMVB
GND_DIG1
PW M_VB
R526
100R
PWMUT
C903
100pF/100V/COG
PWMUB
R527
15k
GND_DIG1
GND_DIG1
PW M_UT
R528
100R
C904
100pF/100V/COG
R529
15k
GND_DIG1
GND_DIG1
PW M_UB
R530
100R
C905
100pF/100V/COG
R531
15k
GND_DIG1
GND_DIG1
Figure 18
Schematic of the Input Logic Block of the Driver Board
3.5.3
IGBT Switch-off Behavior
Due to the stray inductances of the system a voltage overshoots occur during the switching-off the IGBT. Such
overshoots are added to the DC-link voltage, so that the maximum blocking voltage of the IGBT or capacitor might
be exceeded causing damages in both components (DC link capacitor and IGBT module). In order to avoid such
risks an active clamping circuit is used (see Chapter 3.5.6).
Without such protection methods the maximum current would be limited by the DC-link voltage and the voltage
overshoots at switching-off. The voltage overshoots can be minimized by increasing the gate resistor, which will
reduce the di/dt value. Figure 19 shows the maximal switch-off current at different DC-link voltages for a different
values of the gate resistor. These results were obtained with the DC-link capacitor described in Chapter 2.3.4.
Application Note
27
V2.4, 2014-08-11
Max Ic Vs Vce
1800
1600
1400
Ic (A)
1200
1000
800
600
400
200
0
200
250
300
350
400
450
Vce (V)
Rgoff=2.7Ohm
Rgoff=3.9Ohm
Rgoff=4.7Ohm
Figure 19
Maximal Switch-off Current at Different DC-Link Voltages (Gate Resistance as a Parameter)
3.5.4
Maximum Switching Frequency
The IGBT switching frequency is limited by the available power and by PCB temperature. According to theory the
power losses generated in the gate resistors are a function of a gate charge, voltage step at the driver output and
switching frequency. The energy is dissipated mainly through the PCB and raises the temperature around the gate
resistors. When the available power of the DC/DC converter is not exceeded, the limiting factor for the switching
frequency is the absolute maximum temperature for the FR4 material. The allowed operation temperature is 105
°C.
Generally the power losses generated in the gate resistors can be calculated according to Equation (1):
P dis = P RGext + P RGint = ΔV out ⋅ f S ⋅ Q ge
(1)
In Equation (1) f S resembles the switching frequency, ΔV out represents the voltage step at the driver output,
P dis is the dissipated power, Q ge is the IGBT gate charge value corresponding to +15V/-8V switching operation.
This value can be approximately calculated from the datasheet value by multiplying it by 0.77, that is
Q ge = 6.6μC . Therefore the maximum frequency limited by the available power will be:
f Smax = 4.6W ⁄ ( 23V ⋅ 6.6μC ) = 30.3kHz
Application Note
28
V2.4, 2014-08-11
Figure 20 shows experimentally determined board temperature dependencies with switching frequency (at 26°C
ambient temperature). From Figure 20 it can be concluded that the maximum switching frequency is limited by
PCB temperature.
Gate resistor temperature Vs. switching frequency @ Ta=25°C
105
Gate resistor temperature
95
85
75
65
55
45
35
25
1
3
5
7
9
11
13
15
17
19
Switching frequency (KHz)
Figure 20
Temperature of Gate Resistors vs. Switching Frequency
3.5.5
Booster
Two transistors per driver IC are used to amplify the driver ICs signals. On this way the driving IGBTs are supplied
with sufficient current even if driver ICs alone can’t deliver enough current. One NPN transistor is used for
switching the IGBT on and another PNP transistor for switching the IGBT off.
The transistors are dimensioned to have enough peak current to drive HybridPACK™2 modules. Peak current can
be calculated like in Equation (2):
ΔV out
I peak = ----------------------------------------------------R Gint + R Gext + R Driver
(2)
For circuit details please refer to Figure 33.
Application Note
29
V2.4, 2014-08-11
3.5.6
Short Circuit Protection and Clamp Function
The short circuit protection of the Driver Board basically relies on the detection of a voltage level higher as 9 V on
the DESAT pin of the 1ED020I12-FA driver IC and the implemented active clamp function. Thanks to this operation
mode, the collector-emitter overvoltage, which is a result of the stray inductance and the collector current slope,
is limited. Depending on the stray inductance, the current and the DC voltage the voltage overshoot during turn
off changes. Figure 21 shows the parts of the circuit needed for the desaturation function and the active clamping
function.
Figure 21
Desaturation Protection and Active Clamping Diodes
In the case of a short circuit the collector-emitter saturation voltage will rise and the driver detects the short circuit
occurrence - to protect the IGBT it has to be turned off. As a consequence of IGBT turn-off process there will occur
an voltage overshoot due to the stray inductance of the module and the DC-link. This voltage overshoot has to be
lower than the maximum IGBT blocking voltage. Therefore the Driver Board has an active clamping function
whereby the clamping will increase the voltage for the booster and also increase the voltage directly on the gate.
The typical turn-off waveform under short circuit condition and room temperature of a HybridPACK™2 module
without any additional protective functions is shown in Figure 22 a). Typical waveform under short circuit condition
with active clamp function at room temperature is shown in Figure 22 b). As it can be seen, the voltage overshoot
without active clamping at a DC voltage of 275V is close to the maximum IGBT blocking voltage of HybridPACK™2
(650V), which could damage the devices. With active clamping the voltage overshoot can be reduced and the DC
voltage increased without damaging the IGBT module (at 400V DC voltage can be observed voltage overshoot of
approximately 604V, Figure 22 b). In design are implemented 510V clamping diodes. The level of the clamping
voltage must be adjusted depending on the application.
Application Note
30
V2.4, 2014-08-11
a)
b)
Figure 22
a) Short Circuit w/o Active Clamp (DC Voltage=275V, Voltage Overshoot=628V)
b) With Active Clamp Function (DC Voltage=400V, Voltage Overshoot=604V)
Application Note
31
V2.4, 2014-08-11
3.5.7
Fault Output
When a short circuit occurs the voltage VCE is detected by the desaturation protection of the 1ED020I12-FA and
the IGBT is switched off. The fault is reported to the primary side of the driver as long as there is no reset signal
applied to the driver. The fault signal (/FLT) is active low - the schematic of design implemented in Driver Board
can be seen on Figure 23.
Figure 23
Fault Output of a Single Driver IC
Short circuit occurs
Ready signal
Fault signal
UGE
a)
Figure 24
b)
Fault Output During: a) Normal Operation b) Operation under Short Circuit
The fault signal (/FLT) will be in low state if a short circuit occurs and will remain low until /RST signal is pulled
down.
On the Driver Board each of the three legs has its own fault signal (FAULTUn, FAULTVn, FAULTWn). As it can
be seen in Figure 31, a LED will warn in the case of a DESAT-FAULT condition in one of the phases. The three
fault signals are connected to a logical AND gate and the output of this gate, together with the 3 phases fault
signals, is forwarded to the external connector (K1).
Application Note
32
V2.4, 2014-08-11
3.5.8
Temperature Measurement
The IGBT module HybridPACK™2 includes three integrated NTC (Negative Temperature Coefficient) sensors
which simplify the thermal measurements in inverters significantly.
The NTCs are located on the same ceramic substrate together with the IGBT and diode chips. The module is filled
with silicon gel for isolation purpose and under normal operation conditions the requirements for isolation voltages
are met. The NTC isolation capability is tested with 2.5kV AC in final test for 1 minute for 100% of module
production.
The NTCs are connected to the main connector K1 (pins 10, 15 and 19) by means of the circuit showed in
Figure 36. Figure 25 shows the relationship between IGBT module base plate temperature of the three phases
and output voltage of IGBT module temperature block (TEMP_IGBT_U, TEMP_IGBT_V, TEMP_IGBT_W,
K3.10/K3.19/K3.15)
Temperature Measurement
4,5
Output voltage TEMP_IGBT (V)
4,3
4,1
3,9
3,7
3,5
3,3
3,1
2,9
2,7
2,5
-30
-10
10
30
50
70
90
110
Temperature IGBT Module (°C)
Figure 25
Characteristics of the Temperature Measurements
Note: This temperature measurement is not suitable for the short circuit or short term overload detection and
should be used only for the module protection against long term overload or malfunction of the cooling system.
3.5.9
DC Voltage Measurement
On the Hybrid Kit for HybridPACK™2 the voltage at the DC link is measured by means of a isolation amplifier
which offers the necessary galvanic isolation (see Figure 35).
The output of this circuit is connected to the external connector (Vdc, K1.9). Figure 26 shows the relationship
between DC link voltage and Vdc output signal.
Application Note
33
V2.4, 2014-08-11
Vdc Vs. DC-Link Voltage
4,5
y = 0,0071x + 1,3296
4
3,5
Vdc (V)
3
2,5
2
1,5
1
0,5
0
0
50
100
150
200
250
300
350
400
DC-Link Voltage (V)
Figure 26
Characteristics of the DC Voltage Measurement
3.6
Switching Losses
Switching losses can be different comparing to the values given in the HybridPACK™2 IGBT module datasheet.
Main reason for this discrepancy is that switching voltages used on the Driver Board (+15V for turn-on and -8V for
turn-off) differ from HybridPACK™2 characterisation switching voltages (+15V/-15V).
Turn-on losses are expected to be close to the values of the datasheet of HybridPACK™2, but as mentioned, this
will be different for the turn-off losses. In general the turn-off losses depend on the stray inductances of the DClink and increase linear with the DC-link voltage. In the case of the Driver Board the turn-off losses do not increase
linearly because of the fact that the active clamping feature increases the turn-off losses due to decrease of the
di/dt.
3.7
Definition of Layers of Driver Board
The Driver Board was made keeping the following rules for the copper thickness and the space between different
layers shown in Figure 27.
1
Copper
1
2
1: 35 µm
2
2: 35 µm
3
3: 35 µm
4
4: 35 µm
5
5: 35 µm
6
Figure 27
6: 35 µm
3
4
5
Isolation
1-2: 0.5 mm
2-3: 0.5 mm
3-4: 0.5 mm
4-5: 0.5 mm
5-6: 0.5 mm
6
Copper and Isolation for Layers of Driver Board
Application Note
34
V2.4, 2014-08-11
3.8
Schematics, Layout and Bill of Material
To meet the individual customer requirements and to make the Driver Board for the HybridPACKTM2 module as a
platform for development or modifications, all necessary technical data like schematics, layout and components
are included in this chapter.
3.8.1
Schematics
IGBT_ DRIVER_UT VP15_U T VN 8_UT
+1 5.0 V
-8. 0V
I N+
I NR STn
FLTn
VP
COL
G
GN D
VN
IGBT_ MODULE
COLU T
G UT
G NDUT
CO LUT
GU T
GN DUT
G ND_UT
IGBT_ DRIVER_UT
CONNECTO R
SMPS
1 2V
IGBT_ DRIVER_UB
VP15_U BVN8_ UB
+ 15.0 V - 8.0 V
12Vin
SMPS
I N+
I NR STn
FLTn
GND _DIG
VP
COL
G
GN D
VN
COLUB
GUB GUB
G NDUB
CO LUB
GU B
GN DUB
GND_ UB
IGBT_ DRIVER_UB
GND _DIG 1
IGBT_ DRIVER_VT VP15_VT
+1 5.0 V
I N+
I NR STn
FLTn
I NPUT_L OGIC
PWM_ UT
PWM_ UB
PWM_ VT
PWM_ VB
PWM_ WT
PWM_ WB
IGBT_ DRIVER_VB
I N+
I NR STn
FLTn
FAULT_ LOGI C
R ST_INn
FLTn
FLTUn
FLTVn
FLTWn
RSTn_ in
FAU LT_n
FAUL T_Un
FAUL T_Vn
FAUL T_Wn
RST_I Nn
FAUL T_n
FAUL TUn
FAULTVn
FAU LTWn
RSTn
CO LVT
GVT
GN DVT
G ND_VT
IGBT_ DRIVER_VT
I NPUT_L OGIC
FLTUn
FLTVn
FLTWn
C OLVT
GVT
G NDVT
FAULTU n
FAULTVn
FAULTW n
VP15_VB VN 8_VB
+1 5.0 V - 8.0 V
VP
COL
G
GN D
VN
COL VB
GVB G VB
G NDVB
CO LVB
GVB
GN DVB
GWT
G NDWT
CO LWT
GWT
GN DWT
G ND_VB
IGBT_ DRIVER_VB
IGBT_ DRIVER_WT VP15_WT VN 8_WT
+1 5.0 V
-8. 0V
I N+
I NR STn
FLTn
R STn
FAULT_ LOGI C
VP
COL
G
GN D
VN
COLWT
G ND_WT
IGBT_ DRIVER_WT
IGBT_ DRIVER_WB
I N+
I NR STn
FLTn
VP15 _WB VN8_ WB
+15 .0V
- 8.0 V
VP
COL
G
GN D
VN
COL WB
GNDWB
G WB
CO LWB
GWB
GN DWB
G ND_WB
IGBT_ DRIVER_WB
Temp4
Te mp5
PWMUT
PWMUB
PWMVT
PWMVB
PWMWT
PWMWB
Temp2
Temp3
PW M_UT
PW M_UB
PW M_VT
PW M_VB
PW M_WT
PW M_WB
Te mp 0
Temp1
PWMUT
PWMUB
PWMVT
PWMVB
PWMWT
PWMWB
PO WER _VC C
PWMUT
PW MUB
PWMVT
PWMVB
PWMWT
PWMWB
VN 8_VT
-8. 0V
VP
COL
G
GN D
VN
IGBT_ MODULE
DC- LINK_VOL _MEAS
VDC_mea s_uc
VDC
VDC POWER_VCC
DC- LINK_VOL _MEAS
TEMP
TEMP_ IGBT_W
TEMP_ IGBT_U
TEMP_ IGBT_V
TEMP_ IGBT_ W
TEMP_ IGBT_U
TEMP_IG BT_V
TEMP_I GBT_W
TEMP_I GBT_U
TEMP_I GBT_V
Te mp 0
Te mp 1
Te mp 2
Te mp 3
Te mp 4
Te mp 5
Temp 0
Temp 1
Temp 2
Temp 3
Temp 4
Temp 5
CONNECTO R
TEMP
Figure 28
Schematics Block Overview
Application Note
35
V2.4, 2014-08-11
VP15_UT
+15.0V
D4
D5
ES1A
C867
22u/35V
1k6
V z= 1 5V
C868
4u7/25V/X7R
R171
R170
R169
C866
4u7/50V/X7R
1SMA5929BT3G
1k6
1k6
UT_PS
+
GND_UT
VN8_UT
-8.0V
VP15_WT
+15.0V
D6
WT_PS
3
ES1A
D7
C870
22u/35V
Q10
IPD90P03P4L-04
1k6
V z= 1 5V
C871
GND_WT
VN8_WT
4u7/25V/X7R
-8.0V
D8
VP15_VT
+15.0V
VT_PS
D19
6
7
D9
ES1A
Isen
1
1k6
1k6
1k6
R179
Vz = 15 V
1k6
R186
C880
GND_VB VN8_VB
4u7/25V/X7R
-8.0V
VP15_WB
+15.0V
D14
3
WB_PS
IPD144N06NG
D15
ES1A
C883
22u/35V
+
VP15_UB
+15.0V
1k6
D16
TRANSFORMER2
D17
ES1A
+
GND_DIG1
C888
22u/35V
C887
4u7/50V/X7R
1SMA5929BT3G
GND_UB
1k6
V z =1 5 V
R197
4
R196
1k6
GND_DIG1
C885
GND_WB
4u7/25V/X7RVN8_WB
-8.0V
C889
GND_UB
4u7/25V/X7R VN8_UB
-8.0V
R198
GND_DIG1
Vz = 15 V
UB_PS
R194
0R025
C886
10n/50V/X7R
R193
4k75
16
1SMA5929BT3G
1k6
14
15
C882
4u7/50V/X7R
R192
LM3478MM
GND_DIG1
GND_DIG1
GND_DIG1
Q13B 5
BCR10PN
1SMA5929BT3G
1k6
R183
12
13
Q5
1
6
C877
4u7/50V/X7R
1k6
DR
1k6
1
1 0k
UNDER_VOL_DETECTION
C881
10n/50V/X7R
FA/SD
COMP
FB
AGND
PGND
C879
22u/35V
+
2
Vin
7
2
3
4
5
VP15_VB
+15.0V
D13
R190
C884
22n/50V/X7R
2
POWER_UP
1 0k
R187
19K6
6
Q13A 5
BCR10PN
2
C874
GND_VT
VN8_VT
4u7/25V/X7R
-8.0V
D11
1k6
8
V z= 1 5V
ES1A
10
11
D12
1SMB5935BT3
U30
GND_DIG1
R184 80K6
UNDER_VOL_DETECTION
VB_PS
GND_DIG1
C878
100nF/100V/X7R
R182
10K
8
9
D10
ES1A
C872
4u7/50V/X7R
1SMA5929BT3G
R185
GND_DIG1
C876
100µF/20V/0810
+
R178
C875
GND_DIG1
4u7/50V/X7R
1
+
GND_DIG1
C873
22u/35V
+
R180
D20
1SMB30AT3
R191
BZV55/C13
R28
10K
VP
1SMA5929BT3G
1k6
1k6
R173
4
5
C869
4u7/50V/X7R
R175
+
12Vin
R174
T1
10 k
5
10 k
3
D18
R199
VDIG50
+5.0V
R533
VANA50
+5.0V
L1
0R
GND_DIG1
0R
R201
59K
ES1A
+
C890
C891
22u/16V/X7R 100n/16V/X7R
805
MURATA_BLM21P221SN
+
R534
C906
100n/50V/X7R
C907
22u/16V/X7R
opt
GND_DIG1
GND_DIG1
GND_DIG1
Figure 29
GND_ANA1
SMPS - Power Supply
KL_30
+12. 0V
GN D_AN A1
GN D_DI G1
VDC
TEMP_BO AR D
F LTWn
TEMP_H P2_W
F LTVn
TEMP_H P2_V
F LTU n
F LTn
1
3
5
7
9
11
13
15
17
19
21
23
KL_30
+12.0V
K1
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
GN D_DI G1
VAN A50_DB
TEMP_HP2_U
RST_IN n
PWMWT
PWMWB
PWMVT
PWMVB
PWMU T
PWMU B
TW-12-06-L-D -475-SM- A
Figure 30
External Connector
Application Note
36
V2.4, 2014-08-11
V D I G5 0
+5. 0 V
R STn
R S T_ IN n
R 5 11
1 5K
R 5 12
1K
F AU L T_U n
F AU L T_n
FA U LTU n
C 89 6
10n / 5 0V/ X7R
V D I G5 0
+5. 0 V
V D IG 50
+5 .0 V
GN D _D I G1
U 57
R 5 13
R 5 14
1 5K
1
3
6
1K
FA U LTVn
C 89 8
10n / 5 0V/ X7R
V D I G50
+5. 0V
Vc c
A
B
C
Y
5
C 8 97
1 00n / 50 V /X7R
4
GN D _ D I G1
2
GN D
74LV C 1G11 GW
GN D _D I G1
GN D _D IG 1
R 51 5
R 5 16
15K
1K
F AU L T_V n
F AU L T_W n
FA U LTW n
C 89 9
10n / 5 0V/ X7R
GN D _D I G1
VD IG50
+5.0V
1
VD IG 50
+5.0V
B C R 18 3S
4
BC R 18 3S
1 0k
4
BC R 1 83S
1 0k
2
1 0k
5
10 k
6
3
P A C KA GE = 1
Q 1 2B
BC R 18 3S
5
10 k
P AC KA GE = 1
Q 12A
VD I G50
+5. 0V
VD IG 50
+5.0V
10 k
3
P A C KA GE = 2
Q 11B
1
1 0k
2
10k
D 22
D 23
R 5 19
2 20R
D 21
R 5 17
2 20R
R 5 18
2 20R
6
GN D _D I G1
GN D _D I G1
GN D _ D I G1
Figure 31
P AC KA GE = 2
Q11 A
Fault Logic
Application Note
37
V2.4, 2014-08-11
PW M_WT
R520
100R
C900
100pF/100V/COG
R521
15k
GND_DIG1
GND_DIG1
PW M_WB
R522
100R
C901
100pF/100V/COG
R523
15k
GND_DIG1
GND_DIG1
PW M_VT
R524
100R
C902
100pF/100V/COG
PWMWT
R525
15k
PWMWB
PWMVT
GND_DIG1
PWMVB
GND_DIG1
PW M_VB
R526
100R
PWMUT
C903
100pF/100V/COG
PWMUB
R527
15k
GND_DIG1
GND_DIG1
PW M_UT
R528
100R
C904
100pF/100V/COG
R529
15k
GND_DIG1
GND_DIG1
PW M_UB
R530
100R
C905
100pF/100V/COG
R531
15k
GND_DIG1
GND_DIG1
Figure 32
Input Logic
Application Note
38
V2.4, 2014-08-11
VP
C 1 3_U B
10 0pF /10 0V /C OG
GN D
R 28_ U B
C 1 4_U B
17
16
IN+
13
IN-
14
R 3 4_U B
4 k7
15
18
FLTn
12
11
19
20
VD IG50
+5.0V
C OL
D 3_U B
P6S MB510 A
C 1 6_U B
4 u7/ 25V/ X7 R
H V _U B_U SD
U4
/ R ST
/ FLT
V CC2
D E SA T
V D I G5 0
+5 . 0 V
C OL
MU R A160 T3G
GN D
C 15 _U B
4u7/ 2 5V /X7R
R 2 9_U B
4k 7
R STn
U B_ 02
1K
VD I G5 0
10 0pF/ 10 0V / C OG +5 . 0 V
GN D _D I G1
D 6 _U B
U B_01
GN D
IN+
IN-
OU T
C LAMP
NC
RDY
GN D 2
C 1 7_U B
10 0n/ 50V/ X7 R
6
3
GN D 1
GN D 1
GN D 1
GN D 1
T2_U B
1
5
4
R 33_ U B
2R 7
G
3 U B_ 06
R 31 _U B
ZXTP 2012Z
GN D
V CC1
U B _05
3
U B _0 3 47R
7
8
D 4 _U B
E S1D
2
T1_U B
ZXTN 20 10Z
U B _ 041
R 3 2_U B
2R 7
2
D 9_U B
S MBJ 1 4C A
U B_07
V EE 2
V EE 2
V EE 2
V EE 2
1
2
9
10
0R
C 20 _U B
4u7/ 25V/ X7 R
1 E D 020 I1 2-FA
R 14_U B
C 21_ U B
4u7/ 2 5V /X7R
GN D
GN D
VN
C 22 _U B
C 2 3_U B
100n / 50 V/ X7R
10 0n/ 50V / X7R
GN D
GN D _D I G1
Figure 33
IGBT Driver - Bottom Transistor of Phase U
POWER _VC C
C OLUT
COLVT
G UT
C OLWT
GVT
C81
22 n/ 50 V/X7R
GWT
R8 4
10 K
C 80
2 2n/50V/ X7 R
G ND UT
R 83
1 0K
C 79
2 2n /5 0V/ X7R
GN DVT
R82
10K
GND WT
GV_T
EU_ T
EV_T
CUOL VB
Temp2
Temp 0
V_NTC2
Temp 3
U _N TC 1
Temp 1
V_NTC1
C84
22 n/ 50 V/X7R
GN DU B
R8 7
10 K
GV_B
EU _B
EV_B
D CL-_NN1
1
GU B
GU _B
FS800R06KE3
GVB
C 83
2 2n/50V/ X7 R
GN DVB
P3
EW_T
CW _B
C OLWB
V
Temp 4
W _N TC 2
Temp5
W _N TC 1
W
GW _B
EW _B
FS8 00R06KE3
GWB
R 86
1 0K
DC L+_P3
C W_T
GW_T
CV_B
U _N TC 2
Q4C
D CL+_P2
C 82
2 2n /5 0V/ X7R
R85
10K
D CL-_N3
N3
C V_T
GU_ T
P2
Q4B
C U_ T
CU _B
COLU B
Figure 34
DC L+_P1
DC L- _NN22
Q4A
P1
HybridPACK2 - module
FS800R 06 KE3
GND WB
IGBT Module
Application Note
39
V2.4, 2014-08-11
POW ER_VC C
R1 32
4K / 0 .1%
VANA5 0
+5. 0V
C 832
C8 27
100 n/ 16 V/ X7 R
R13 8
590 K
VB_ 23
3
3K9
1
OU T- I N-
VB_ 21
2
R5 09
39R
VB_ 22
3
C 833
1 0n /50 V/X7R
GN D1
6
R5 10
2K /0 .1%
R13 9
Vdd 1
8
Vd d2
C82 8
150 p/ 50V/ C0 G
U1 9
O UT+
I N+
GND 2
IN- A
O UTA
IN+A
7
5
1
VDC
R 14 5
1 0K 0.1 %
2
R 13 7
5 90 K
R40 8
158 R
4
V+
8
GN D_ AN A1
U 18
R 136
5 90 K
C83 5
100 n/ 16V/ X7 R
VANA50
+5. 0V
R1 27
2K /0 .1%
R 13 4
R13 5
5 90 K
590 K
HV_ VD_I CL +
+5 VVB
+5 V
33 0p/ 50 V/CO G
C8 30
10 0n /16 V/X7R
R 133
5 90 K
GN D_ ANA1
AC PL-7 82 T
IN- B
O UTB
IN+B
GN D_AN A1
GN D_ VB
GN D_VB
G ND_ VB
5
4
V-
7
6
AD 85 52AR Z
C 83 1
R 14 6
1 50 p/ 50V/ C0 G
1 0K 0.1 %
GN D_ AN A1
GN D_ AN A1
+5 VVB
+5 V
VP1 5_VB
+15 .0 V
U5 6
3
C8 21
1 00n /5 0V/X7R
1
I
Q
IN H
GND
GND
4
2
5
C 82 2
1 0u /16 V/X7R
TLE4 29 6GV5 0
GND _VB
Figure 35
GN D_ VB
DC Voltage Measurement
Application Note
40
V2.4, 2014-08-11
VA N A50
+5.0V
C 894
10n / 50 V/ X7R
V+
2
IN -A
O U TA
IN +A
3
GN D _ A N A1
R 204
opt
C 90 8
10 n/ 5 0V/ X7R
6
IN -B
O U TB
IN +B
7
GN D _ A N A1
5
Tem p5
C 909
V-
TE MP_I GBT_ W
4
A D 85 52A R Z
Tem p4
1u/ 16V/ X7R
GN D _AN A 1
R 206
R 20 5
10 K 5/1%
1
V AN A 50
+5 . 0V
R 2 03
1 0K 5/1%
8
GN D _A N A1
U 33
C 91 0
10 n/ 5 0V/ X7R
0R
G N D _ AN
GNAD1 _ A N A1
VA N A50
+5. 0V
0R
R 208
10K5/ 1%
C 895
Te m p2
R 21 0 op t
IN -A
OU TA
I N +A
GN D _AN A 1
op t
GN D _AN
GNAD1 _A N A1
5
C 91 4
10 n/50V / X7 R
GN D _A N A1
Tem p1
C 91 5
AD 855 2A R Z
Tem p0
GN D _AN A 1
R 21 3
10K5/ 1%
4
C 913
10n / 50 V/ X7R
1u / 1 6V/ X7R
R 214
VA N A50
+5.0V
6
V-
IN -B
OU TB
I N +B
1u/ 16V V/ X7R
2
3
R 209
10 K5/ 1%
8
Te m p3
C 912
R 2 12
7
TEMP _IGB T_ V
C 911
10n / 50 V/ X7R
GN D _AN A1
U 34
V+
1
TEMP _IGB T_ U
10 n/ 50V/ X7 R
VA N A5 0
+5. 0 V
R 2 11
1 0K5 / 1%
R 2 07
C 916
10n/50 V /X7R
0R
GN D _AGN
N A1
D _A N A 1
Figure 36
IGBT Module Temperature Measurement
Application Note
41
V2.4, 2014-08-11
3.8.2
Assembly Drawing
Figure 37
Assembly Drawing of the Driver Board (Top) - part 1
Application Note
42
V2.4, 2014-08-11
Figure 38
Assembly Drawing of the Driver Board (Top) - part 2
Application Note
43
V2.4, 2014-08-11
Figure 39
Assembly Drawing of the Driver Board (Bottom) - part 1
Application Note
44
V2.4, 2014-08-11
Figure 40
Assembly Drawing of the Driver Board (Bottom) - part 2
Application Note
45
V2.4, 2014-08-11
For detail information use the zoom function of your PDF viewer to zoom into the drawings on Figure 37,
Figure 38, Figure 39 and Figure 40.
3.8.3
Layout
Layout of the Driver Board is shown on Figure 41 (Top Layer), on Figure 42 (Layer 2), on Figure 43 (Layer 3),
on Figure 44 (Layer 4), on Figure 45 (Layer 5) and on Figure 46 (Bottom Layer).
Figure 41
Driver Board - Top Layer
Figure 42
Driver Board - Layer 2
Figure 43
Application Note
46
V2.4, 2014-08-11
Figure 44
Figure 45
Figure 46
Driver Board - Bottom Layer
Application Note
47
V2.4, 2014-08-11
3.8.4
Bill of Materials
Table 3
Bill of Materials for Hybrid Kit for the HybridPACK™2 Evaluation Driver Board
Reference
Value / Device
Package
C15_WT,C15_WB,C15_VT,C15_VB,C15_UT, 4u7/25V/X7R
C15_UB,C16_WT,C16_WB,C16_VT,C16_VB,
C16_UT,C16_UB,C20_WT,C20_WB,C20_VT,
C20_VB,C20_UT,C20_UB,C21_WT,C21_WB,
C21_VT,C21_VB,C21_UT,C21_UB,C868,C87
1,C874,C880,C885,C889
C1206
C17_WT,C17_WB,C17_VT,C17_VB,C17_UT, 100n/50V/X7R
C17_UB,C22_WT,C22_WB,C22_VT,C22_VB,
C22_UT,C22_UB,C23_WT,C23_WB,C23_VT,
C23_VB,C23_UT,C23_UB,C821
C0603
C79,C80,C81,C82,C83,C84
22n/50V/X7R
C0603
C822
10u/16V/X7R
C1206
C827,C830,C835,C891
100n/16V/X7R
C0402
C828,C831
150p/50V/C0G
C0402
C832
330p/50V/COG
C0402
C833,C881,C886,C894,C895
10n/50V/X7R
C0402
C866,C869,C872,C877,C882,C887
4u7/50V/X7R
C1210
C867,C870,C873,C879,C883,C888
22u/35V
EIA 7343-31 (Kemet D)
C875
4u7/50V/X7R
C1210
C876
100u/20V
C0810
C878
100nF/100V/X7R
C1206
C884
22n/50V/X7R
C0402
C890,C907
22u/16V/X7R
C1210
C896,C898,C899
10n/50V/X7R
C0603
C897,C906
100n/50V/X7R
C0805
C900,C901,C902,C903,C904,C905
100pF/100V/COG
C0603
C908,C910,C911,C913,C914,C916
10n/50V/X7R
C0603
C909,C915
1u/16V/X7R
C0603
C912
1u/16VV/X7R
C0603
D3_WT,D3_WB,D3_VT,D3_VB,D3_UT,D3_UB P6SMB510A
SMB
D4,D6,D8,D10,D11,D14,D16,D18
ES1A
DO214
D4_WT,D4_WB,D4_VT,D4_VB,D4_UT,D4_UB ES1D
DO214
D5,D7,D9,D13,D15,D17
DO214
1SMA5929BT3G
D6_WT,D6_WB,D6_VT,D6_VB,D6_UT,D6_UB MURA160T3G
DO214
D9_WT,D9_WB,D9_VT,D9_VB,D9_UT,D9_UB SMBJ14CA
SMB
D12
1SMB5935BT3
SMB
D19
BZV55/C13
SMD
Application Note
48
V2.4, 2014-08-11
Table 3
Bill of Materials for Hybrid Kit for the HybridPACK™2 Evaluation Driver Board (cont’d)
Reference
Value / Device
Package
D20
1SMB30AT3
SMB
D21,D22,D23
LED_LSM676-MQ
D0805
K1
MMS-112-01-L-DV
24POL
K1_opt,K2_opt,K3_opt,K4_opt,K5_opt,K6_opt
JST 09HVD6B-EMGF-NR
09HVD6B-EMGF-NR
L1
MURATA_BLM21P221SN
L0805
Q4
FS800R06KE3
HybridPACK™2
Q5
IPD144N06NG
TO252
Q10
IPD90P03P4L-04
TO252
Q11,Q12
BCR183S
SOT363
Q13
BCR10PN
SOT363
R14_WT,R14_WB,R14_VT,R14_VB,R14_UT,
R14_UB,R206,R207,R214
0R
R0603
R28_UB
1K
R0603
R28
10K
R0805
R29_UB
4K7
R0603
R31_UB
47R
R0805
R32_WT,R32_WB,R32_VT,R32_VB,R32_UT, 2R7
R32_UB,R33_WT,R33_WB,R33_VT,R33_VB,
R33_UT,R33_UB
R2512
R34_UB,R193
4k75
R0402
R82,R83,R84,R85,R86,R87,R182
10K
R0402
R127,R510
2K /0.1%
R0603
R132
4K / 0.1%
R0603
R133,R134,R135,R136,R137,R138
590K
R1206
R139
3K9
R0603
R145,R146
10K 0.1%
R0603
R169,R170,R171,R173,R174,R175,R178,R17 1k6
9,R180,R183,R185,R186,R190,R191,R192,R1
96,R197,R198
R1206
R184
80K6
R0402
R187
19K6
R0603
R194
0R025
R2010
R199,R533
0R
R1210
R201
59K
R0603
R203,R205,R208,R209,R211,R213
10K/1%
R0603
R204,R210,R212
opt
R0603
Application Note
49
V2.4, 2014-08-11
Table 3
Bill of Materials for Hybrid Kit for the HybridPACK™2 Evaluation Driver Board (cont’d)
Reference
Value / Device
Package
R408
158R
R0603
R509
39R
R0603
R511,R513,R515,R521,R523,R525,R527,R52 15k
9,R531
R0603
R512,R514,R516
1K
R0603
R517,R518,R519
220R
R0603
R520,R522,R524,R526,R528,R530
100R
R0603
R534
opt
R1210
R535
226K
R0603
R536
5K1
R0603
R537
47K
R0603
T1
TRANSFORMER2
T1_WT,T1_WB,T1_VT,T1_VB,T1_UT,T1_UB
ZXTN2010Z
SOT89
T2_WT,T2_WB,T2_VT,T2_VB,T2_UT,T2_UB
ZXTP2012Z
SOT89
U4,U5,U6,U7,U8,U9
1ED020I12-FA
PG-DSO-20
U18,U33,U34
AD8552ARZ
SO-8
U19
ACPL-782T
DIP-8
U30
LM3478MM
MSOP-8
U56
TLE4296GV50
SCT595
U57
74LVC1G11GW
SOT363
U58
MAX6457UKD3A-T
SOT23-5
Application Note
50
V2.4, 2014-08-11
Hybrid Kit for the HybridPACK™2 Logic Board
4
Logic Board contains all components for the control of the Hybrid Kit for the HybridPACK™2. Furthermore it
provides the interface for all the others elements which build a complete inverter system: motor interface (encoder,
resolver, GMR or hall sensor), current sense interface, communication (CAN and RS232) and additional analogue
and digital inputs/outputs. It is supported in 2 versions: version v1.2 on Figure 47 (not produced anymore) and
version v1.3b on Figure 48. Figure 49 shows the block structure of the Logic Board and the following chapters
describe these blocks in detail. Although the block structure shown on Figure 49 can be applied on both versions,
v1.2 and v1.3b are different in a few details. Comparing to v1.2 the Logic Board v1.3b is a further step in the
development of the Hybrid Kit that offers some new features to the customer - the most important is GMR interface
detailed described in Chapter 4.10.
New features on Logic Board v1.3b comparing to v1.2 are following:
•
•
•
•
•
•
•
•
•
•
On-Board (on the bottom of the Logical Board) temperature measurements (Figure 78);
Usage of Infineon Technologies TLE7368E Micro Controller Power Supply IC (Figure 63);
Added some reference power supply for MCU A/D converters;
Implemented parallel communication interface on resolver chip AD2S1200YST (IC8 on Figure 67) and added
belonging circuitry (see Figure 69);
Added more options for trimming the resolver signal and added test points for measuring resolver signals;
Implemented differential signaling to the encoder interface (instead of single ended interface as it was in v1.2);
Improved phase current sense filtering - adapted to filter signals up to 5kHZ cut-off frequency by means of
second order filter (Figure 74);
Adapted filtering on DC-Bus voltage measuring signals, temperature sensing signals, emulated encoder
outputs of resolver chip (Figure 74);
Removed one general purpose digital I/O due to leak of pins on the connector;
Due to added differential signaling and GMR interface the external interface 34-pin connector is replaced with
50-pin connector; (Figure 50 and Figure 51);
Application Note
51
V2.4, 2014-08-11
Figure 47
Hybrid Kit for the HybridPACK™2 Logic Board v1.2
Application Note
52
V2.4, 2014-08-11
Figure 48
Hybrid Kit for the HybridPACK™2 Logic Board v1.3b
Debug
Connector
Logic Board
Supply
Watchdog
Supply
t
o
r
C
o
PWM
n
n
VDC Meas.
e
c Temp. IGBT (x3)
FAULT
Signals
RST
C
o
n
n
e
c
t
Microcontroller
TC1767
Encoder
Other Sensor
CAN / RS232
Level
Shifter
o
r
EEPROM
VDC, Temp
I, U, V Current
Measurement
Resolver
Interface
Resolver
Driver Board
HybridPACK
TM
Connector
2
Current U
CAN RS232
A/D IO Supply
Current V
Current W
Encoder
Resolver
Other sensor
Figure 49
Block Diagram of the Logic Board
Application Note
53
V2.4, 2014-08-11
4.1
External Connector Pin Assignment
Logic Board external connector X1-SIG1 (Harwin M80-5123442 on Logic Board v1.2) or K2 (Harwin M805125042P on Logic Board v1.3b) provides the interface to all the external systems: motor (encoder, resolver, Hall
sensor or GMR), current sense, communication (CAN and RS232) and extra analogue and digital inputs/outputs.
Figure 50 and Table 4 are showing the pin assignment of the connector X1-SIG1 for the Logic Board v1.2.
Figure 51 and Table 5 are showing the pin assignment of the connector K2 for the Logic Board v1.3b. The female
part for 34-pin connector Harwin M80-5123442 (Logic Board v1.2) is socket Harwin M80-4603442. The female
part for 50-pin connector Harwin M80-5125042P (Logic Board v1.3b) is socket Harwin M80-4605042.
StatorTemp
PosA
PosB
PosZ
PosU
PosV
PosW
S2
S6
S3
S1
R1
R2
DIO_1
DIO_2
DIO_3
DIO_4
2
1
ADC_IN1
4
3
ADC_IN2
6
5
ADC_IN3
8
7
10
9
12
11
14
13
16
15
Motor Interface
(Encoder)
Motor Interface
(Hall Sensor)
+12.0V
+12.0V
GND_DIG1
Motor Interface
(Resolver)
Phase Current
Sense
VANA5.0
GND_ANA1
Communication
I_U
18
17
20
19
22
21
I_W
24
23
VDIG5.0
26
25
GND_DIG1
28
27
30
29
32
31
34
33
I_V
General Purpose
Ana/Dig IN/OUT
Power Supply
CAN1_L
CAN1_H
ASC_TX
ASC_RX
Bottom View on Crimp Connector M80-4603442 (counterpart on Logic Board v1.2 M80-5123442)
Figure 50
External Connector Pin Assignment Logic Board v1.2
Table 4
External Connection Pin Assignment Logic Board v1.2
Pin Number
Pin Name
Type
Description
1
ADC_IN1
I/O
General Purpose Analog I/O
2
StatorTemp
Input
Motor Temperature Measurement
3
ADC_IN2
I/O
4
PosA
Input
Encoder Phase A
Application Note
54
V2.4, 2014-08-11
Table 4
External Connection Pin Assignment Logic Board v1.2
Pin Number
Pin Name
Type
Description
5
ADC_IN3
I/O
6
PosB
Input
Encoder Phase B
7
KL_30_IN
Supply +12.0V Power Supply
8
PosZ
Input
9
KL_30_IN
10
PosU
Input
11
GND_DIG1
Supply Digital Ground
12
PosV
Input
13
VANA50
Supply +5.0V Analog Power Supply
14
PosW
Input
15
GND_ANA1
Supply Analog Ground
16
S2
Input
Resolver Sine (high)
17
I_U
Input
Current Sense Phase U
18
S6
Input
Resolver Sine (low)
19
I_V
Input
Current Sense Phase V
20
S3
Input
Resolver Cosine (high)
21
I_W
Input
Current Sense Phase W
22
S1
Input
Resolver Cosine (low)
23
VDIG50
Supply +5.0V Digital Power Supply
24
R1
Output Resolver Excitation (high)
25
GND_DIG1
26
R2
Output Resolver Excitation (low)
27
CAN1_L
I/O
Low line I/O CAN Signal
28
DIO1
I/O
General Purpose Digital I/O
29
CAN1_H
I/O
High line I/O CAN Signal
30
DIO2
I/O
31
ASC_TX
Output RS-232 Transmitter Output
32
DIO3
I/O
33
ASC_RX
Input
RS-232 Receiver Input
34
DIO4
I/O
Application Note
Encoder Phase Z - index
Hall Sensor Phase U
Hall Sensor Phase V
Hall sensor Phase W
55
V2.4, 2014-08-11
S2
2
1
ADC_IN1
S6
4
3
ADC_IN2
S3
6
5
ADC_IN3
S1
8
7
StatorTemp
10
9
12
11
R1
R2
VANA50
GND_ANA1
DIO_1
DIO_2
14
13
16
15
18
17
20
19
I_W
22
21
iGMR_CSn+
24
23
iGMR_DATA-
26
25
28
27
30
29
32
31
34
33
36
35
PosZ/iGMR_Z+
38
37
PosZ/iGMR_Z-
40
39
PosU/iGMR_U
42
41
PosV/iGMR_V
44
43
PosW/iGMR_W
46
45
48
47
50
49
GND_ANA1
I_U
I_V
iGMR_DATA+
iGMR_CLKiGMR_CLK+
CAN1_L
CAN1_H
ASC_TX
ASC_RX
GND_DIG1
+12V
+12V
GND_DIG1
GND_DIG1
DIO_3
VDIG50
GND_DIG1
iGMR_CSniGMR_Ren_DE+
Motor Interface
(Resolver)
Motor Interface
(Encoder)
Motor Interface
(Hall Sensor)
Motor Interface
(iGMR Sensor)
Phase Current
Sense
Communication
General Purpose
Ana/Dig IN/OUT
iGMR_Ren_DEPosA/iGMR_A+
PosA/iGMR_A-
Power Supply
Not Connected
PosB/iGMR_B+
PosB/iGMR_B-
GND_DIG1
VDIG50
Bottom View on Crimp Connector M80-4605042 (counterpart on Logic Board v1.3b M80-5125042P)
Figure 51
External Connector Pin Assignment Logic Board v1.3b
Application Note
56
V2.4, 2014-08-11
Table 5
Pin Number
Pin Name
Type
Description
1
ADC_IN1
I/O
2
S2
Input
Resolver Sine (high)
3
ADC_IN2
I/O
4
S6
Input
Resolver Sine (low)
5
ADC_IN3
I/O
6
S3
Input
Resolver Cosine (high)
7
StatorTemp
Input
Motor Temperature Measurement
8
S1
Input
Resolver Cosine (low)
9
GND_ANA1
10
R1
Output Resolver Excitation (high)
11
DIO1
I/O
12
R2
Output Resolver Excitation (low)
13
DIO2
I/O
14
VANA50
Supply +5.0V Analog Power Supply
15
DIO3
I/O
16
GND_ANA1
17
VDIG50
18
I_U
Input
19
GND_DIG1
20
I_V
Input
21
iGMR_CSn-
Output iGMR Chip Select (differential signal)
22
I_W
Input
23
iGMR_REn_DE+
Output iGMR Read Enable (differential signal)
24
iGMR_CSn+
Output iGMR Chip Select (differential signal)
25
iGMR_REn_DE-
Output iGMR Read Enable (differential signal)
26
iGMR_DATA-
I/O
iGMR Data (differential signal)
27
PosA/iGMR_A+
Input
Encoder Phase A (differential signal)
28
iGMR_DATA+
I/O
iGMR Data (differential signal)
29
PosA/iGMR_A-
Input
Encoder Phase A (differential signal)
30
iGMR_CLK-
Output iGMR SSC Clock (differential signal)
31
PosB/iGMR_B+
Input
32
iGMR_CLK+
Output iGMR SSC Clock (differential signal)
33
PosB/iGMR_B-
Input
Encoder Phase B (differential signal)
34
CAN1_L
I/O
Low line I/O CAN Signal
35
PosZ/iGMR_Z+
Input
Encoder Phase Z - index (differential signal)
36
CAN1_H
I/O
High line I/O CAN Signal
37
PosZ/iGMR_Z-
Input
Encoder Phase Z - index (differential signal)
38
ASC_TX
Output RS-232 Transmitter Output
Application Note
Current Sense Phase U
Current Sense Phase V
Current Sense Phase W
Encoder Phase B (differential signal)
57
V2.4, 2014-08-11
Table 5
Pin Number
Pin Name
Type
Description
39
PosU/iGMR_U
Input
Hall Sensor Phase U
40
ASC_RX
Input
RS-232 Receiver Input
41
PosV/iGMR_V
Input
Hall Sensor Phase V
42
GND_DIG1
43
PosW/iGMR_W
Input
44
KL_30_IN
45
GND_DIG1
46
KL_30_IN
47
VDIG50
48
GND_DIG1
49
NC
NC
50
GND_DIG1
4.2
Hall Sensor Phase W
Not Connected
Connector to the Driver Board (K1)
See Chapter 3.3.
4.3
Power Supply
The complete system (Driver Board and Logic Board) must to be supplied with and external DC power supply
connected to connector X1-SIG1 on the Logic Board v1.2 or K2 on the Logic Board. On the Logic Board v1.2 +12V
power supply should be connected to the pins 7 and 9 of X1-SIG1 and GND_DIG1 on pins 11 and 25 of X1-SIG1.
On the Logic Board v1.3b +12V power supply should be connected to the pins 44 and 46 of K2 and GND_DIG1
on pins 19, 42, 45, 48 and 50 of K2. The input voltage should be kept between 7V and 18V and the current
consumption will vary depending on different factors, i.e. PWM frequency.
This supply line will be forwarded to the Driver Board through the connector K1 (pins 1, 2 and 3 for +12V). On both
boards a protection circuit will avoid damages in the case of overvoltage or wrong polarity (see Figure 52).
KL _30_ IN
+12. 0V
Q4
I PD 90P03 P4L-04
KL _30
+12. 0V
D2
BZ V55/ C 13
R 128
10K
GN D _D I G1
Figure 52
D3
1SMB 30AT3
GN D _D I G1
Overvoltage and Wrong Polarity Protection Circuit (same for Logic Board v1.2 and v1.3b)
The supply block (see Figure 62 for Logic Board v1.2 and Figure 63 for Logic Board v1.3b) generates all
necessary voltages for the components on the logic board (5V, 3.3V and 1.5V). Furthermore the 5V (analogue and
digital) are connected to the external connector (X1-SIG1/K2) for supplying external systems (i.e. current sensor).
Application Note
58
V2.4, 2014-08-11
On the Logic Board v1.2 the power-on sequence for the supply signals will be following (see Figure 62): after
applying the main power supply for the system (+12V) the IC U13 will be switched-on. As soon as
VANA50/VDIG50 (VOUT of IC U13) reaches the correct level the signal RO will activate IC U14 and VDIG15 will
be generated. After that the RESET output of IC U14 will turn-on IC U12 (VDIG33/VANA33). Finally the signal
POWERrstn (RESET output of IC U12) will be activated waking-up the microcontroller.
For the Logic Board v1.3b is used Infineon Technologies TLE7368E Micro Controller Power Supply IC. After
applying the main power supply the IC13 will be switched-on (Figure 63). As soon as 5V/3.3V/1.5V power supplies
reached their correct values the signal POWERrstn (RO_1 and RO_2 outputs of IC12) will be activated wakingup the microcontroller.
4.4
Microcontroller
The microcontroller block (uC block overview is given in Figure 71 for Logic Board v1.2 and in Figure 72 for Logic
Board v1.3b) contains following elements:
•
TC1767 (Logic Board v1.2 on Figure 75 and Logic Board v1.3b on Figure 76) is a 32-Bit Microcontroller
member of the Infineon Technologies AUDO FUTURE product family designed for automotive applications.
TriCoreTM CPU providing high-end microcontroller performance combined with sophisticated DSP capabilities
(please refer to datasheet for further details);
•
Input filter (see Figure 73 for Logic Board v1.2 and Figure 74 for Logic Board v1.3b): passive filters for digital
and analogue signals and voltage dividers for voltage level adaptation;
•
EEPROM (Figure 77): 256kB Electrically-Erasable Programmable Read-Only Memory optimized for use in
automotive applications where low-power and low-voltage operations are essential (for more details refer to
AT25256A-10TQ-2.7 datasheet). The communication with the microcontroller is done through SSC0 interface
(high-speed synchronous serial interface, SPI-compatible);
•
RS-232 (pins ASC_TX and ASC_RX on connector X1-SIG1/K2) & CAN (pins CAN1_H and CAN1_L on
connector X1-SIG1/K2) Transceivers (see Figure 71 for Logic Board v1.2 and Figure 72 for Logic Board
v1.3b);
•
Possibility to connect debugging systems like Lauterbach to the JTAG connector K3-OCDS (Header 8X2) please refer to Figure 64;
4.4.1
Configuration of TC1767
The TC1767 can be configured with the respect to the different boot modes and with the respect to the different
interfaces (serial/parallel) to the resolver and iGMR position sensors.
4.4.1.1
Boot Configuration of TC1767
Figure 53
HW Boot Configuration of TC1767 DIP-Switch
The picture above (Figure 53) shows the definition of the boot HW configuration switch (DIP-Switch SW1 on
Figure 76). The meaning of the switches will be described in the following Table 6.
The ON position of the switch is equal to a logical LOW at the dedicated pin.
Application Note
59
V2.4, 2014-08-11
Table 6
User Startup Modes for TC1767
CFG[7...0]
11)
Type of Boot TC1767
2
3
OFF OFF X
3)
4
5
6
7
8
X
X
OFF ON
X
X
X
OFF ON
ON
11XXX10X
Internal Start from Flash
010XX100
Bootstrap Loader Mode, Generic Bootloader at ON
CAN pins
10101100
Bootstrap Loader Mode, ASC Bootloader
OFF ON
OFF ON
OFF OFF ON
ON
10100100
Alternate Boot Mode, ASC Bootloader on fail
OFF ON
OFF ON
ON
OFF ON
ON
1011X10X
Alternate Boot Mode, Generic Bootloader at
CAN pins on fail
OFF ON
OFF OFF X
OFF ON
X
all others
reserved; don’t use this combination
2)
OFF ON
1) 1 to 8 are the DIP-Switch numbers (SW1 on Figure 54)
2) The shadowed line indicates the default settings.
3) ’x’ represents the don’t care state.
4.4.1.2
Selecting Serial/Parallel Interface
DIP-4 switch (SW2 on Figure 72) is used to select serial/parallel interface for the communication with resolver or
iGMR position sensor - please refer to Table 7.
Table 7
Selecting Serial/Parallel Interface
SW2[4...1]
Inetrface to the Resolver/iGMR
41)
00002)
iGMR enabled (SPI and Incremental mode)
Resolver in Parallel Mode
1111
Resolver in Serial Mode
iGMR disabled
all others
reserved; don’t use this combination
3
2
1
OFF3) OFF
OFF
OFF
ON
ON
ON
ON
1) 1 to 4 are the DIP-Switch numbers
2) 0 is equal to open switch, “1” is equal to closed switch
3) ’x’ represents the don’t care state.
Figure 54
The Boot Configuration Switch (SW1) and Serial/Parallel Interface Select Switch (SW2)
Application Note
60
V2.4, 2014-08-11
4.5
Watchdog
The Logic Board contains a pin-selectable watchdog timer that supervises the microcontroller activity and
signalizes when the system is operating improperly. During normal operation, the microcontroller (GPTA39)
should repeatedly toggle the watchdog input (WDI, see Figure 65) before the selected watchdog time-out period
elapses to report that the system is processing code properly. If this does not occurs, the supervisor asserts a
watchdog output (WDO) which will reset the microcontroller via PORSTn (external power-on hardware reset).
The state of the three logic control pins (SET0, SET1 and SET2) determines watchdog timing characteristics (see
table in Figure 65). The jumper J1 allows disabling the watchdog functionality in a very easy way.
4.6
Phase Current Sensing
Phase current sensing signals should be connected to the Logic Board connector X1-SIG1/K2 to the pins I_U, I_V
and I_W (Figure 73 for the Logic Board v1.2 and Figure 74 for the Logic Board v1.3b). The Logic Board is
designed to work with current transducers (not provided with the Hybrid Kit) with voltage output proportional to the
current (usually deploying Hall effect - like LEM sensors). User can take +5V (analog) available on the X1-SIG1/K2
pins to supply current transducers. The exact type of current transducer will be depend on many parameters in
application, but usually the most important is the motor current consumption. Please notice that if you control 3phase balanced synchronous system it is enough to measure just 2 phases, since the 3rd phase current can be
calculated as algebraic combination out of the 2 measured currents.
4.7
Resolver Interface
The Logic Board includes a 12-Bit Resolver-to-digital converter (meaning A/D converter) which integrates an onboard programmable sinusoidal oscillator that provides sine wave excitation for resolvers (pins R1 and R2 on
connector X1-SIG1/K2). For more details please refer to the data sheet of the component (AD2S1200YST) and
the schematics of the circuit - for Logic Board v1.2 see Figure 66 and for Logic Board v1.3b see Figure 67. With
resistors (R155, R156, R157, R158, R159 and R160) user can trim the LMH6672 (dual op-amp) output voltage
values (resolver excitation). On the Logic Board v1.3b is given additional possibility to trim the resolver excitation
with potentiometers (R483, R484, R485 - not populated, user should solder them if needed). Please refer to data
sheet of used resolver to trim this values properly. The resolver response should be connected between pins S1
and S3 (sine) and S2 and S6 (cosine) on the connector X1-SIG1/K2.
4.8
Encoder Interface
If encoder is used as a sensor for the motor position/speed sensing the following pins on connector X1-SIG1/K2
should be connected: the phase A should be connected to pin PosA (Logic Board v1.2) or between pins
PosA/iGMR_A+ and PosA/iGMR_A- (Logic Board v1.3), the phase B should be connected to pin PosB (Logic
Board v1.2) or between pins PosB/iGMR_B+ and PosB/iGMR_B- (Logic Board v1.3b) and phase Z (index or zero
marker) should be connected to pin PosZ (Logic Board v1.2) or between pins PosZ/iGMR_Z+ and PosZ/iGMR_Z(Logic Board v1.3b).
4.9
Hall Sensor Interface
If Hall sensor is used as a sensor for the motor position/speed sensing the following pins on connector X1-SIG1/K2
should be connected: the phase U should be connected to pin PosU (Logic Board v1.2) or to pin PosU/iGMR_U
(Logic Board v1.3b), the phase V should be connected to pin PosV (Logic Board v1.2) or to pin PosV/iGMR_V
(Logic Board v1.3b) and phase W should be connected to pin PosW (Logic Board v1.2) or to pin PosW/iGMR_W
(Logic Board v1.3b).
Application Note
61
V2.4, 2014-08-11
4.10
GMR Interface
As mentioned on the beginning of the Chapter 4, the Logic Board v1.3b supports GMR interface by means of a
bi-directional SSC (SPI compatible), encoder (or incremental) and Hall sensor interface. It is explicitly
recommended to use Infineon Technologies TLE5012 GMR-based angular sensor for rotor position sensing. The
TLE 5012 is a 360° angle sensor that detects the orientation of a magnetic field. This is achieved by measuring
sine and cosine angle components with monolithic integrated Giant Magneto Resistance. For more details about
TLE5012 please refer to the data sheets on Infineon Technologies internet pages.
V D I G33
+ 3.3 V
C 11 27
GN D _D I G1
GN D _D I G 1
C 1128
10p/ 16V / X7R
iGM R _D ATA +
C 1129
iGM R _D ATA -
4
R 488
1K
VD I G33
+3. 3V
R 447
100R
7
6
GN D _D I G1
C 1130
10 p/1 6V/ X7 R
G N D _D I G1
GN D _D I G1
GN D _D I G1
I C 32
4
12
1
iG MR _ C LK _uC
7
V D I G33
+ 3.3 V
9
C 11 31
3
iG MR _ C S _uC
R 4 89
1K
R 4 90
1K
2A
1Y
2Y
E N*
D ou t1+
D i n1
D out 1D ou t2+
D i n2
D out 2D ou t3+
D i n3
D out 3D ou t4+
D i n4
G ND
100n/ 16 V/ X7R
74LV C 2G 04GW
EN
6
D out 4-
2
iG MR _C LK +
3
iG MR _C LK -
6
iG MR _R E n_D E +
5
iG MR _R E n_D E -
10
iG MR _C S n+
11
iG MR _C S n-
14
13
8
V CC
1A
GN D
1
iG MR _ R E _uC
15
100n/ 16V / X7R
4
D S90 LV03 1A
G N D _ D I G1
2
I C 28
5
GN D _D IG 1
16
V CC
DIN
R O U T D O/ R I +
D O/ R I DE
RE
Vcc
1
5
iGM R _I N D EX _uC
D S 92LV 010
GN D
2
3
iG MR _D I _uC
iGM R _R O U T_uC
8
100n/ 16 V/ X7R
I C 26
G N D _D I G1
G N D _ D I G1 G N D _D I G1
Figure 55
GMR SSC Interface (Logic Board v1.3b only)
4.10.1
GMR SSC Interface Mode
The schematics of SSC interface on the Logic Board is shown on Figure 55. Signals on connector X1-SIG/K2 that
are used for SSC interface are: iGMR_CSn+/iGMR_CSn- (Chip Select, differential signals),
iGMR_REn_DE+/iGMR_REn_DE- (Read Enable, differential signals), iGMR_DATA+/iGMR_DATA- (Serial Data,
differential signals) and iGMR_CLK+/iGMR_CLK- (SSC Clock, differential signals) - all signals are listed in
Table 5. On Figure 56 is presented the schematics of possible technical solution (implemented by Infineon
Technologies System Engineering) for usage of TLE5012. The PCB with TLE5012 and a few additional
components is mounted perpendicular to the electric motor shaft - just as shown on Figure 57. The TLE5012 is
on the opposite side of the PCB - next to the motor shaft.
Application Note
62
V2.4, 2014-08-11
U1
3
5
R in1 +
Ro ut 1
R in1 -
R in2 +
Ro ut 2
R in2 -
11
R4
1k
0 60 3
U2
6
VDD SC K
CSQ
DATA
C LK
I FA
I FB
1
7
13
U3
2
3
VCC
4
2
5
8
1
5
3
D O+
D in
D O-
8
16
4
7
12
8
6
R in3 +
Ro ut 3
R in3 -
R in4 +
Ro ut 4
R in4 -
2
R1
10 0R
06 03
R2
10 0R
06 03
R9
R 10
R1 1
3k 3
06 03
3 k3
0 60 3
3k 3
06 03
1
6
7
X15
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
9
R3
10 0R
14
06 03
15
VCC
EN
EN_ n
GN D
DE
RE
R ou t
R6
R7
R8
3k 3
06 03
3 k3
0 60 3
3k 3
06 03
D S9 0C 03 2BTM
G ND
TL E5 01 2
G ND
H ea de r_ 7x2
4
R5
5 4R
DS9 2LV0 10 ATM
06 03
U4
12
8
3Y
3Z
4A
4Y
4Z
10
11
14
13
VCC
G
G
GN D
AM26 LS3 1C DR
Figure 56
GMR SSC Interface - Proposal Using TLE5012
Figure 57
Picture of Possible Physical Implementation of the GMR Sensor
Application Note
0 60 3
3A
6
5
C6
16
4
2Y
2Z
10p /2 5V/ X7R
15
2A
2
3
06 03
0 60 3
C5
10 0n/ 16 V/X7 R/EMK1 07 B710 4KA
06 03
C4
1 00n /1 6V/ X7R /EMK10 7B7 104 KA
0 60 3
C3
10 0n/ 16 V/X7 R/ EMK1 07 B710 4KA
1 206
C2
1 0u /1 0V/X7 R/ LMK31 6B7 10 6KL
06 03
C1
10 0n /1 6V/ X7R/ EMK10 7B71 04 KA
9
1Y
1Z
C7
7
1A
1 0p/ 25 V/X7 R
1
63
V2.4, 2014-08-11
4.10.2
GMR Encoder Interface Mode
Infineon Technologies iGMR sensor TLE5012 can be used with encoder interface as well. This working mode is
referred as IIF Interface mode in theTLE5012 data sheet. To avoid signal integrity and EMC problems, within
Hybrid Kit it is expected that the 2 phase signals (A and B) and zero (index) signal are provided differentially. On
the connector X1_SIG (Figure 51) encoder inputs are: PosA/iGMR_A+ and PosA/iGMR_A (phase A),
PosB/iGMR_B+ and PosB/iGMR_B (phase B) and PosZ/iGMR_Z and PosZ/iGMR_Z (phase Z - index) - please
refer to the Table 5. Please refer to the TLE5012 data sheet to get iGMR sensor running in incremental mode.
4.10.3
GMR Hall Sensor Interface Mode
TLE5012 supports Hall sensor interface mode as well (iGMR emulates Hall sensor mode). For this purpose to the
connector X1-SIG/K2 inputs PosU/iGMR_U (phase U), PosV/iGMR_V (phase V) and PosW/iGMR_W (phase W)
should be connected. Please notice (on Figure 74) that the pull-up resistors to 3.3V (R491, R492 and R493) are
already provided on the Logic Board. For more details on Hall sensor mode please refer to the TLE5012 data
sheet.
4.11
Definition of Layers for the Logic Board
The Logic Board was made keeping the following rules for the copper thickness and the space between different
layers shown in Figure 58 for the Logic Board v1.2 (4 layers) and Figure 59 for the Logic Board v1.3b (6 layers).
Copper
Isolation
1: 35 µm / 1 oz.
1-2: 0.5 mm
2: 35 µm / 1 oz.
2-3: 0.5 mm
3: 35 µm / 1 oz.
3-4: 0.5 mm
4: 35 µm / 1 oz.
Figure 58
Definition of the Layers for the Logic Board v1.2
1
Copper
1
2
1: 35 µm
2
2: 35 µm
3
3: 35 µm
4
4: 35 µm
5
5: 35 µm
6
Figure 59
6: 35 µm
3
4
5
Isolation
1-2: 0.5 mm
2-3: 0.5 mm
3-4: 0.5 mm
4-5: 0.5 mm
5-6: 0.5 mm
6
Definition of the Layers for the Logic Board v1.3b
Application Note
64
V2.4, 2014-08-11
4.12
Schematics, Layout and Bill of Materials
To meet the individual customer requirements and to make the Logic Board for the HybridPACKTM2 module as a
platform for development or modifications, all necessary technical data like schematics, layout and components
for the Logic Board are included in this chapter.
4.12.1
Schematics
OC DS1
uC
TD O
TD I
TMS
TC K
TR STn
BR KIN n
BR KOU Tn
TD O
TD I
TMS
TCK
TRSTn
BR KIN n
BR KOUTn
TD O
TD I
TMS
TC K
TR STn
BR KI Nn
BR KOUTn
R es e tn
R es et n
R esetn
DEB UG
WDO WDI
WDI
W ATCH D OG
W ATCH D OG
C ON N ECTOR_ Driv erBo ar d
LEV EL_SH IFTER
POW ER rs t n
SUP PLY
CONN EC TOR
I _U
I _V
I _W
I _U
I_V
I _W
I _U
I _V
I _W
C AN 1_L
C AN 1_H
ASC _ TX
ASC _ RX
C AN1 _L
C AN1_H
A SC_ TX
A SC_RX
Resolv er
S1
S3
S2
S6
R1
R2
AD C _I N1
AD C _I N2
AD C _I N3
St atorTem p
Po s A
Po s B
Po s Z
Po s U
Po s V
Po s W
A
B
NM
A
B
NM
S1
S3
S2
S6
R1
R2
R esolv e r
SAMPLE
R ESETn
C Sn
RD n
SO
SC LK
RD VELn
FS1
FS2
D OS
LOT
SA MPLE
R ESETn_res
R Dn
SO
SC L K
R D VEL
FS 1
FS 2
A
B
NM
SA MPLE
R esetn_R es
SL S01
MR ST1
SC L K1
R D VEL
FS 1
FS 2
FL T_Un
FL T_Vn
FLT_ Wn
F LT_n
R STn
PWMU T_uc
PWMU B_uc
PWMVT_u c
PWMVB_uc
PWMW T_uc
PWMW B_uc
FLTUn _uc
FLTVn _uc
FLTWn_ uc
RSTn_ uc
PW MU T_uC
PW MU B_uC
PW MVT_ uC
PW MVB _uC
PW MW T_u C
PW MW B_uC
PWMU T
PW MU B
PW MV T
PWMVB
PWMW T
PW MW B
PW MUT
PW MUB
PW MVT
PW MVB
PW MWT
PW MWB
FLTU n_u C
FLTVn_uC
FLTW n_uC
FLTn_u C
R ST_ IN n _uC
FLTU n
FLTV n
FLTW n
FLTn
R ST_I N n
FLTUn
FLTVn
FLTWn
FLTn
R ST_I Nn
LEV EL_SH IFTER
VD C_uC
TE MP_IGBT_W
TE MP_IGBT_U
TEMP_I GBT_V
TEMP_Board
VD C
TEMP_H P2_W
TEMP_H P2_U
TEMP_H P2_V
TEMP_BOAR D
C ON N ECTOR_ Driv erBo ar d
D OS
LOT
AD C _I N1
AD C _I N2
AD C _I N3
D IO_1
D IO_2
D IO_3
D IO_4
D I O_1
D I O_2
D I O_3
D I O_4
uC
CON NEC TOR
Figure 60
C AN 1_L
C AN 1_H
AS CTX
AS CR X
St at orTemp
PosA
PosB
PosZ
PosU
PosV
PosW
St at o rTemp
Pos A
Pos B
Pos Z
PosU
Pos V
PosW
S1
S3
S2
S6
R1
R2
PW MU Tn
PW MUBn
PW MVTn
PW MVBn
PWMW Tn
PW MWBn
SUPPL Y
Schematics Block Overview Logic Board v1.2
Application Note
65
V2.4, 2014-08-11
O CD S 1
uC
TD
TD
TM
TC
TR
BR
BR
T DO
TD I
TM S
TC K
T RS T n
B R K INn
B RK O UT n
O
I
S
K
S Tn
KIN n
KO UT n
T DO
T DI
T MS
T CK
T R S Tn
BR KIN n
B R K OU T n
R e se t n
R e se t n
R es e t n
W A TC H D OG
DE BUG
W DO W D I
WD I
W A TC H D OG
SU PPL Y
P OW E R rs t n
C ON N E C TO R
S U P P LY
P os A / i G MR _A +
P o s A / i GM R _ A P os B / i G MR _B +
P o s B / i GM R _ B P os Z / i G MR _Z +
P o s Z / i GM R _ Z -
P o s A / i GM
P o s A / i GM
P o s B / i GM
P o s B / i GM
P o s Z / i GM
P o s Z / i GM
R_ A +
R_ A R_ B +
R_ B R_ Z +
R_ Z -
P o s A / i GM
P o s A / i GM
P o s B / i GM
P o s B / i GM
P o s Z / i GM
P o s Z / i GM
Po s U/ G
i MR _ U
P o sU / i GM R _ U
P W MU Tn
P W M UBn
P W MV Tn
P W MV B n
P W MW Tn
P W MW B n
P o s V / i GM R _ V
P o s W / i GM R _ W
C ON N E C T OR _D ri v er B oa rd
L E V E L_ S H I F T E R
P o s U / i G MR _U
R_ A+
R_ AR_ B+
R_ BR_ Z +
R_ Z -
PW M
PW M
PW M
PW M
PW M
PW M
U T _ uc
UB_ u c
V T_ u c
V B _ uc
W T _u c
W B _ uc
P W MU T _u C
P W MU B _ u C
P W MV T_ u C
P W MV B _u C
P W MW T_ u C
P W MW B _ uC
P W MU T
P W M UB
P W MV T
P W MV B
P W MW T
P W MW B
P
P
P
P
P
P
W MU T
W MU B
W MV T
W MV B
W MW T
W MW B
F L TU n _u C
F L TV n _ u C
F L TW n_ u C
F L Tn _ u C
RS T _ INn _ u C
F LT U n
F L TV n
F L TW n
FL Tn
R S T_ I N n
F
F
F
F
R
LT U n
LT V n
LT W n
LT n
ST _ INn
G
i MR
i GM R _ D A TA +
G
i MR _ D A T A i GM R _ C LK +
i GM R _ C L K i GM R _ C S n +
i GM R _ C S n G
i MR _ R E n _ D E +
i G MR _R E n _ D E -
i GM
i GM
i GM
i GM
i GM
i GM
i GM
i GM
I_ U
I_ V
I_ W
i GM
i GM
i GM
i GM
i GM
i GM
R es o l v e r
S
S
S
S
R
R
1
3
2
6
1
2
S
S
S
S
R
R
A
1
B
3
N M
2
6 A D 2 S 12 0 0 _ S A MP L E n
1 A D 2 S 1 20 0 _ R E S E Tn
2
A D 2 S 1 20 0 _ C S n
A D 2S 12 0 0 _S OE
A D 2S 1 2 0 0 _R D V E Ln
A D 2 S 1 2 0 0_ F S 1
A D 2 S 1 2 0 0_ F S 2
F LT _ U n
F L T_ V n
F L T_ W n
F L T _n
R S Tn
R _ D I _ uC
R _ R OU T_ u C
R _ C LK _u C
R _ C S _ uC
R _ R E _ uC
R_ IN DEX _ u C
F L TU n _u c
F L TV n_ u c
F L TW n_ u c
F L Tn _ u C
R S T n _ uc
L E V E L_ S H I F T E R
i GM R
I_ U
I_ V
I_ W
C A N1 _ L
C A N1 _ H
ASC T X
AS C RX
S t a t or Te m p
S t a t o rT e m p
1
3
2
6
1
2
i G MR _D I _ uC
G
i MR _ R O U T _ uC
G
i MR _ C L K _ uC
i G MR _C S _ uC
i G MR _R E _ uC
i GM R _ I N D E X _ uC
C A N 1 _L
C A N 1 _H
A SC_ T X
A SC_ R X
CAN 1 _ L
C AN1 _ H
ASC _ T X
A SC_ R X
S
S
S
S
R
R
R_ DAT A+
R_ DAT AR_ CL K +
R_ CL K R_ CSn +
R_ CSn R_ REn _ DE +
R_ REn _ DE I_ U
I_ V
I_ W
V D C_ u C
V D C _u C
V DC
S t a t o rT e m p
A
B
NM
A
B
N M
A D 2 S 1 2 0 0_ S A M P L E n _u C
A D 2 S 1 2 0 0_ R E S E T n _u C
T E M P _ I GB T _ W
T E MP _I G B T _ U
T E M P _ I GB T _ V
T E M P _ HP 2 _ W
T E M P _ HP 2 _ U
T E M P _ HP 2 _ V
T E MP _ B O A R D
A D 2 S 1 20 0 _ S A MP LE _ u C
A D 2 S 1 20 0 _ R E S E Tn _ u C
A D 2 S 1 2 0 0_ C S n_ u C
A D 2 S 1 2 0 0_ S O E _ uC
A D 2 S 1 20 0 _ C S n _ u C
A D 2 S 1 20 0 _ S OE _ u C
A D 2 S 1 2 0 0_ R D V E L n _ uC
A D 2 S 1 2 0 0_ F S 1 _ u C
A D 2 S 1 2 0 0_ F S 2 _ u C
T E M P _ B oa rd
T e mp _ B o a rd
C ON N E C T OR _D ri v er B oa rd
A D 2 S 1 20 0 _ R D V E L n_ u C
A D 2 S 1 20 0 _ F S 1 _u C
A D 2 S 1 20 0 _ F S 2 _u C
LE V E L_ S H I F T E R _ R E S OL V E R
T E MP _ B O A R D
A D 2 S 1 2 00 _ D OS
A D 2 S 1 2 0 0_ L OT
A D 2 S 12 0 0 _ D B 1 1 _ S O
A D 2 S 1 20 0 _ D B 1 0 _ S C L K
A D 2 S 1 20 0 _ D B 9
A D 2 S 1 20 0 _ D B 8
A D 2 S 1 20 0 _ D B 7
A D 2 S 1 20 0 _ D B 6
A D 2 S 1 20 0 _ D B 5
A D 2 S 1 20 0 _ D B 4
A D 2 S 1 20 0 _ D B 3
A D 2 S 1 20 0 _ D B 2
A D 2 S 1 20 0 _ D B 1
A D 2 S 1 20 0 _ D B 0
R es o l v e r
A D 2 S 1 2 0 0_ D OS
A D 2 S 1 2 0 0_ L OT
A D 2 S 1 2 0 0_ D B 11 _ S O
A D 2 S 1 2 0 0_ D B 10 _ S C LK
A D 2 S 1 2 0 0_ D B 9
A D 2 S 1 2 0 0_ D B 8
A D 2 S 1 2 0 0_ D B 7
A D 2 S 1 2 0 0_ D B 6
A D 2 S 1 2 0 0_ D B 5
A D 2 S 1 2 0 0_ D B 4
A D 2 S 1 2 0 0_ D B 3
A D 2 S 1 2 0 0_ D B 2
A D 2 S 1 2 0 0_ D B 1
A D 2 S 1 2 0 0_ D B 0
A D 2 S 1 2 0 0_ D OS
A D 2 S 1 2 0 0_ L OT
A D 2 S 1 2 0 0_ D B 1 1_ S O
A D 2 S 1 2 0 0_ D B 1 0_ S C L K
A D 2 S 1 2 0 0_ D B 9
A D 2 S 1 2 0 0_ D B 8
A D 2 S 1 2 0 0_ D B 7
A D 2 S 1 2 0 0_ D B 6
A D 2 S 1 2 0 0_ D B 5
A D 2 S 1 2 0 0_ D B 4
A D 2 S 1 2 0 0_ D B 3
A D 2 S 1 2 0 0_ D B 2
A D 2 S 1 2 0 0_ D B 1
A D 2 S 1 2 0 0_ D B 0
EN n
S E R I A L _ P A R A LL E L _ MO D E _ u C
A D 2S 1 2 0 0 _D OS _ u C
A D 2S 12 0 0 _L O T_ u C
A D 2 S 1 2 00 _ D B 11 _ S O_ u C
A D 2 S 1 2 00 _ D B 10 _ S C LK _ u C
A D 2 S 1 2 0 0_ D B 9_ u C
A D 2 S 1 2 0 0_ D B 8_ u C
A D 2 S 1 2 0 0_ D B 7_ u C
A D 2 S 1 2 0 0_ D B 6_ u C
A D 2 S 1 2 0 0_ D B 5_ u C
A D 2 S 1 2 0 0_ D B 4_ u C
A D 2 S 1 2 0 0_ D B 3_ u C
A D 2 S 1 2 0 0_ D B 2_ u C
A D 2 S 1 2 0 0_ D B 1_ u C
A D 2 S 1 2 0 0_ D B 0_ u C
S E R I A L _ P A R A L LE L_ M OD E _u C
A D 2 S 1 2 0 0_ D OS _ u C
A D 2 S 1 2 0 0_ L OT _ u C
A D 2 S 1 20 0 _ D B 1 1 _ S O_ u C
A D 2 S 1 2 0 0_ D B 1 0_ S C L K _u C
A D 2 S 1 2 0 0_ D B 9 _u C
A D 2 S 1 2 0 0_ D B 8 _u C
A D 2 S 1 2 0 0_ D B 7 _u C
A D 2 S 1 2 0 0_ D B 6 _u C
A D 2 S 1 2 0 0_ D B 5 _u C
A D 2 S 1 2 0 0_ D B 4 _u C
A D 2 S 1 2 0 0_ D B 3 _u C
A D 2 S 1 2 0 0_ D B 2 _u C
A D 2 S 1 2 0 0_ D B 1 _u C
A D 2 S 1 2 0 0_ D B 0 _u C
S E R I A L _ P A R A LL E L _ MO D E _ u C
A D 2 S 1 20 0 _ D O S _ uC
A D 2 S 1 20 0 _ LO T _u C
A D 2 S 1 20 0 _ D B 1 1 _ S O_ u C
A D 2 S 1 20 0 _ D B 1 0 _ S C L K _ u C
A D 2 S 1 20 0 _ D B 9 _ u C
A D 2 S 1 20 0 _ D B 8 _ u C
A D 2 S 1 20 0 _ D B 7 _ u C
A D 2 S 1 20 0 _ D B 6 _ u C
A D 2 S 1 20 0 _ D B 5 _ u C
A D 2 S 1 20 0 _ D B 4 _ u C
A D 2 S 1 20 0 _ D B 3 _ u C
A D 2 S 1 20 0 _ D B 2 _ u C
A D 2 S 1 20 0 _ D B 1 _ u C
A D 2 S 1 20 0 _ D B 0 _ u C
LE V E L_ S H I F T E R _ R E S OL V E R
A D C_ IN 1
A D C_ IN 2
A D C_ IN 3
A D C_ IN 1
A D C_ IN 2
A D C_ IN 3
DIO _ 1
DIO _ 2
DIO _ 3
D I O_ 1
D I O_ 2
D I O_ 3
uC
C O N N E C T OR
Figure 61
Schematics Block Overview Logic Board v1.3b
Application Note
66
V2.4, 2014-08-11
FB/ N C
EN
GND
C8 6
22 u/16V/ X7R
OU T
OU T
RES ET
GN D_DI G1
2. 2nF
R121
0R
C8 9
100n /1 6V/ X7R
C 90
10uf / 10 V/X7R
8
GND _ANA1
GN D _AN A1
POWER rs tn
GND _D IG 1
GND _D IG1
R12 2
10 K
GN D_ DI G1
1
KL_30_I N
+12. 0V
VD IG50
+5.0V
GND _D IG1
2
EN
TPS76 71 5QD
GND _ DI G1
R116
10K
R 115
10K
3
C 95
10 0n /1 6V/ X7R
ENn
C97
+
IN
IN
VD I G50
+5. 0V
VDI G15
+1. 5V
0.4A / 1.4W
6
OU T
5
OU T
7
FB/ N C
8
RES ET
GND
68 0R
U 14
1
R1 19
L2
C 88
10 uf / 10V/X7R
7
10 uF/6 .3 V/X7 R
TLE6 38 9- 2GV50
GN D_DI G1
C96
4
3
C 98
SI _G ND
GND
3
2
9
8
10
5
1 00n/16V/ X7R
14
12
SI
VOUT
FB
SO
C OMP
RO
SY NC
3
6
4
VDI G50
+5. 0 V
C94
7
VS
SI _EN ABLE
CS
GDR V
1 0K
R 118
IN
IN
VD IG33
VANA3 3
+3. 3VMUR ATA_BLM21P2 21 SN+3.3 V
5
6
GN D_ D IG1
1 00 uF/ 10V
C9 1
220nF/5 0V/ X7R
11
GN D_ DI G1
BDS
C92
220nF/ 50 V/X7 R
C93
100uF/3 5V/ MAL214095001E3
+
2
GN D_ DI G1
GN D_ANA1
TPS76 733QD
D1
MBR S340T3
U13
13
1
C8 7
100n/16V/ X7R
U 12
L3
47 uH /B8 24 64G4473M
47mR /0.33W
KL_ 30
+12. 0V
GND _D IG 1
3
4
1
R1 14
Q1
SPD09P06PL G
C 85
R 113
0R
100n/16V/ X7R
VAN A50
+5.0V
L1
MUR ATA_ BLM21P221SN
1
Q2
BC 847BL 3
2
GND _D IG1
Q3
BC 847BL3
2
GND _D IG1
D2
BZV5 5/C 13
R 12 8
10K
GND _D IG1
Figure 62
Q4
IP D90P0 3P4 L- 04
KL _3 0
+12.0 V
D3
1 SMB30AT3
GN D_DI G1
Power Supply Logic Board v1.2
Application Note
67
V2.4, 2014-08-11
VD IG 50
+5 .0 V
VD IG 33
+3. 3V
VD IG 15
+1 .5 V
Q_ STBY VD IG 33
+1 .0 V
+ 3. 3V
25
WDI
WDO
RT
17
C 11 59
1 n/ 16 V/X7R
2
FB_ EXT
PAD
G ND_ A1
GN D_ A2
GN D_ A3
GN D_ A4
24
GN D_ DIG 1
1
Q2
BD P94 9
Q_ T2
Q_ T1
RO _1
RO _2
31
Q_ T2
+5 .0 V
8
7
3
4
Q _T1
+5. 0V
VDI G3 3
+3 .3 V
G ND_ DI G1
L9
MUR ATA_BL M21 PG2 21 SN
GN D_ DI G1
C1 157
C 12 3
1 0u /10 V/X7R
1 00 n/ 16V/ X7 R
R 11 3
SMK-R 000 / I sa belle nh ue tt e
R 47 6
1 0K
G ND_ DI G1
GND _AN A1
Q _T2
+5. 0V
Q_T1
+5. 0V
GN D_AN A1
VD IG1 5
+1 .5V
VAN A15
+1 .5 V
MURATA_BL M21 PG2 21SN
L1 1
3
1
8
G ND_ DI G1
Q4
IPD 90 P03P4 L- 04
SH DN
TEMP
C1 145
1u /25 V/X7 R/F_ 16 37 035
IN
7
KL _3 0_I N
+12 .0 V
Vre f 50
IC 53
+5 .0 V
MAX6 14 3AASA50
6
OUT
TRIM
5
KL_ 30
+12. 0V
D2
GN D
C 116 7
1 00n /5 0V/ X7R/ C0 80 5F10 4K5
VDI G50
+5 .0V
I.C ._ 1
I.C ._ 8
4
C11 66
4.7 u/ 50 V/X7R /C 12 10 F4 75 K5
2
Figure 63
C 11 58
10 u/ 10V/ X7 R
POW ERrs tn
Q_ STBY
+1 .0 V
L 10
GND _AN A1
VAN A33
+3. 3V
VDI G3 3
+3 .3 V
GN D_D IG 1
KL_ 30
+1 2. 0V
MU RATA_ BLM2 1PG 22 1SN
C 115 5
2 2u/ 16 V/X7R /F_ 14 635 75
32
VD IG 15
+1 .5 V
3
GND _P
+ 12 .0 V
DRV_ EXT
SEL _Q 2
EN _u C
EN _I GN
L1
MUR ATA_BL M21 PG2 21 SN
GN D_D IG 1
4
2
GN D_ DI G1
VANA5 0
+5. 0V
29
5
30
6
GND _D IG 1
VDI G5 0
+5 .0 V
37
1
18
19
36
23
9
10
GN D_ DIG 1
G ND_ DI G1
C8 5
100 n/ 50 V/X7R
Q_ LD O1
Q_ LD O2
G ND_ DI G1
R 47 4 10 K
R 47 5 10 K
D1
MBRS3 40 T3
VD IG 50 VD IG 33
+5 .0 V
+3. 3V
C1 15 6
2 20n /2 5V/ X7R /F_ 14 146 26
KL _3 0
+
SS1 2_ 1A_ If _2 0V_ Vr
BZV55/ C1 3
R1 28
R48 6 0 R / 0 .1 %
G ND _DI G1
C 11 46
4 u7/ 10 V/X7 R/F_ 94 02 195
VDI G3 3
+3 .3 V
FB
IN_ LD O2
C2+
CCP
28
Ty p XXL
C1 14 4
4u 7/ 10 V/ X7R /F_ 940 21 95
G ND _DI G1
C1C2-
W E_7 44 770 94 70
L3
IN1
IN2
IN3
C1+
BST
VSW
+ 5. 4V
R 47 3
1 0K
SS12 _1 A_I f _20 V_Vr
C11 54
22u /1 6V/ X7 R/ F_1 463 57 5
C1 15 3
1 00n /5 0V/ X7R 15
16
33
35
26
27
C 11 52
1 00u F_3 5V_MAL 21 409 70 01 E3
C1 15 1
1 00n /5 0V/ X7R 12
13
Q_ STBY
MON_ STBY
SW1
SW2
C1 142
4u7 /1 0V/ X7R
20
21
22
14
IN_ STBY
SEL _STBY
C 115 0
68 0n /5 0V/ F_ 14 14 70 2
+
C 92
2 20n F/1 00 V/ C3 21 6X7R 2A2 24 KT5
C9 3
100 uF_ 35 V_ MAL2 14 097 00 1E3
IC 13
TL E73 68 E
34
11
C 113 6
22 u/ 16 V/X7R /F_ 14 635 75
C1 135
22 u/1 6V/ X7R/ F_1 46 357 5
Q_ STBY
+1. 0V
KL _3 0
+ 12 .0 V
D6
C86
2 2u /1 6V/ X7 R/ F_1 463 57 5
D5
GND _D IG 1
D3
1 SMB30 AT3
10 K
G ND_ REF1
GN D_AN A1
G ND_ DI G1
GN D_ DI G1
Power Supply Logic Board v1.3b
VD I G33
+3. 3V
R1
10 K
R2 R3 R4 R5
10K 10K 10K 10K
X3-OC D S1
R es etn
BR KOU Tn
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
HE AD ER 8X2
TMS
TD O
TD I
TR STn
TC K
BR KIN n
R6
1 0K
GN D _ D IG1
Figure 64
JTAG Debug Connector (same for Logic Board v1.2 and v1.3b)
Application Note
68
V2.4, 2014-08-11
se t2
0
0
0
0
1
1
1
1
VD IG3 3
+3 .3V
R 149
opt
R 150
4k7
set1
0
0
1
1
0
0
1
1
s et0
0
1
0
1
0
1
0
1
tde lay, twd
1 ms
1 0ms
3 0ms
Disa bled
100m s
1s
10s
60s
U23
R 151
4k7
8
Vcc
2
GN D
NC
SET0
SET1
SET2 WD O
4
5
6
1
WD I
3
7
W \D \ O\
1
GN D_ D IG1
W DI
1
2
R 154
opt
2
R 153
4k7
MAX636 9KA-T
J1
Jum pe r
GN D _ DI G1
Figure 65
Watchdog (same for Logic Board v1.2 and v1.3b)
VANA50
+5.0V
7
GND_ANA1
R104
0R
-
KL_30
+12.0V
SinLO
S6
12
13
8
GND_ DI G1
R107
opt
U4D PACKAGE= 1
LT1639HS
+
Cos
R106
0R
14
CosLO
C77
10n/16V/ X7R
GND_DIG1
VDIG50
+5.0V
U8
1
2
3
4
5
6
7
8
9
10
11
RDn
CSn
SAMPLEn
RDVELn
GND_DIG1
74LVC1G04GW
SinLO
Sin
12
13
14
15
16
17
18
19
20
21
22
GND_DI G1
GND_ANA1
R155
R157
tbd_opt
DVdd
RD
CS
SAMPL E
RDVEL
SOE
DB11/SO
DB10/SCLK
DB9
DB8
DB7
RESET
FS2
FS1
LOT
DOS
DI R
NM
B
A
CPO
DGND
33
32
31
30
29
28
27
26
25
24
23
C144
100n/ 25V/X7R
GND_ANA1
t bd_opt
VANA50
+5.0V
REFOUT
REFBYP
AGND
Cos
CosLO
AVdd
SinLO
Sin
AGND
EXC
EXC
4u7/25V/ X7R
C80
4
1
10 n/16V/X7R
C79
GND_DIG1
op t
Y
NC
GND_DIG1
GND_DIG1
GND_ANA1
DB6
DB5
DB4
DB3
DGND
DVdd
DB2
DB1
DB0
XTALOUT
CLKIN
R110
U9
2
5 A
3 VCC
GND
L8
R156
44
43
42
41
40
39
38
37
36
35
34
C78
10uF/10V/X7R
GND_ANA1
Cos
CosLO
GND_ANA1
SAMPLE
C1111
22uF/16V/X7R
C143
22uF/16V/X7R
VANA50
+5.0V
R109
opt
VDIG33
+3 .3V
INH
MURATA_BLM21P221SN
3
GND_ANA1
R108
0R
-
Q
C76
9 -
TLE4266GSV10
I
C1112
100n/ 25V/X7R
C7 5
10n/16V/ X7R
10 +
2
GND_ANA1
4u 7/16V/X7R
S2
U4C PACKAGE= 1
LT1639HS
U25
1
R105
opt
RESETn
FS1
FS2
LOT
DOS
NM
B
A
R159
tbd_opt
GND_ANA1
tbd_opt
R158
tbd_opt
U6
2
3
6
5
8
U4B PACKAGE= 1
LT1639HS
+
+Vs
6
IN-1
OUT1
IN+1
IN-2
OUT2
IN+2
1
7
R2
R1
-Vs
5
4
GND_ANA1
S3
Sin
R103
opt
4 GND
U4A PACKAGE= 1
LT1639HS
4
3 + V+
1
R102
0R
2 11 V-
S1
LMH6672
GND_ANA1
R160
tbd_opt
GND_DIG1
AD2 S1200YST
SCLK
2
2
C84
20pF/50V/COG
HCM49 8.192MABJ-UT
GND_DIG1
Figure 66
1
20pF/50V/COG
1
C83
GND_DI G1
U11
GND_DIG1
4u7 /25V/X7R
R112
39K
GND_DIG1
C81
SO
VDIG50
+5.0V
10n/ 16V/X7R
C82
R111
20K
Resolver Logic Board v1.2
Application Note
69
V2.4, 2014-08-11
GND_ANA1
VANA50
+5.0V
R107
opt
CosLO
AD2S1200_RDVELn
R109
opt
AD2S1200_DB11_SO
AD2S1200_DB10_SCLK
AD2S1200_DB9
AD2S1200_DB8
AD2S1200_DB7
GND_ANA1
R110
2A
2Y
VCC
C7 6
C7 5
10 n/16 V/X 7R
4u 7/16 V/X 7R
Si nLO
Si n
44
43
42
41
40
39
38
37
36
35
34
R2
8
TP3
Testpad_SMD_Etting er
R158
6
IN-2
OUT2
IN+2
2K4/0.1%
5
R159
3K3/0.1%
7
R1
LMH6672
GND_ANA1
R160
GND_ANA1
2K4/0.1%
GND_ DIG 1
U1
100n/16V/X7R
6
4
VDIG50
+5.0V
74LVC2G04GW
GND_DIG1
C8 1
R471
10K
1Y
NM
B
A
3
1
AD2S1200YST
1
1
2
2
HCM49 8.192MABJ- UT
20 pF/5 0V /CO G
AD2S1200_SOE
1A
AD2S1200_RESETn
AD2S1200_FS2
AD2S1200_FS1
AD2S1200_LOT
AD2S1200_DOS
R157
390/0.1%
TP4
IN-1
OUT1
IN+1
2K4/0.1%
R485
5K_pot_0,25W_20%_Bour ns_3314J_opt
AD2S 120 0_DB6
AD2S 120 0_DB5
AD2S 120 0_DB4
AD2S 120 0_DB3
3
GND
AD2S1200_SAMPLEn
2
IC30
1
C1164
5
VDIG33
+3.3V
IC6
R155
VANA50
+5.0V
GND_DIG1
12
13
14
15
16
17
18
19
20
21
22
opt
AD2S 120 0_DB2
AD2S 120 0_DB1
AD2S 120 0_DB0
-
AD2S1200_CSn
RESET
FS2
FS1
LOT
DOS
DIR
NM
B
A
CPO
DGND
33
32
31
30
29
28
27
26
25
24
23
C8 4
R108
0R
4u 7/25 V/X 7R
C8 3
14
DVdd
RD
CS
SAMPLE
RDVEL
SOE
DB11/SO
DB10/SCLK
DB9
DB8
DB7
C8 2
+
Testpad_SMD_Etting er GND_ANA1
RE FO UT
RE FB YP
AG ND
Co s
Co sLO
AV dd
Si nLO
Si n
AG ND
EX C
EX C
13
IC8
1
2
3
4
5
6
7
8
9
10
11
C1217
opt
TP2
GND_DIG1
IC4D PACKAGE = 1
LT1639HS
GND_ANA1
C1216
opt
2
DB 6
DB 5
DB 4
DB 3
DG ND
DV dd
DB 2
DB 1
DB 0
XTALO UT
CL KIN
TP8
Co s
Co sLO
Cos
R106
0R
10 n/16 V/X 7R
8
2K4/0.1%
GND_ANA1
4u 7/25 V/X 7R
-
12
10 n/16 V/X 7R
C7 9
+
9
Testpad_SMD_
R156
TP1
IC4C PACKAGE = 1
GND_ANA1
LT1639HS
10
S6
R483
5K_pot_0,25W_20%_Bour ns_3314J_opt
R105
opt
GND_DIG1 GND_DIG1
+V s
-
C144
100n/25V/X7R
TP9
GND_DIG1
GND_ANA1
VDIG50
+5.0V
TP7
C143
22uF/16V/X7R
GND_ANA1
SinLO
R104
0R
L8
C1111
22uF/16V/X7R
-V s
7
INH
3
GND_ANA1
GND_ANA1
+
MURATA_BLM21PG221SN
Q
4
6
10 uF/1 0V /X7R
GND_ANA1
IC4B PACKAGE = 1
LT1639HS
GND_ANA1
5
S2
C7 7
TP6
10 n/16 V/X 7R
C7 8
R103
opt
S3
Sin
C8 0
S1
2
TLE4266GSV10
I
R4 84
5K _po t_0 ,25W_2 0%_ Bou rns_33 14J_op t
IC4A PACKAGE = 1
LT1639HS
V+
+
1
R102
0R
2
11 - V4
3
IC25
1
20 pF/5 0V /CO G
100n/16V/X7R
C1 112
TP5
KL_30
+12.0V
GND
C1163
4
10 0n/5 0V /X7R/C0 805 F10 4K5
VANA50
+5.0V
GND_DIG1
GND_DIG1
Figure 67
GND_DIG1
Resolver Logic Board v1.3b
R71
R7 3
10 K
R7 2
10 0R
C6 0
10 0pF/ 50V/ COG
1 0K
GND _DI G1
GND _DI G1
GN D_D IG 1
VDI G50
+ 5. 0V
1K
U2
1
48
47
46
44
43
41
40
38
37
PW MWT_u C
PWMWB_u C
PWMVT_u C
PW MVB_u C
PW MUT_u C
PWMUB_u C
RST_ INn _u C
36
35
33
32
30
29
27
26
FLTU n_ uC
FL TVn_ uC
FLTWn_ uC
FLTn_u C
VDI G3 3
+3.3 V
C 65
1 00n /1 6V/X7R
GN D_D IG 1
R8 7
10 0R
R 80
R8 1
R82
R83
R 84
R8 5
R8 6
GND _DI G1
31
42
4
10
15
21
1D IR
1O E
2D IR
2O E
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
VCCA
VCCA
GN D
GN D
GN D
GN D
VCC B
VCC B
GND
GND
GND
GND
1K
1K
1K
1K
1K
1K
1K
R8 8
1K
1K
1K
1K
1K
1K
R7 4
R7 5
R76
R 77
R 78
R7 9
GN D_ DIG 1
C6 1
10 0pF/ 50V/ COG
GND _DI G1
24
25
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
7
18
28
34
39
45
7 4ALVC 164 24 5DG G
R8 9
10 0R
C6 2
10 0pF/ 50V/ COG
GND _DI G1
R ST_I Nn
R9 1
10 0R
R9 2
PWMW B
PWMVT
PWMVB
15 K R90 VDI G5 0
+5 .0 V
1K
PWMWT
FLTUn
PWMUT
C6 3
10 0pF/ 50V/ COG
PWMU B
C64
GND _DI G1
1 00n /1 6V/X7R
VD IG 50
+5 .0 V
1K
C 66
1 00 n/1 6V/X7R
15 K R93
GND _DI G1
VDI G5 0
+5. 0V
R9 4
10 0R
R9 5
FL TVn
C6 7
10 0pF/ 50V/ COG
C 68
GND _DI G1
1 00n /1 6V/X7R
15 K R96
GND _DI G1
1K
VDIG 50
+5. 0V
R9 8
FLTWn
C 70
1 00n /1 6V/X7R
GND _DI G1
1K
1 5K R9 9
VDI G50
+5 .0V
R9 7
10 0R
C6 9
10 0pF/ 50V/ COG
GND _DI G1
R1 00
FLTn
C71
1 00 n/1 6V/ X7R
GN D_D IG1
Figure 68
Level Shifter for Adapting 3.3V to 5V Logic Levels Logic Board v1.2
Application Note
70
V2.4, 2014-08-11
R 73
10K
G ND _D IG1
G ND _DI G1
1K
47
46
44
43
41
40
38
37
PWMW T_ uC
PW MWB_ uC
PWMVT_ uC
PWMVB_ uC
PWMU T_ uC
PW MUB_ uC
RST_IN n_ uC
36
35
33
32
30
29
27
26
FLTUn _uC
FL TVn _uC
FLTWn _uC
FLTn_ uC
VDIG 33
+3. 3V
C65
1 00n /1 6V/ X7R
GN D_ DIG 1
31
42
4
10
15
21
1 DIR
1 OE
2DI R
2OE
1 A0
1 A1
1 A2
1 A3
1 A4
1 A5
1 A6
1 A7
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2 A0
2 A1
2 A2
2 A3
2 A4
2 A5
2 A6
2 A7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
VC CA VCCB
VC CA VCCB
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
R7 1
R80
1K
G ND_ DI G1
I C2
1
48
10 K
VDI G50
+5. 0V
R 88
1K
1K
1K
1K
1K
1K
R 74
R 75
R 76
R7 7
R7 8
R7 9
GND _D IG 1
PWMW T
24
25
PWMWB
2
3
5
6
8
9
11
12
PWMVT
PWMVB
RST_ IN n
13
14
16
17
19
20
22
23
1 5K
1K
VD IG 50
R9 0 +5. 0V
PWMU T
R9 2
PWMUB
FL TU n
C 64
1 00 n/1 6V/ X7 R
VDI G5 0
+5. 0V
7
18
28
34
39
45
G ND_ DI G1
1 5K
1K
C6 6
10 0n /16 V/X7R
R9 3
VDI G50
+ 5. 0V
R9 5
FLTVn
C6 8
1 00 n/1 6V/ X7 R
1 5K
G ND_ DI G1
74 AL VC1 642 45 DG G
1K
R9 6
VD IG5 0
+5.0 V
R9 8
FL TW n
C7 0
1 00 n/1 6V/ X7 R
1 5K
G ND_ DI G1
1K
R9 9
VD IG 50
+5. 0V
R1 00
FL Tn
C7 1
1 00 n/ 16V/ X7 R
G ND_ DI G1
R 497 0R
EN n
SER I AL_PAR ALL EL_MOD E_u C
I C 29
R 456 1K
1
48
GN D _D I G1
A D 2S 120 0_D B 9_uC
A D 2S 120 0_D B 8_uC
A D 2S 120 0_D B 7_uC
A D 2S 120 0_D B 6_uC
A D 2S 120 0_D B 5_uC
A D2S 12 00_D B10 _SC LK_uC
47
46
44
43
41
40
38
37
A D 2S 120 0_L OT_uC
A D 2S 120 0_D OS_uC
A D 2S 1200 _D B 11_SO_ uC
A D 2S 120 0_D B 4_uC
A D 2S 120 0_D B 3_uC
A D 2S 120 0_D B 2_uC
A D 2S 120 0_D B 1_uC
A D 2S 120 0_D B 0_uC
36
35
33
32
30
29
27
26
VD IG33
+3. 3V
31
42
4
10
15
21
1 D IR
1 OE
2 DI R
2OE
1 A0
1 A1
1 A2
1 A3
1 A4
1 A5
1 A6
1 A7
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2 A0
2 A1
2 A2
2 A3
2 A4
2 A5
2 A6
2 A7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
VC C A VC C B
VC C A VC C B
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
24
25
GND _ D I G1
A D2 S120 0_ D B9
A D2 S120 0_ D B8
A D2 S120 0_ D B7
A D2 S120 0_ D B6
A D2 S120 0_ D B5
A D2 S120 0_ D B10_ SC LK
13
14
16
17
19
20
22
23
A D2 S120 0_ LOT
A D2 S120 0_ D OS
A D2 S120 0_ D B11_ SO
A D2 S120 0_ D B4
A D2 S120 0_ D B3
A D2 S120 0_ D B2
A D2 S120 0_ D B1
A D2 S120 0_ D B0
VD IG5 0
+5 .0 V
7
18
28
34
39
45
74 LVC H 1 6T2 45D L
C 1132
10 0n/16V/ X7R
R 498 0R _o pt
GN D _DI G1
2
3
5
6
8
9
11
12
C 11 33
10 0n/ 16V /X7R
GND _D I G1
Figure 69
Level Shifter for Adapting 3.3V to 5V Logic Levels Logic Board v1.3b
KL_30
+12.0V
GN D_ANA1
GN D_D IG1
VDC
TEMP_BOAR D
F LTWn
TEMP_HP2_W
F LTVn
TEMP_HP2_V
F LTU n
F LTn
1
3
5
7
9
11
13
15
17
19
21
23
KL_30
+12. 0V
K1
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
GND _DIG1
VANA50_D B
TEMP_HP2_U
RST_INn
PWMWT
PWMWB
PWMVT
PWMVB
PWMUT
PWMUB
TW-12- 06- L-D- 475- SM-A
Figure 70
Connector to the Driver Board (same for Logic Board v1.2 and v1.3b)
Application Note
71
V2.4, 2014-08-11
V D I G 33
+ 3 .3 V
L5
M U R A T A _ B L M2 1 P 22 1 S N
U1 6
E H 2 64 5 E T T TS - 20 . 0 0 0M
4
1
V DC
T RI
u c _ T C 1 7 67
GN D
2
P W MV B n
GP T A 2 6
P W MW T n
GP T A 2 7
P W MW B n
GP T A 3 9
WD I
1 0n / 1 6 V / X 7 R
C 1 05
P W MV T n
GP T A 1 9
2 2u F / 6 . 3 V / X 7 R
GP T A 1 8
GN D _ D I G 1
GP T A 2 8
A
B
N M
G P TA 24
G P TA 14
G P TA 43
GP T A 2 4
GP T A 1 4
GP T A 4 3
D I O_ 1
D I O_ 2
D I O_ 3
D I O_ 4
G P TA 45
G P TA 17
G P TA 32
G P TA 21
GP T A 4 5
GP T A 1 7
GP T A 3 2
GP T A 2 1
S CL K 0
M RS T 0
M TS R 0
S LS O0
V D I G3 3
+ 3. 3 V
E E P R OM
V D I G5 0
+ 5 . 0V
1 0 0 n / 16 V / X 7 R
T X DCA N1
R X DCA N1
D I O _1
D I O _2
D I O _3
D I O _4
G N D _D I G1
C A N_ T X 1
C A N _R X 1
AN4
1
4
AN1
AN6
AN3
AN1 2
AN2
I_ U
I_ V
I_ W
A N 15
A N 14
A N 13
A N 31
AN1 5
AN1 4
AN1 3
AN3 1
A N 16
A N 17
A N 19
AN1 6
AN1 7
AN1 9
A D C_ IN 1
A D C_ IN 2
A D C_ IN 3
GP T A 4 1
P 5_ 9
P 5_ 8
GP T A 3 5
GP T A 3 4
GP T A 2 9
GP T A 3
GP T A 4 0
S CL K 1
M RS T 1
S LS O1
R DVE L
FS 2
FS 1
L OT
R 3 15
DO S
R 3 16
CAN H
C A NL
FL 1
2
7
6
3
B 8 27 8 9 C 0 1 04 N 00 1
1
R 13 2
60R
C1 1 0
4 . 7 n/ 5 0 V / X 7 R
G ND _ DIG 1
4
C A N 1_ L
GN D _ D I G 1
0 R_ o p t
0R
S A MP LE
R e s e t n_ R es
R 13 3
5k1
SC L K1
MR S T 1
SL S0 1
GN D _ D I G1
I n p ut _ F i l t e r
IN H
T X DO A
u c _ T C 1 7 67
C 11 2
A D C _I N 1
A D C _I N 2
A D C _I N 3
AN1
AN6
AN3
A N 12
AN2
C 1 14
I_ U
I_ V
I_ W
T E M P _I GB T _ U
T E M P _I GB T _ V
T E M P _I GB T _ W
T E M P _B oa rd
S t a t o rT e mp
1 0 0n / 1 6 V / X 7 R
T E M P _ I GB T _ U
T E M P _ I GB T _ V
T E M P _ I GB T _ W
T E M P _ B o ard
S t a t or Te m p
U 17
T L E 6 25 0 GV 33
2
8
TxD
R xD
GN D
AN4
10 0 n / 1 6V / X 7R
VD C
Vc c
V3 3 V
3
5
GN D _ D I G1
T XD 0 A
R XD 0 A
VD C_ u C
C A N 1_ H
R 13 1
60R
1
3
4
5
R1 3 4
R XDO A
1K
15
C 1C 2+
V-
6
10 0 n / 16 V / X 7 R
GN D _ D I G 1
C 2T 1 ni
T1 o u t
T 2 ni
T2 o u t
R 1o u t R 1 i n
R 2o u t R 2 i n
G ND
C 11 1
1 0 0n / 1 6 V / X 7R
C1 1 3
Vc c
14
7
13
8
16
A S CT X
R 13 5
1K
A S CR X
V D I G 33
+ 3. 3 V
G N D _D I G1
C 1 15
G ND _ DIG 1
11
10
12
9
U 18
M A X 32 3 2 E I P W R Q1
2
C 1+
V+
1 0 0n / 1 6 V / X 7 R
GP T A 1 2
GP T A 3 8
GP T A 1 1
GP T A 4 6
GP T A 4 4
GP T A 4 2
C1 0 8
12
38
11
46
44
42
22 u F / 6 . 3 V / X 7 R
P TA
P TA
P TA
P TA
P TA
P TA
C1 0 7
G
G
G
G
G
G
10 0 n / 1 6V / X 7R
Po s A
Po s B
Po s Z
Po s U
Po s V
Po s W
C1 0 9
I N P U T _ F I L TE R
A
B
N M
O UT
P OR S T n
R STn
Po s A
Po s B
Po s Z
Po s U
P os V
P os W
3
P W MU T n
P W MU B n
E E P R OM
R1 0 1
1 0K
R e s et n
R es e t n
TR S T n
TC K
TD I
TD O
TM S
BRKO UT n
BRKIN n
GP T A 8
GP T A 9
CSn
SC K
SI
S O
V DIG 3 3
+ 3 .3 V
T RST n
TC K
TD I
TD O
TM S
B RK O UT n
BRKIN n
T R S Tn
T CK
T DI
TD O
T MS
B RK O UT n
B RK IN n
GP T A 2 0
Cl k
C 10 6
F LT _ n
FL T_ n
GP T A 1 3
GP T A 1 0
GP T A 1 5
10 0 n / 1 6V / X 7R
C 10 4
F LT _ U n
F LT _ V n
F LT _ W n
F L T _ Un
FL T_ Vn
FL T_ W n
G N D _ D I G1
Figure 71
Microcontroller Logic Board v1.2
Application Note
72
V2.4, 2014-08-11
V D I G 33
+ 3 .3 V
L5
M U R A T A _ B L M2 1 P 22 1 S N
I C1 6
E H 2 6 45 E T T TS -2 0 . 00 0 M
4
1
VDC
TR I
u c_ T C 1 7 67
VDC
T E MP _ I GB T _ U
T E MP _ I GB T _ V
T E MP _ I GB T _ W
T E MP _ B oa rd
S t a t orT e mp
V D I G5 0
+5 . 0 V
A N2 9
AN1
AN2
AN3
AN4
AN5
P4 _ 1
P4 _ 0
P2 _ 5
A N 29
AN
AN
AN
AN
AN
1
2
3
4
5
I_ U
I_ V
I_ W
A N1 5
A N1 4
A N1 3
A N3 1
A N 15
A N 14
A N 13
A N 31
A D C _I N 1
A D C _I N 2
A D C _I N 3
A N1 7
A N1 8
A N1 9
A N 17
A N 18
A N 19
P5 _ 0
P5 _ 1
P5 _ 2
P5 _ 3
P5 _ 4
P5 _ 5
P5 _ 6
P5 _ 7
P5 _ 8
P5 _ 9
P 5_ 1 2
P 5_ 1 3
P 5_ 1 5
P 3_ 1 0
P 3_ 1 1
P 3_ 1 2
A D 2 S 1 2 00 _ D B 0 _ uC
A D 2 S 1 2 00 _ D B 1 _ uC
A D 2 S 1 2 00 _ D B 2 _ uC
A D 2 S 1 2 00 _ D B 3 _ uC
A D 2 S 1 2 00 _ D B 4 _ uC
A D 2 S 1 2 00 _ D B 5 _ uC
A D 2 S 1 2 00 _ D B 6 _ uC
A D 2 S 1 2 00 _ D B 7 _ uC
A D 2 S 1 2 00 _ D B 8 _ uC
A D 2 S 1 2 00 _ D B 9 _ uC
A D 2 S 1 2 00 _ D OS _u C
A D 2 S 1 2 00 _ LO T _u C
A D 2 S 1 2 00 _ R D V E Ln _ uC
GP T A 3
A D 2 S 1 2 00 _ S A MP L E _ uC
GN D _ D I G1
C A N 1 _H
FL1
C A N _T X 1
CA N_ RX 1
R1 3 3
5 K1
1
4
8
T xD
Rx D
INH
A D 2S 1 2 00 _ R E S E T n _ uC
A D 2 S 1 2 00 _ F S 1 _u C
A D 2 S 1 2 00 _ F S 2 _u C
I C 17
T L E 62 5 0 GV 3 3
CA NH
C ANL
R 1 31
6 0R
B 8 27 8 9C 0 10 4 N 0 01
7
6
1
4
2
3
R 1 32
6 0R
C 1 10
4 . 7n / 5 0 V / X7 R
GN D _ D I G 1
C A N1 _ L
G ND_ DIG 1
iGMR Serial Mode/Encoder Mode:
(switch pin 1 open (OFF)) -> iGMR_INDEX_uC low
I np u t _ F li t e r
T XD OA
C 1 12
Resolver Serial (2,3,4 is ON)
A D 2 S 1 20 0 _D B 1 1_ S O_ u C
A D 2 S 1 20 0 _D B 1 0_ S C L K _ u C - uC_TC1767.SCLK1 drives
- MRST1 as input, driven by Resolver
V D I G3 3
- SERIAL_PARALLEL_MODE_uC is
+ 3 . 3V
Default is serial mode
- AD2S1200_CSn_uC
SW 2
S W D I P -4 / S M
C 1 14
P 5_ 1 1
P 5_ 1 0
10 0 n / 16 V / X 7 R
iGMR disabled: (switch pin 1 closed (ON))
A D C _I N 1
A D C _I N 2
A D C _I N 3
G N D _ D I G1
GN D _ D I G 1
3
5
P 4_ 1
P 4_ 0
P 2_ 5
P1 _ 8
P 1 _ 10
P4 _ 3
C 1 07
T X DCA N 1
R X DCA N 1
T XD 0A
R XD 0A
P 1_ 8
P 1 _1 0
P 4_ 3
V D I G 33
+ 3. 3 V
E E P R OM
1 00 n / 16 V / X 7 R
P4 _ 2
P2 _ 0
P2 _ 2
2 2 uF / 6 . 3 V / X 7 R
P 4_ 2
P 2_ 0
P 2_ 2
Vc c
V3 3 V
D I O _1
D I O _2
D I O _3
S CL K 0
M RS T 0
M TS R 0
S LS O 0
5
R1 3 4
RXDO A
S LS O 1
S LS O 2
P3 _ 8
P 2_ 1 2
11
10
12
9
C2 +
V-
6
1 0 0n / 1 6 V / X7 R
GN D _ D I G 1
C2 T1 i n T 1o u t
T2 i n T 2o u t
R 1 ou t R 1i n
R 2 ou t R 2i n
14
7
13
8
A SCT X
R 1 35
1K
GN D _D I G1
15
GN D
Vc c
A SCR X
V DIG 3 3
+ 3 . 3V
16
C1 1 5
G
i MR _I N D E X _ uC
C 1 11
10 0 n / 16 V / X 7R
C 11 3
C1 -
G N D _D I G1
i GMR
S CL K 1
M RS T 1
3
4
1K
A D 2S 1 2 0 0_ S OE _u C
S E R I A L _P A R A L LE L _ MOD E _ uC
IC5 2
MA X 3 2 32 E I P W R Q1
1
2
C1 +
V+
G
i MR _C LK _ u C
G
i MR _R OU T _ u C
1 0 0n / 1 6V / X 7R
I_ U
I_ V
I_ W
A
B
NM
P 0 _ 12
P 0 _ 14
P 0 _ 11
GN D
P o sW / i GM R _ W
P 0 _1 2
P 0 _1 4
P 0 _1 1
2
P o sV / i GM R _ V
P o s W / i GMR _ W
V D C _ uC
G N D _D I G1
W DI
C 10 9
P o s V / i GMR _ V
TE M P _I GB T _U
TE M P _I GB T _V
TE M P _I GB T _W
TE M P _B oa rd
S t a t o rT em p
PW M W Bn
1 0 0 n/ 1 6 V / X 7 R
C1 0 8
P o sU / G
i MR _U
D I O _1
D I O _2
D I O _3
P W M W Tn
CSn
SC K
SI
SO
R_ A +
R_ A R_ B +
R_ B R_ Z +
R_ Z -
P o s U / i GM R _ U
A
B
NM
PW M VBn
P1 _ 9
P 3 _ 13
I N P U T_ F I L TE R
P o sA / i GM
P o sA / i GM
P o sB / i GM
P o sB / i GM
P o sZ / i GM
P o sZ / i GM
2
1 00 n / 16 V / X 7 R
RS T n
G ND
P O RS T n
R ST n
MR _ A +
MR _ A MR _ B +
MR _ B MR _ Z +
MR _ Z -
P W M V Tn
GP T A 1 9
GP T A 3 9
R e se t n
R es e t n
P o s A /G
i
P o s A /G
i
P o s B /G
i
P o s B /G
i
P o s Z /G
i
P o s Z /G
i
GP T A 1 8
GP T A 2 7
OU T
E E P R OM
R1 0 1
1 0K
T RST n
T CK
T DI
T DO
T MS
B R K OU T n
B R K INn
3
P W M UT n
P W M UB n
10 n / 16 V / X 7 R
C1 0 5
T RS T n
T CK
T DI
TD O
T MS
BRKO UT n
BRKIN n
V D I G3 3
+3 . 3 V
GP T A 8
GP T A 9
2 2 uF / 6. 3 V / X 7 R
TR S T n
TC K
TD I
TD O
TM S
B RK O UT n
BRKIN n
G P TA 2 0
Cl k
C1 0 6
F LT _ n
F L T _n
P1 _ 5
P1 _ 6
P1 _ 7
1 00 n / 1 6V / X 7 R
C 10 4
F LT _ U n
F LT _ V n
F LT _ W n
F L T _U n
F L T _V n
F L T _W n
GN D _D I G1
A D 2S 1 2 0 0_ C S n _ u C
G
i MR _C S _u C
G
i MR _R E _u C
G
i MR _D I _u C
u c_ T C 1 7 67
Figure 72
Microcontroller Logic Board v1.3b
Application Note
73
V2.4, 2014-08-11
VANA50
+5.0V R174
10K
VANA50
+5.0 V
R1 75
St atorTemp
5 1k
R184
AN2
C172
10 0p/50V/ X7R
R176
opt
R177
10K
VANA50
+5.0 V
AN4
R191
R178
5 1k
GND_ANA1
VDC
51K
R179
ADC_IN1
C176
100p /50V/ X7R
R185
opt
5 1k
VANA50
+5.0 V
GND_ANA1
AN6
R205
GND_ANA1
DIO_3
C184
100 p/50V/ X7R
R203
opt
R214
R210
91K
51K
51K
C186
100p/50V/X7R
51K
R223
PosW
R224
C194
100p/ 50V/X7R
GPTA46
51K
0R
R229
AN31
R230
R231
AN13
I _W
C196
100p/ 50V/X7R
R227
91K
C193
100p/50V/X7R
GND_DI G1
0R_opt
GND_ANA1
R2 35
opt
GPTA44
C189
100p/50V/X7R
GND_DI G1
AN14
51K
R216
91K
R222
I _V
R2 28
opt
GPTA42
C185
100p/50V/X7R
GND_DI G1
R213
PosV
GND_ANA1
51K
R207
91K
C191
100p/ 50V/X7 R
R217
opt
C181
100p/50V/X7R
GND_DI G1
R204
AN15
I_U
R201
91K
PosU
GND_DIG1
GND_ANA1
GPTA11
51K
C182
100p/50V/X7R
GPTA21
51K
C187
100p /50V/ X7R
R208
opt
PosZ
GND_DIG1
DIO_4
C177
100p/50V/X7R
GND_DI G1
R206
AN3
51K
R200
91K
R190
91K
R197
GPTA32
51K
C175
100p/50V/X7R
GPTA38
51K
C179
100p/50V/X7R
R196
GND_ANA1
TEMP_I GBT_W
R193
91K
PosB
GND_DIG1
GND_ANA1
R183
91K
GND_DI G1
GPTA17
51K
AN19
5 1k
GPTA12
51K
R187
DIO_2
C178
100 p/50V/ X7R
R192
opt
ADC_IN3
C183
100p /50V/ X7R
R202
opt
R182
91K
PosA
GND_DIG1
R195
10K
R199
R198
TEMP_I GBT_V
GPTA45
C174
100p/50V/X7R
R189
AN17
AN1
51K
GND_ANA1
ADC_IN2
C180
100p /50V/ X7R
R194
opt
R181
opt
R180
DIO_1
51K
R186
10K
R188
GND_ANA1
TEMP_I GBT_U
51K
AN16
C173
100 p/50V/ X7R
R234
TEMP_Board
AN12
51K
GND_ANA1
R236
opt
A
C198
100p/ 50V/X7R
GPTA24
51K
GND_ANA1
R237
91K
C199
100p/50V/X7R
GND_ DI G1
B
R238
51K
R239
91K
GPTA14
C200
100p/50V/X7R
GND_ DI G1
R240
NM
51K
R241
91K
GPTA43
C201
100p/50V/X7R
GND_ DI G1
Figure 73
Input Filter Logic Board v1.2
Application Note
74
V2.4, 2014-08-11
General Purpose Analogue IN
V A NA 5 0
+ 5 . 0V
V D I G5 0
+ 5 . 0V
C 1 1 60
GN D _ D I G1
Encoder Inputs/iGMR Inputs
(iGMR Emulates Encoder)
R 1 94
op t
R1 9 8
C1 8 0
1 n/ 5 0 V / X7 R
A DC_ IN1
GN D _ A N A 1
T E MP _ I GB T _V
V A NA 5 0
+ 5 . 0V
A N2
68K
R2 0 5
R 2 02
op t
C1 8 3
1 n/ 5 0 V / X7 R
GN D _ A N A 1
R 2 08
op t
GN D _ A N A 1
A N4
R 1 76
op t
R 43 0
6
1 0 p/ 5 0 V / X7 R
10 0R
C 1 04 2
1 0p / 5 0V / X 7 R
C 11 4 7
1 0 p/ 5 0 V / X7 R
C1 7 8
1 n/ 5 0 V / X7 R
C 1 14 8
10 p / 50 V / X 7R
R 43 1
10
9
1 0 0R
14
C 1 14 9
1 0p / 50 V / X 7R
15
51K
R 2 03
op t
GN D _ A N A 1
1 A+
1Y
1 B2 A+
R 1 83
2K
2Y
2 B-
GN D _D I G1
3
R1 8 7
5
P 0_ 1 4
1K
3 A+
3Y
R 1 90
2K
11
3 BGN D _D I G1
4 A+
4Y
4 B-
13
R1 9 7
P 0_ 1 1
1K
A M 26 C 3 2 QD
R 2 01
2K
GN D _D I G1
V D I G 33
+ 3 . 3V
Hall Sensor/iGMR Inputs (iGMR Emulates Hall Sensor)
Assumed Open-Collector output from Hall sensor
C1 8 4
1 n/ 5 0 V / X7 R
GN D _ A N A 1
T E MP _ B oa rd
P 0_ 1 2
1K
G ND_ DIG 1
A N 19
A DC_ IN3
C1 7 2
1 n/ 5 0 V / X7 R
G+
G-
GN D _ A N A 1
R1 9 5
1 0K
R1 9 9
R 1 75
S t at o rT em p
68K
2
C 1 0 41
P o sZ / i GM R _ Z -
R 1 92
op t
V A NA 5 0
+ 5 . 0V
10 0 R
P o sZ / i GM R _ Z +
A N 18
C1 8 7
1 n/ 5 0 V / X7 R
R 4 29
7
P o sB / i GM R _ B -
51K
4
C 1 04 5
10 p / 50 V / X 7R 12
1
1 0 p/ 5 0 V / X7 R
P o sB / i GM R _ B +
GN D _ A N A 1
A DC_ IN2
A N3
V A NA 5 0
R 1 74
+5 . 0 V
1 0K
R 1 81
op t
C 1 0 40
P o sA / i GM R _ A +
P o sA / i GM R _ A -
C1 7 3
1 n/ 5 0 V / X7 R
R1 8 6
1 0K
R1 8 8
T E MP _ I GB T _W
68K
A N 17
R 17 8
51K
C 10 4 4
1 0 p/ 5 0 V / X7 R
8
68K
C 1 0 43
1 0p / 5 0V / X 7 R
R 1 77
10 K
Vc c
A N1
1 00 n / 16 V / X 7R
GN D
T E MP _ I GB T _U
R1 8 0
GN D _ D I G1
IC3 3
R1 9 1
16
Temperature and DC Bus Measurements
R 4 91
2 K7
R 49 2
2 K7
R 49 3
2 K7
A N5
R 4 94
P o s U / i GMR _U
P4 _ 2
1K
D7
B A T 54 -0 4W
C 1 2 13
o pt
R1 8 4
A N2 9
V DC
68K
R 1 85
op t
GN D _D I G1
R 4 95
C1 7 6
1 n/ 5 0 V / X7 R
P o s V/G
i MR _ V
P2 _ 0
1K
GN D _ A N A 1
D 8
B A T 5 4-0 4 W
C 1 2 14
o pt
GN D _D I G1
R 4 96
V ANA5 0
+5 . 0 V
Phase Current Sense
L 12
MU R A TA _ B L M2 1P G 22 1 S N
R2 1 5
I_ U
6K 8
1 0 0n / 1 6V / X 7 R 3
C 10 6 4
6 K8
2
3 3 00 p / 10 V / C 0 G
C 1 91
R 47 7
68 0 0p / 1 0V / C 0G
GN D _ A N
op t
G AN1D _ A N A 1
P A CK A G E = 1
1
V+
+
6K 8
A N 14
6K 8
10
C 10 6 7
6 K8
3 3 00 p / 10 V / C 0 G
9
C 1 96
R 48 1
68 0 0p / 1 0V / C 0G
op t
GN D _ A N
G AN1D _ A N A 1
0R
R2 0 0
9 1K
P 4 _3
1K
C 1 82
10 0 p/ 5 0 V / X7 R
R 2 41
2K
G N D _ D I G1
A N1 3
GN D _A N A 1
12
13
Figure 74
N M
P 2 _5
5 1K
A N 31
R 2 39
2K
GN D _D I G1
R2 4 0
G N D _ D I G1
8
- R 48 2
G ND_ DIG 1
P 1 _1 0
1K
C 1 79
10 0 p/ 5 0 V / X7 R
R 1 96
I C 31 C P A C K A GE = 1
L T 16 3 9H S
+
R1 9 3
9 1K
D I O_ 3
0R
R 2 35
R 2 37
2K
B
P 4 _0
5 1K
G ND_ A NA 1
3 K3
R 23 0
GN D _D I G1
P 1 _8
1K
R 1 89
G ND_ A NA 1
I C 31 B P A C K A GE = 1
L T 16 3 9H S
5
R2 2 4
+
C 10 6 5
7
6 K8
3 3 00 p / 10 V / C 0 G
6
- R 47 9
0R _o p t
C 1 94
R 48 0
R2 2 9
68 0 0p / 1 0V / C 0G
op t
0R
GN D _ A N
G AN1D _ A N A 1
R 2 28
R2 1 8
I_ W
R2 3 4
A
C 1 74
10 0 p/ 5 0 V / X7 R
GN D _D I G1
R2 3 8
D I O_ 2
G ND_ A NA 1
I_ V
C 1 2 15
o pt
G N D _ D I G1
0R
R4 7 2
3 K3
R 22 3
R1 8 2
9 1K
A N1 5
-V-R 47 8
D9
B A T5 4 -04 W
Emulated encoder outputs out of AD2S1200
P 4 _1
5 1K
GN D _A N A 1
P2 _ 2
1K
R 1 79
D I O_ 1
C 1 1 61
I C 31 A
L T 16 3 9H S
4
R 2 17
11
G ND_ A NA 1
3 K3
R 21 4
P o s W /G
i MR _ W
General Purpose
Digital IN/OUT
I C 31 D P A C K A GE = 1
L T 16 3 9H S
+
14
-
Input Filter Logic Board v1.3b
Application Note
75
V2.4, 2014-08-11
VANA33
+3.3V
AN6
GND_ANA1
C149
100n/16V/X7R
TC1767
Package = 1
GND_ANA1
AN1
AN2
AN3
AN4
GND_ANA1
AN12
AN13
AN14
AN15
GND_ANA1
U24F
Analog I nput s
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
48
47
46
45
44
43
42
41
60
59
58
57
56
55
50
49
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
40
39
38
37
35
34
33
32
31
30
AN32
AN33
AN34
AN35
29
28
GPTA24
GPTA26
GPTA27
BRKI Nn
U24H
Por t 1: GPTA, SSC1, ADC0, OCDS
GPTA28
GPTA29
74
75
76
77
78
79
80
81
164
160
161
162
163
165
GPTA32
GPTA34
GPTA35
GPTA38
GPTA39
MRST1
SCLK1
Package = 1
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
9
Por t 4: GPTA, SCU
P4. 0/IN28/IN52/OUT28/OUT52
P4. 1/IN29/IN53/OUT29/OUT53
P4. 2/IN30/IN54/OUT30/OUT54/ EXTCLK1
P4. 3/IN31/IN55/OUT31/OUT55/ EXTCLK0
Package = 1
P5_8
P5_9
VD IG33
+3. 3V
1
BC R 183 S
4K 7
U24J
Port 3: GPTA, ASC0/1, SSC0/1, SCU, CAN
136
135
129
130
132
126
127
131
128
138
137
144
143
142
134
133
RXD0A
TXD0A
SCLK0
MRST0
MTSR0
SLSO0
SLSO1
RXDCAN1
TXDCAN1
P3. 0/OUT84/ RXD0A
P3. 1/OUT85/ TXD0
P3. 2/OUT86/ SCLK0
P3. 3/OUT87/ MRST0
P3. 4/OUT88/ MTSR0
P3. 5/SLSO00/ SLSO10/SLSO00&SLSO10
P3. 6/SLSO01/ SLSO11/SLSO01&SLSO11
P3. 7/SLSI01/OUT89/SLSO02&SLSO12
P3. 8/SLSO06/ OUT90/TXD1
P3. 9/OUT91/ RXD1A
P3. 10/OUT92/ REQ0
P3. 11/OUT93/ REQ1
P3. 12/OUT94/ RXDCAN0/RXD0B
P3. 13/OUT95/ TXDCAN0/TXD0
P3. 14/OUT96/ RXDCAN1/RXD1B
P3. 15/OUT97/ TXDCAN1/TXD1
TC1767
U24L
Por t 5: GPTA, MLI0
Package = 1
SW1
P5.0/IN26/IN40/OUT8/OUT40
P5.3/IN43/OUT11/OUT43
P5.8/OUT89/ RDATA0B
P5.9/OUT90/ RVALID0B
P5.10/OUT91/ RREADY0B
P5.11/OUT92/ RCLK0B
P5.12/OUT93/ SLSO07/TDATA0
P5.13/SLSO16/ TVALI D0B
P5.14/OUT94/ TREADY0B
P5.16/OUT95/ TCLK0
CFG7R161
CFG6 R162
CFG5 R163
CFG4 R164
CFG3 R165
CFG2 R166
CFG1 R167
CFG0 R168
680R
680R
680R
680R
1k
680R
680R
680R
Ty co_1- 1571983-1
GND_DIG1
Package = 1
VD IG15
+1. 5V
L7
PAC KA GE = 1
Q6 A
10k
D4
VD IG33
+3. 3V
LE D_LSM676- MQ
6
2
R17 1
Package = 1
VD I G33
+3.3V
10k
VD I G33
+3. 3 V
U 24 B
Os c illat or
102
C lk
XTA L1
V_ D D OS C
V _D D OSC 3
103
XTA L2
VSS OS C
TC 1767 Pack age = 1
105
106
104
B 82422A1 103 K
+
GN D _D I G1
L6
+
B82422A 110 3K
GN D _D I G1
121
POR STn
118
P OR ST
ESR 0
TES TMOD E
ESR 1
120
R 172
2 20R
U24D
GND _D IG1
1 14
1 15
1 11
1 13
1 12
TR STn
TCK
TDI
TD O
TMS
P ac k ag e = 1
TC1767
0R _opt
122
GND _D IG1
1 0k
10K
U 2 4C
General C ont r ol
R 173
V DI G33
+3. 3V
R1 69
Por t 0: GPTA, SCU
P0.0/IN0/HWCFG0/ OUT0/OUT56
P0.6/IN6/HWCFG6/ REQ2/OUT6/OUT62
P0.7/IN7/HWCFG7/ REQ3/OUT7/OUT63
P0.8/IN8/OUT8/OUT64
P0.9/IN9/OUT9/OUT65
P0.14/IN14/REQ4/OUT14/OUT70
TC1767
Package = 1
TC1767
R17 0
AN31
Port 2: GPTA, SSC0/1, MLI 0, MSC0
GPTA40
GPTA41
GPTA42
GPTA43
GPTA44
GPTA45
GPTA46
TC1767
GPTA8
GPTA9
GPTA10
GPTA11
GPTA12
GPTA13
GPTA14
GPTA15
P2.0/IN32/OUT32/OUT28/ TCLK0
P2.1/IN33/TREADY0A/OUT33/ SLSO03/SLSO13
P2.2/IN34/OUT34/OUT29/ TVALI D0A
P2.3/IN35/OUT35/OUT30/ TDATA0
P2.4/IN36/RCLK0A/ OUT36/OUT31
P2.5/IN37/OUT110/OUT37/ RREADY0A
P2.6/IN38/RVALID0A/OUT111/OUT38
P2.7/IN39/RDATA0A/OUT39
P2.8/SLSO04/SLSO14/EN00
P2.9/SLSO05/SLSO15/EN01
P2.10/IN10/OUT0/MRST1A
P2.11/IN11/OUT1/SCLK1A/FCLP0B
P2.12/IN12/OUT2/MTSR1A/SOP0B
P2.13/IN13/OUT3/SLSI11/SDI0
TC1767
U24K
86
87
88
90
GPTA3
145
146
147
148
166
167
173
174
149
150
151
152
168
169
175
176
U24I
P1. 0/IN16/OUT16/OUT72/BRKIN/BRKOUT
P1. 1/IN17/OUT17/OUT73
P1. 4/IN20/EMGSTOP/ OUT20/OUT76
P1. 8/IN24/IN48/MTSR1B/ OUT24/OUT48
P1. 9/IN25/IN49/MRST1B/ OUT25/ OUT49
P1. 10/IN26/IN50/OUT26/OUT50/ SLSO17
P1. 11/IN27/IN51/SCLK1B/OUT27/OUT51
P1. 12/IN16/OUT16/AD0EMUX0
P1. 15/BRKI N/ BRKOUT
TC1767
AN19
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
C 151
10uF/ 6 .3 V
116
119
93
98
107
108
109
110
94
95
96
97
73
72
71
117
AN16
AN17
Package = 1
TC1767
BRKOUTn
GPTA17
GPTA18
GPTA19
GPTA20
GPTA21
U24G
67
66
65
64
63
62
61
36
C 150
10uF/ 6. 3V
C145
C147
GND_ANA1
47n/16V/X7R
VDIG15
+1.5V
47n/16V/X7R
VANA33
GND_ANA1+3.3V
52
26
V_AREF0
V_FAREF
C146
C148
100n/16V/X7R
V_DDM
V_DDMF
V_DDAF
VANA50
+5. 0V
47n/ 16V/X7R
54
24
23
U24E
Analog Power Supply
53
25 V_SSM
51 V_SSMF
27 V_AGND0
V_FAGND
VANA50
+5. 0V
OCDS / J TAG Control
TR ST
TC K/ DA P0
TD I/ BR KI N
TD O/D AP2 / BR KOUT
TMS/ DA P1
Pack age = 1
TC176 7
GN D_D I G1
V D IG 15
+1.5V
GN D _D IG 1
G N D _D I G1
1 00n / 16 V /X 7R
1 00n / 16 V /X 7R
C 159
1 00n / 16 V / X7R
C 158
C 15 7
1 00n /1 6V / X7R
1 00n /1 6V / X7R
C 15 6
C 15 5
C 15 4
1 00n / 16 V/ X7R
1 00n / 16 V/ X 7R
1 00n / 16 V/ X 7R
C 15 3
Power S upply
10
21
68
84
89
99
123
153
170
141
1 00n / 16 V/ X 7R
D igit a l C irc uit r y
V _D D
V_ D D (S B )
V _D D
V _D D
V _D D
V _D D
V _D D
V _D D
V _D D
V_D D FL3
C 15 2
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
C 11 10
V_ D
V_ D
V_ D
V_ D
V_ D
V_ D
V_ D
V_ D
V_ D
V_ D
V _S S
V _S S
V _ SS
V _ SS
V _ SS
V _ SS
V _ SS
V _ SS
V _ SS
V _ SS
V _ SS
11
20
69
83
91
100
124
139
154
171
Pac k age = 1
12
22
70
82
85
92
101
125
140
155
172
1 00n / 16 V/ X 7R
1 00n / 16 V/ X 7R
C 17 1
1 00n / 16 V /X 7R
C 17 0
1 00n / 16 V /X 7R
C 169
1 00n / 16 V / X7R
C 168
1 00n/ 1 6V / X7R
C 16 7
1 00n /1 6V / X7R
C 16 6
1 00n /1 6V / X7R
C 16 5
1 00n / 16 V/ X7R
U 24A
C 16 4
C 16 3
C 16 0
1 00n / 16 V/ X 7R
VD I G3 3
+3. 3V
G N D _D I G1
TC 17 67
VD I G3 3
+3. 3V
C 161
47n / 1 6V /X7 R
C 1 62
4 7n/ 16V/ X7R
GN D _D I G1
Figure 75
Microcontroller TC1767 Pin Assignment Logic Board v1.2
Application Note
76
V2.4, 2014-08-11
V_AREF0
V_FAREF
VANA33
+3.3V
Vref 50
+5. 0V
52
26
C149
100n/16V/X7R
53
25
51
27
Package = 1
GND_ANA1
67
66
65
64
63
62
61
36
AN1
AN2
AN3
AN4
AN5
AN13
AN14
AN15
60
59
58
57
56
55
50
49
GND_ANA1
31
30
GND_ANA1
GND_ANA1
GND_REF1
GND_ANA1GND_ANA1 GND_ANA1
GND_REF1
IC24F
SAK-TC1767-256F133HL
Analog I nputs
48
AN0
AN16 47
AN1
AN17 46
AN2
AN18 45
AN3
AN19 44
AN4
AN20 43
AN5
AN21 42
AN6
AN22 41
AN7
AN23
40
AN8
AN24 39
AN9
AN25 38
AN10
AN26 37
AN11
AN27 35
AN12
AN28 34
AN13
AN29 33
AN14
AN30 32
AN15
AN31
29
AN32
AN34 28
AN33
AN35
GND_ANA1
GND_ANA1
AN17
AN18
AN19
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
GPTA3
GND_ANA1
GPTA8
GPTA9
P0_11
P0_12
AN29
P0_14
AN31
145
146
147
148
166
167
173
174
149
150
151
152
168
169
175
176
I C24G
SAK-TC1767- 256F133HL
Port 0: GPTA, SCU
P0.0/IN0/HWCFG0/OUT0/ OUT56
P0.6/IN6/HWCFG6/REQ2/OUT6/OUT62
P0.7/IN7/HWCFG7/REQ3/OUT7/OUT63
P0.8/IN8/OUT8/OUT64
P0.9/IN9/OUT9/OUT65
Package = 1
GND_ANA1
Package = 1
IC24H
Package = 1
VDI G33
+3.3V
IC24L
IC24K
86
87
88
90
P4_0
P4_1
P4_2
P4_3
Por t 4: GPTA, SCU
P4.2/IN30/IN54/OUT30/OUT54/EXTCLK1
P4.3/IN31/IN55/OUT31/OUT55/EXTCLK0
Package = 1
SAK-TC1767- 256F133HL
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
9
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
P5_8
P5_9
P5_10
P5_11
P5_12
P5_13
P5_15
SW1
R499
R500
R501
R502
R503
R504
R505
R506
100k CFG7
100kCFG6
100kCFG5
100kCFG4
100kCFG3
100kCFG2
100kCFG1
100kCFG0
R161
R162
R163
R164
R165
R166
R167
R168
1K
1K
1K
1K
1K
1K
1K
1K
Ty co_1-1571983-1
GND_DI G1
V D I G15
+1. 5V
Package = 1
C 15 5
1 00n/ 16V /X 7R
1 00n/ 16V /X 7R
1 00n / 16 V / X7 R
C 154
1 00n/16 V / X7 R
GN D _D IG 1
12
22
70
82
85
92
101
125
140
155
172
GN D _D IG 1
C 15 3
10
21
68
84
89
99
123
153
170
141
1 00n/ 16 V / X7 R
V _D D
V _D D ( S B)
V _D D
V _D D
D igit a l C irc uit r y
V _D D
V _D D
V _D D
P ower S upply
V _D D
V _D D
V_D D FL3
C 15 2
P
P
P
P
P
P
P
P
P
P
V _SS
V _SS
V _SS
V _SS
V _SS
V _SS
V _SS
V_S S
V_S S
V_S S
V_S S
V_ D D
V_ D D
V_ D D
V_ D D
V_ D D
V_ D D
V_ D D
V_ D D
V_ D D
V_ D D
C 11 10
1 00n/ 16V/ X 7R
1 00n/ 16V/ X 7R
11
20
69
83
91
10 0
12 4
13 9
15 4
17 1
C 17 1
1 00n/ 16V/ X 7R
C 17 0
1 00n/ 16V/ X 7R
C 16 9
1 00n/ 16V /X 7R
C 16 8
1 00n/ 16V / X7R
C 167
1 00n/ 16 V / X7 R
C 16 6
1 00n/16 V / X7 R
C 16 5
C 16 4
1 00n/ 16V/ X 7R
1 00n/16 V / X7 R
IC 2 4A
P ac k age = 1
SA K- TC 1 767- 256 F 133H L
C 16 3
C 16 0
Port 5: GPTA, MLI0
P5.8/OUT89/RDATA0B
P5.9/OUT90/RVALI D0B
P5.10/OUT91/RREADY0B
P5.11/OUT92/RCLK0B
P5.12/OUT93/SLSO07/TDATA0
P5.13/SLSO16/TVALID0B
P5.14/OUT94/TREADY0B
P5.16/OUT95/TCLK0
VD I G33
+3. 3V
Package = 1
1 00n/16 V / X7 R
Package = 1
SAK- TC1767- 256F133HL
P3_10
P3_11
P3_12
P3_13
RXDCAN1
TXDCAN1
1 00n/ 16V/ X7 R
MRST1
SCLK1
P2_12
C 15 9
GPTA39
Port 3: GPTA, ASC0/ 1, SSC0/1, SCU, CAN
P3.0/OUT84/RXD0A
P3.1/OUT85/TXD0
P3.2/OUT86/SCLK0
P3.3/OUT87/MRST0
P3.4/OUT88/MTSR0
P3.5/SLSO00/SLSO10/ SLSO00&SLSO10
P3.6/SLSO01/SLSO11/ SLSO01&SLSO11
P3.7/SLSI01/OUT89/SLSO02&SLSO12
P3.8/SLSO06/OUT90/ TXD1
P3.9/OUT91/RXD1A
P3.10/OUT92/REQ0
P3.11/OUT93/REQ1
P3.12/OUT94/RXDCAN0/ RXD0B
P3.13/OUT95/TXDCAN0/TXD0
P3.14/OUT96/RXDCAN1/ RXD1B
P3.15/OUT97/TXDCAN1/TXD1
1 00n/ 16V/ X 7R
P2_2
P2_5
136
135
129
130
132
126
127
131
128
138
137
144
143
142
134
133
RXD0A
TXD0A
SCLK0
MRST0
MTSR0
SLSO0
SLSO1
SLSO2
P3_8
C 15 8
BRKI Nn
IC24J
IC24I
Port 2: GPTA, SSC0/1, MLI 0, MSC0
P2.0/IN32/OUT32/OUT28/TCLK0
P2.1/IN33/TREADY0A/OUT33/SLSO03/SLSO13
P2.2/IN34/OUT34/OUT29/TVALI D0A
P2.3/IN35/OUT35/OUT30/TDATA0
P2.4/IN36/RCLK0A/OUT36/ OUT31
P2.5/IN37/OUT110/OUT37/RREADY0A
P2.6/IN38/RVALID0A/OUT111/OUT38
P2.7/IN39/RDATA0A/OUT39
P2.8/SLSO04/SLSO14/ EN00
P2.9/SLSO05/SLSO15/ EN01
P2.10/IN10/OUT0/MRST1A
P2.11/IN11/OUT1/SCLK1A/FCLP0B
P2.12/IN12/OUT2/MTSR1A/ SOP0B
P2.13/IN13/OUT3/SLSI11/SDI 0
74
75
76
77
78
79
80
81
164
160
161
162
163
165
P2_0
1 00n/ 16V/ X 7R
GPTA18
GPTA19
GPTA20
P1_5
P1_6
P1_7
P1_8
P1_9
P1_10
GPTA27
Por t 1: GPTA, SSC1, ADC0, OCDS
P1. 0/IN16/OUT16/OUT72/ BRKIN/BRKOUT
P1. 4/IN20/EMGSTOP/OUT20/OUT76
P1. 8/IN24/IN48/MTSR1B/OUT24/OUT48
P1. 9/IN25/IN49/MRST1B/OUT25/ OUT49
P1. 10/IN26/IN50/OUT26/OUT50/ SLSO17
P1. 11/IN27/IN51/SCLK1B/OUT27/OUT51
P1. 15/BRKI N/ BRKOUT
C 15 6
116
119
93
98
107
108
109
110
94
95
96
97
73
72
71
117
BRKOUTn
C 15 7
C145
C147
47n/16V/X7R
V_DDM
V_DDMF
V_DDAF
47n/16V/X7R
54
24
23
C148
100n/16V/X7R
IC24E
Analog Power Supply
C146
VANA15
+1.5V
47n/ 16V/X7R
VANA33
+3.3V
V_SSM
V_SSMF
V_AGND0
V_FAGND
VANA50
+5. 0V
V D I G33
+3.3V
G N D _D I G1
C 16 1
100n / 16 V/ X7R
GN D _ D I G1
VD I G1 5
+1.5V
L7
VD I G33
+3.3V
B82 422A 1103K
V D I G33
+3. 3 V
1
10k
2
10 k
6
118
POR S T
ES R 0
TESTMOD E
ES R 1
C lk
1 02
1 03
I C 24 B
S AK -TC 17 67- 256 F133H L
Os c illa t or
XTAL1
XTAL2
V_D D OSC
V_D D OSC 3
VSS OSC
VD I G33
+3.3V
105
106
104
GN D _D I G1
L6
B82 422A 1103K
Pa c k ag e = 1
C 1 50
10u/ 10V/ X7R
2 20R
GN D_ D I G1
GN D _D I G1
GN D _D IG1
12 2
12 0
10 K
121
R 173
10 K
R 169
VD I G33
+3. 3V
I C 24C
SA K- TC 1767- 25 6F13 3H L
Gen eral C on trol
R 1 72
D4
V D IG33
+3. 3V
P OR STn
C 1 51
10u/ 10V/ X7R
PA C KA GE = 1
Q6A
LE D_L SM 676- M Q
R 1 71
4K 7
BC R 183S
0R _opt
R 17 0
P ack ag e = 1
TR S Tn
TC K
TD I
TD O
TMS
GN D _ D I G1
11 4
11 5
11 1
11 3
11 2
I C 24D
SA K- TC 1767 -256F1 33H L
OCDS / JTAG Cont rol
TR ST
TC K/ D AP0
TD I/ BR K IN
TD O/ D A P2/B R KOU T
TMS/ D AP1
Pac k age = 1
Figure 76
Microcontroller TC1767 Pin Assignment Logic Board v1.3b
Application Note
77
V2.4, 2014-08-11
VD I G3 3
+ 3.3 V
R7
10K
R9
10K
U1
1 00n/ 16V/ X7R
C 29
R8
10K
8
4
7
3
6
5
2
SC K
SI
SO
H OLD
1
WP
CS
AT2 5256 A-10 TQ-2 .7
C Sn
VC C
GN D
SC K
SI
SO
R 10
opt
GN D _D IG1
Figure 77
EEPROM (same for Logic Board v1.2 and Logic Board v1.3b)
VANA50
+5.0V
Unit temperature sensor (Ambient)
Position: bottom of Logic Board
Temp = 10mV/°C + 500mV
Temp @ -40C: +100mV
Temp @ +125C: +1,750V
LPF: -3dB @ 32Hz
C1211
100n/50V/X7R
IC 54
1
VCC
R 487
Vout
2
270K
GND
3
Temp_Board
LM50C IM3
C1212
22n/50V/X7R
G ND _AN A1
Figure 78
On-Board Temperature Measurement (Logic Board v1.3b only)
Application Note
78
V2.4, 2014-08-11
4.12.2
Assembly Drawing
Figure 79
Assembly Drawing of the Logic Board v1.2 (Top)
Application Note
79
V2.4, 2014-08-11
Figure 80
Assembly Drawing of the Logic Board v1.3b (Top)
Application Note
80
V2.4, 2014-08-11
Figure 81
Assembly Drawing of the Logic Board v1.2 (Bottom)
Application Note
81
V2.4, 2014-08-11
Figure 82
Assembly Drawing of the Logic Board v1.3b (Bottom)
For detail information use the zoom function of your PDF viewer to zoom into the drawings on Figure 79,
Figure 80, Figure 81 and Figure 82.
Application Note
82
V2.4, 2014-08-11
4.12.3
Layout
Layout of the Logic Board v1.2 is shown on Figure 83 (Top Layer), on Figure 84 (Layer 2), on Figure 85 (Layer
3) and on Figure 86 (Bottom Layer).
Layout of the Logic Board v1.3b is shown on Figure 87 (Top Layer), on Figure 88 (Layer 2), on Figure 89 (Layer
3), on Figure 90 (Layer 4), on Figure 91 (Layer 5) and on Figure 92 (Bottom Layer).
Figure 83
Logic Board v1.2 - Top Layer
Application Note
83
V2.4, 2014-08-11
Figure 84
Logic Board v1.2 - Layer 2
Application Note
84
V2.4, 2014-08-11
Figure 85
Logic Board v1.2 - Layer 3
Application Note
85
V2.4, 2014-08-11
Figure 86
Logic Board v1.2 - Bottom Layer
Application Note
86
V2.4, 2014-08-11
Figure 87
Logic Board v1.3b - Top Layer
Application Note
87
V2.4, 2014-08-11
Figure 88
Logic Board v1.3b - Layer 2
Application Note
88
V2.4, 2014-08-11
Figure 89
Application Note
89
V2.4, 2014-08-11
Figure 90
Application Note
90
V2.4, 2014-08-11
Figure 91
Application Note
91
V2.4, 2014-08-11
Figure 92
Logic Board v1.3b - Bottom Layer
Application Note
92
V2.4, 2014-08-11
4.12.4
Bill of Materials
Table 8
Bill of Materials for Hybrid Kit for the HybridPACK™2 Logic Board v1.2
Reference
Value / Device
Package
C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C13,C14, 10n/50V/X7R
C15,C16,C17,C18,C19,C23,C24,C25,C26,C27
, C28
C0402
C29,C64,C65,C66,C68,C70,C71,C85,C87,C89 100n/16V/X7R
, C95,C98,C106,C107,C109,C111,C112,C113,
C114,C115,C148,C149,C152,C153,C154,C15
5,C156,C157,C158,C159,C160,C163,C164,C1
65,C166,C167,C168,C169,C170,C171,C1110
C0402
C60,C61,C62,C63,C67,C69
100pF/50V/COG
C0402
C75
4u7/16V/X7R
C1206
C76,C77,C80,C81,C104
10n/16V/X7R
C0402
C78,C88,C90
10uf/10V/X7R
C1206
C79,C82
4u7/25V/X7R
C1206
C83,C84
20pF/50V/COG
C0402
C86
22u/16V/X7R
C1210
C91,C92
220nF/50V/X7R
C0805
C93
100uF/35V
C1010
C94
100uF/10V
C3528
C96
2.2nF
C0402
C97
10uF/6.3V/X7R
C1206
C105,C108
22uF/6.3V/X7R
C1206
C110
4.7n/50V/X7R
C0603
C143,C1111
22uF/16V/X7R
C1210
C144,C1112
100n/25V/X7R
C0603
C145,C146,C147,C161,C162
47n/16V/X7R
C0402
C150,C151
10uF/6.3V
C3216
C172,C173,C174,C175,C176,C177,C178,C17 100p/50V/X7R
9,C180,C181,C182,C183,C184,C185,C186,C1
87,C189,C191,C193,C194,C196,C198,C199,C
200,C201
C0402
D1
MBRS340T3
SMC
D2
BZV55/C13
SOD80
D3
1SMB30AT3
SMB
D4
LED_LSM676-MQ
L0805
FL1
B82789C0104N001
B82789C0
J1
Jumper
K1
TW-12-06-L-D-475-SM-A
Application Note
93
12POL
V2.4, 2014-08-11
Table 8
Bill of Materials for Hybrid Kit for the HybridPACK™2 Logic Board v1.2 (cont’d)
Reference
Value / Device
Package
L1,L2,L5,L8
MURATA_BLM21P221SN
L0805
L3
47uH/B82464G4473M
B82464G4
L6,L7
B82422A1103K
C1210
Q1
SPD09P06PLG
TO252-3
Q2,Q3
BC847BL3
TSLP3-1
Q4
IPD90P03P4L-04
TO252-003
Q6
BCR183S
SOT363
R1,R2,R3,R4,R5,R6,R101,R115,R116,R118,
R122,R128,R169,R174,R177,R186,R195
10K
R0603
R7,R8,R9,R71,R73,R173
10K
R0402
R10
opt
R0402
R72,R87,R89,R91,R94,R97
100R
R0603
R74,R75,R76,R77,R78,R79,R80,R81,R82,R83 1K
, R84,R85,R86,R88,R165
R0402
R90,R93,R96,R99
15K
R0603
R92,R95,R98,R100,R134,R135
1K
R0603
R102,R104,R106,R108,R121,R224,R316
0R
R0603
R103,R105,R107,R109,R110,R149,R154,R17 opt
6,R181,R185,R192,R194,R202,R203,R208,R2
17,R228,R235,R236
R0603
R111
20K
R0603
R112
39K
R0603
R113
0R
R1210
R114
47mR/0.33W
R0805
R119
680R
R0603
R131,R132
60R
R0603
R133
5K1
R0603
R150,R151,R153,R171
4K7
R0603
R155,R156,R157,R158,R159,R160
opt
R0603
R161,R162,R163,R164,R166,R167,R168
680R
R0402
R170,R229,R315
0R_opt
R0603
R172
220R
R0603
R175,R178,R179,R180,R184,R187,R188,R18 51K
9,R191,R196,R197,R198,R199,R204,R205,R2
06,R213,R214,R222,R223,R230,R231,R234,R
238,R240
R0603
R182,R183,R190,R193,R200,R201,R207,R21
0,R216,R227,R237,R239,R241
91K
R0603
SW1
Tyco_1-1571983-1
DIP
U1
AT25256A-10TQ-2.7
TSSOP-08
Application Note
94
V2.4, 2014-08-11
Table 8
Bill of Materials for Hybrid Kit for the HybridPACK™2 Logic Board v1.2 (cont’d)
Reference
Value / Device
Package
U2
74ALVC164245DGG
TSSOP-48
U4
LT1639HS
SO-14
U6
LMH6672
SO8
U8
AD2S1200YST
LQFP-44
U9
74LVC1G04GW
SOT353
U11
HCM49 8.192MABJ-UT
HCM49
U12
TPS76733QD
SO8
U13
TLE6389-2GV50
P-DSO-14
U14
TPS76715QD
SO8
U16
EH2645ETTTS-20.000M
SM_Q_EH26
U17
TLE6250GV33
SO8
U18
MAX3232EIPWRQ1
TSSOP-16
U23
MAX6369KA-T
SOT23-8
U24
LQFP-176
U25
TLE4266GSV10
SOT223-4
X1-SIG1
Harwin M80-5123442
34POL
X3-OCDS1
HEADER 8X2
16POL
U58
MAX6457UKD3A-T
SOT23-5
Table 9
Bill of Materials for hybrid Kit for HybridPACK™2 Logic Board v1.3b
Reference
Value / Device
Package
C29,C64,C68,C70,C71,C106,C107,C109,C11 100n/16V/X7R
1,C112,C113,C114,C115,C123,C148,C149,C1
52,C153,C154,C155,C156,C157,C158,C159,C
160,C161,C163,C164,C165,C166,C167,C168,
C169,C170,C171,C1110,C1210
C0402
C65,C66,C1127,C1129,C1131,C1132,C1133,
C1160,C1161,C1163,C1164
100n/16V/X7R
C0603
C75
4u7/16V/X7R
C1206
C76,C77,C80,C81,C104
10n/16V/X7R
C0402
C78
10uF/10V/X7R
C1206
C79,C82
4u7/25V/X7R
C1206
C83,C84
20pF/50V/COG
C0402
C85,C1151,C1153
100n/50V/X7R
C0603
C86,C1135,C1136,C1154,C1155
22u/16V/X7R/F_1463575
C1210
C92
220nF/100V/C3216X7R2A2 C1206
24KT5
C93,C1152
100uF_35V_MAL21409700 C1010_CAP_Pin1_Plus
1E3
C105,C108
22uF/6.3V/X7R
Application Note
95
C1206
V2.4, 2014-08-11
Table 9
Bill of Materials (cont’d)for hybrid Kit for HybridPACK™2 Logic Board v1.3b
Reference
Value / Device
Package
C110
4.7n/50V/X7R
C0603
C143,C1111
22uF/16V/X7R
C1210
C144
100n/25V/X7R
C0603
C145,C146,C147
47n/16V/X7R
C0402
C150,C151,C1157,C1158
10u/10V/X7R
C1206
C172,C173,C176,C178,C180,C183,C184,C18 1n/50V/X7R
7,C1169,C1170,C1171,C1173,C1174,C1175,
C1176,C1177,C1178,C1179,C1180,C1183,C1
184,C1185,C1189,C1190,C1191,C1192,C119
3,C1194,C1195,C1196,C1197
C0402
C174,C179,C182
100p/50V/X7R
C0402
C191,C194,C196
6800p/10V/C0G
C0603
C1040,C1041,C1042,C1043,C1044,C1045,C1 10p/50V/X7R
147,C1148,C1149
C0603
C1064,C1065,C1067
3300p/10V/C0G
C0603
C1112,C1167
100n/50V/X7R/C0805F104K5
C0805
C1128,C1130
10p/16V/X7R
C0603
C1142
4u7/10V/X7R
C1210
C1144,C1146
4u7/10V/X7R/F_9402195
C1206
C1145
1u/25V/X7R/F_1637035
C0603
C1150
680n/50V/F_1414702
C1206
C1156
220n/25V/X7R/F_1414626
C0603
C1159
1n/16V/X7R
C0402
C1166
4.7u/50V/X7R/C1210F475K5
C1210
C1172,C1181,C1182,C1187,C1188,C1201,C1 1n/50V/X7R_opt
202,C1203,C1204,C1205,C1206,C1207,C120
8,C1209
C0402
C1211
100n/50V/X7R
C0805
C1212
22n/50V/X7R
C0603
R10,R103,R105,R107,R109,R110,R176,R181, opt
R185,R192,R194,R202,R203,R208,R477,
R480,R481,C1213,C1214,C1215,C1216,
C1217
R0603
D1
MBRS340T3
SMC
D2
BZV55/C13
SOD80C_Pin1_Cathode
D3
1SMB30AT3
SMB
D4
LED_LSM676-MQ
Vishay_TLMK2300
D5,D6
SS12_1A_If_20V_Vr
DO214AC_SMA_Pin1_Cathode
D7,D8,D9
BAT54-04W
SOT323
FL1
B82789C0104N001
EPCOS_B82789C0
Application Note
96
V2.4, 2014-08-11
Table 9
Reference
Value / Device
Package
IC1
AT25256A-10TQ-2.7
TSSOP8
IC2
74ALVC164245DGG
TSSOP48
IC4,IC31
LT1639HS
SO14
IC6
LMH6672
SO8
IC8
AD2S1200YST
LQFP44_P0_8
IC13
TLE7368E
SO36-38
IC16
EH2645ETTTS-20.000M
Ecliptek_EH2645
IC17
TLE6250GV33
SO8
IC23
MAX6369KA-T
SOT23-8
IC24
LQFP176_p0_50
IC25
TLE4266GSV10
SOT223
IC26
DS92LV010
SO8
IC28,IC30
74LVC2G04GW
SOT363
IC29
74LVCH16T245DL
SSOP48
IC32
DS90LV031A
SO16-1
IC33
AM26C32QD
SO16-1
IC52
MAX3232EIPWRQ1
TSSOP16
IC53
MAX6143AASA50
SO8
IC54
LM50CIM3
SOT23
J1
Jumper
jumper_2way
K1
TW-12-06-L-D-475-SM-A
Samtec_TW-12-06-L-D-475-SM-A
K2
Harwin M80-5125042P
Harwin_M80-5125042P
K3-OCDS
HEADER 8X2
tyco_1761686-6
L1,L8,L9,L10,L11,L12
MURATA_BLM21PG221SN L0805
L3
WE_7447709470
WE-PD_744770
L5
MURATA_BLM21P221SN
L0805
L6,L7
B82422A1103K
L1210
Q2
BDP949
SOT223
Q4
IPD90P03P4L-04
TO252-3
Q6
BCR183S
SOT363
R1,R2,R3,R4,R5,R6,R7,R8,R9,R71,R73,
R173,R174,R177,R186,R195,R471,R473,
R474,R475,R476
10K
R0402
R74,R75,R76,R77,R78,R79,R80,R88,R92,
R95,R98,R100,R134,R135,R161,R162,R163,
R164,R165,R166,R167,R168,R180,R187,
R197,R234,R238,R240,R456
1K
R0402
R90,R93,R96,R99
15K
R0402
R101,R128,R169
10K
R0603
Application Note
97
V2.4, 2014-08-11
Table 9
Reference
Value / Device
R102,R104,R106,R108,R478,R479,R482,R49 0R
7
Package
R0603
R113
SMK-R000 / Isabellenhuette R1206
R131,R132
60R
R0603
R133
5K1
R0402
R149,R154
opt
R0402
R150,R151,R153
4K7
R0402
R155,R156,R158,R160
2K4/0.1%
R0603
R157
390/0.1%
R0603
R159
3K3/0.1%
R0603
R170,R224,R498
0R_opt
R0603
R171
4K7
R0603
R172
220R
R0603
R175,R184,R191,R198,R205
68K
R0402
R178,R179,R188,R189,R196,R199
51K
R0402
R182,R193,R200
91K
R0402
R183,R190,R201,R237,R239,R241
2K
R0402
R214,R217,R223,R228,R230,R235
6K8
R0402
R215,R218,R472
3K3
R0402
R229
0R
R0402
R429,R430,R431,R447
100R
R0603
R483,R484,R485
5K_pot_0,25W_20%_Bourn Bourns_3314J
s_3314J_opt
R486
0R / 0.1%
R0402
R487
270K
R0603
R488,R489,R490,R494,R495,R496
1K
R0603
R491,R492,R493
2K7
R0603
R499,R500,R501,R502,R503,R504,R505,
R506
100k
R0402
SW1
Tyco_1-1571983-1
Tyco_1-1571983-1
SW2
SW DIP-4/SM
SO8
TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9
Testpad_SMD_Ettinger
Ettinger_12_18_815_testpad
U1
HCM49 8.192MABJ-UT
Citizen_HCM49
Application Note
98
V2.4, 2014-08-11
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG

Evaluation Kit for Applications with HybridPACK™2 Modules

Transcription

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