From 3D Toolbox to 3D Integration

Transcription

From 3D Toolbox to 3D Integration:
Examples of Successful 3D Applicative
Demonstrators
N.Sillon
© CEA. All rights reserved
Agenda





Introduction
2,5D: Silicon Interposer
3DIC: Wide I/O Memory-On-Logic
3D Packaging: X-Ray sensor
Conclusion
TSV SUMMIT – N.Sillon | 2
What could be a silicon chip in 10 Years…
Stacked advanced logic +
Memory
Moving parts (MEMS)
Stacked Memory
Passives components
 Of course, it seems to be:






Optical I/O
Too expensive
Not compatible with an efficient supply chain
Not repairable
Difficult to test
Not reliable
….
Thermal management
A silicon interposer…
Silicon interposer 5 years ago…
 It seemed to be:






Too expensive
Not repairable
Difficult to test
Not reliable
…
Flip Chip
Avec TSV
Si Interposer
 And Today: Commercially available in foundries and
used by major fabless
Source: Xilinx
Source: Altera
What could be a silicon chip in 10 Years…
 Of course, it seems to be:






Too expensive
Not repairable
Difficult to test
A good target to drive 3D integration
Not reliable
Toolbox developments
….
A lot of intermediate stand alone products
(and businesses…).
Stacked DRAM or Flash
Memory on
Application Processor
MEMS on its IC driver
Multichip Interposer (2,5 D) for FPGA
Focus 3 applications…3 ways of collaboration with Leti
Agenda





Introduction
3D Packaging: Imaging
Conclusion
Silicon Interposer for supercomputers
3 years
Common Lab, 3
assignes
Process flow for interposer
 Example of Leti-Shinko High Density interposer
<<<
<<
Total size: 26x26mm, Thickness 100µm
Micro Copper bumps: Pitch 50µm, 100000/interposer
Damascene: 2 line and 1 via levels, CDmin 0.5µm
TSV: 10x100µm
RDL and passivation: CDmin 10µm
High pillars: pitch 500µm, height
Process flow description: front side
TSV etching
TSV insulation
TSV and line 1 metallization
Damascene levels
Micro bumps
Temporary bonding
Process flow description: back side
Back side thinning and TSV exposure
Backside Redistribution Layer
Backside passivation and High Pillars
Debonding
Physical characterisation: cross section
 Good integrity of the overall structure: no delamination
 No copper extrusion or residue between TSV and Line 1
 No copper extrusion or residue between TSV and Backside RDL
TSV SUMMIT – N.Sillon
| 12
Process flow description: Assembly
Silicon interposer
After mounting
(4chip , Si-IP, Organic substrate)
Silicon interposer
chip
chip
Organic substrate
On Going Developments
 BOW/Constraint management
Dev. of low stress BEOL
Insertion of compensation layers
On Going Developments
 BOW/Constraint management
 Underfill materials for high troughput
 CTE mismatch compensation between organic
substrate and Silicon Interposer
 Evolution towards Silicon Package
Agenda





Introduction
3D Packaging: X-Ray sensor
Conclusion
3D ST-Leti: from Lab to Fab
Prototyping/Production
Industrial maturity and stability
Short Cycle time
2 complementary Lines
Maturity
Advanced Dev
Design Teams
STE/STM/Leti
Advanced flows
Advanced demonstrators
Benchmark tools
Advanced modules
3D Integration successes Leti-STMicro
ST implement TSV for
CMOS image sensors in
300mm
(Process from Leti)
300mm R&D Line
for 3D Integration
@ Leti
Wide I/O
Memory + Logic
stack.
Partitioning
45nm/130 nm
Demonstrator
(Set Top Box
application)
Partitioning
Analog/Logic
Demonstrator.
HDMI Product
2008
2010
2011
2012
| 18
Wide I/O DRAM stacking on Logic
 Objectives
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SoC in advanced CMOS node
Quad-channel Wide I/O DRAM*
Bandwidth >10GByte/s
Reduced power consumption
 Face to back 3D integration
 Top die: μ-Bumps
 Bottom die: Bumps, TSV & μ-Pillars
 Die-to-die stacking on BGA
* JEDEC standard JESD229
TSV SUMMIT – N.Sillon 19
Wide I/O : Design
Channel 1
Channel 0
Bank 0
Bank 1
Bank 0
Bank 1
Bank 2
Bank n
Bank 2
Bank n
Bank 0
Bank 1
Bank 0
Bank 1
Bank 2
Bank n
Bank 2
Bank n
Channel 2
Design STE/Leti
• Mag3D platform: Low power, NoC based
architecture
Channel 3
Commercial memory
•
Wide-IO memory: Power
efficient and high bandwidth
Temporary Bonding/debonding
Back side TSV reveal
Si
Advanced modules
SiO2
SiO2/Ta
Cu
Micro pillar
Wide I/O Daisy Chain
Maturity
Advanced Dev
Advanced flows
Benchmark tools
No TSV leakage
Advanced modules
> 98% yield on TSV chain
Prototyping/Production
WIDE IO DRAM
Industrial maturity and stability
Short Cycle time
Maturity
CuNiAu
µ-pillar
SoC
Advanced Dev
TSV
Wide I/O demonstrator
Advanced flows
Benchmark tools
Bump
BGA
Advanced modules
Memory on Application Processor
• Wioming SoC [1], co-designed by CEA / ST-Ericsson
• 73 mm2, 1250 TSV and ~1000 Bumps Bottom / BGA
• Wide I/O DRAM 1GB, 4x128 bits, 200MHz
• 3D Process and test performed in Grenoble
WIDE IO DRAM
SoC
Wioming SoC floorplan
WIDE IO DRAM
CuNiAu
µ-pillar
SoC
TSV
 Full functionality demonstrated with high final test yield
 Performances exceed JEDEC Wide IO standard
• Bandwidth
• Power consumption
Bump
BGA
[1] A Three-Layers 3D-IC Stack including Wide IO and a 3D NoC - a Practical Design Perspective – P. Vivet & al, RTI 2011
Agenda

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
Introduction
3D Packaging: : X-Ray sensor
Conclusion
Open 3D: starting point
 TSV / 3D can be a solution for a lot of devices,
whatever the reason (compacity, heterogeneity, cost,
performance…)
 A complete 3D development is long and costly
(techno developement, specific design,…).
 Mature/flexible technologies can be used for low
cost demonstrators
Open 3D™ : Boost 3D diffusion in applications
Our goal: facilitate access to 3D technology
Need 3D on your wafers?
Open 3D™ TechBox
3D Design & Layout
3D Technology
3D Packaging
First success story : Open 3D™ for CERN
high spatial, high contrast resolving CMOS
pixel read-out chip working in single photon
counting mode
It can be combined with different
semiconductor sensors which convert the Xrays directly into detectable electric signals.
This represents a new solution for various Xray and gamma-ray imaging applications.
 Project started On June 2011
 First wafers delivered on January 2012
TSV
Design
Test structures
Process Flow
Wafer view
Single chip
Technology
RDL
Back side UBM
Medipix wafer after front
side UBM
TSV
Accoustic image of
the bonding interface
Thin wafer on tape
Wafer level Electrical Tests
Functionnal
tests on ASICS
Contact UBM
P01-Résistance cum ulée Chaine de 2 TSV (VSS)
100
90
80
70
%
60
TSV
2 TSV chain resistance
50
Test RDL
40
Test Final
30
20
10
0
5. 20E -01
5. 40E -01
5. 60E -01
5. 80E -01
6. 00E -01
6. 20E -01
6. 40E -01
Ohm s
Chip Delivery & test
Test Board & socket
GELPAK of 16 diced chips
(Courtesy of Jerome ALOZY / CERN)
TSV SUMMIT – N.Sillon
| 30
1
1
 W24-H2 DAC dependency
(Courtesy of Jerome
ALOZY / CERN)
Next step: Integration
Conclusion
 We have in mind complete 3D integrated systems…with
intermediate products.
 Concrete 3D integrations demonstrators have been achieved
with partners, allowing low capex validation and anticipation
of integration problems for manufacturing
 Silicon Interposer
 3D IC – memory on logic
 Xray Detector
 Toolbox development is still on going for next gen…with
tools/materials suppliers
Warm Thanks to all 3D community…
Merci de votre
attention

From 3D Toolbox to 3D Integration

Transcription

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