DRN 8080B본문_수출

Transcription

DRN 8080B본문_수출

INTRODUCTION
This service manual provides a variety of service
information. It contains the mechanical structure
of the DVD-ROM Drive together with mechanical
adjustments and the electronic circuits in
schematic diagram. This DVD-ROM Drive was
manufactured and assembled under our strict
quality control standards and meets or exceeds
industry specifications and standards.
GENERAL FEATURE
• ATAPI interface
• Ultra Slim type DVD-ROM drive. (Height : 12.7 mm)
• Ability to read single sided, single layer,
or dual layer DVD media
• ATA4, Ultra DMA33 support
• DVD-5, DVD-9, DVD-10 Capable
• Sustained Transfer Rate 10,800 KB/sec (Max.)
DVD media & 3600 KB/sec (Max.) CD-ROM Media
• (150)ms Average Access time in DVD mode
• (130)ms Average Access time in CD mode
• Support 8x(Max.) Rotational Modes in DVD mode
• Support 24x(Max.) Rotational Modes in CD mode
•
•
•
•
•
•
•
•
•
•
•
DVD-R, CD-R, CD-RW read capability
Drawer load
MPC level 3 compatible
Photo CD : Single and Multisession support
XA ready
Subcode Q
Red Book Audio
Analog Line out
Digital Audio through Atapi interface
Energy conservation modes
Horizontal/Vertical operation
SPECIFICATIONS
1. SUPPORTED SYSTEM
• IBM Compatible Pentium 133MHz or Above
• MPEG II Board or Software MPEG II Program
2. SUPPORTED OS
• MS-DOS (Ver 3.1 or Higher)
• Windows 3.1/95/98 Higher
• Windows NT (Ver 3.5, Ver 4.0) or Higher
• OS/2 Warp (Ver 3.0 & 4.0) or Higher
3. GENERAL PERFORMANCE
• Rotational Speed........................................................DVD : 3.3X~8X (CAV) Approx. 4,800 rpm
(single layer - Press)
2.0X~4X (CAV) Approx. 3,800 rpm(DVD-R)
2.0X~4X (CAV) Approx. 4,200 rpm(dual layer)
CD-ROM : 10X~24X (CAV) Approx. 4,650~5,000rpm
CD-RW, V-CD, Audio CD : 6X~12X (CAV) Approx. 3,200rpm
• Data Transfer Rate
* Sustained Data Transfer Rate................................DVD(Outer side)
DVD (Inner side)
CD (Outer side)
CD (Inner side)
:
:
:
:
Approx. 10,800kbytes/sec
* Burst (ATAPI) .........................................................16.67 Mbytes/sec (PIO Mode 4)
16.67 Mbytes/sec (Muliword DMA Mode 2)
33.3 Mbytes/sec (Ultra DMA)
• Access Time (Including Latency)
* Random Access*1 ..................................................DVD : 150ms Typical (8X)
CD : 130ms Typical (24X)
* Full Access (First to Last Block)*2 ..........................DVD : 240ms Typical (8X)
CD : 220ms Typical (24X)
Notes :
*1 : Average Random Seek time is the typical value of more than 100times including latency and error
correction time.
*2 : Average Seek time is the typical value of more than 100times including latency and error correction time.
Test Disc : a CD : A-BEX TCDR-701
b DVD : A-BEX TDV-520 or TEAC MDVD411/MDVD-191or TDR-820
• Data Buffer Capacity .................................................. 512Kbytes
3
4. POWER REQUIREMENTS
• Voltage .......................................................................+5V DC + 5%
• Ripple .........................................................................+5V : 100mVp-p
• Seek ..........................................................................1300mA Max, 960mA Typical
• Normal Read ..............................................................1,000mA Max, 880mA Typical
• Standby & sleep .........................................................40mA Max
5. AUDIO PERFORMANCE
• Frequency Response .................................................20Hz~20KHz ( + 3dB)
• S/N Ratio (IHF-A+20kHZ LPF) ...................................80 dB (Typical at 1 KHz 0dB)
75 dB (Limit at 1 KHz 0dB)
• T.H.D. (IHF-A+20kHZ LPF) ........................................0.05% (Typical at 1 KHz 0dB)
0.15% (Limit at 1 KHz 0dB)
• Channel Separation (IHF-A+20kHZ LPF)...................75 dB (Typical)
70 dB (Limit)
• Output Level (1kHz 0dB) 47KΩ Load .........................1.0Vrms + 20%
4
DISASSEMBLY
1. CABINET
3. FRONT PANEL
A. Release 3 screws (A).
B. Lift up the Cabinet in the direction of arrow (1).
(See Fig.1)
A. Release 2 screws (C) and remove the Front Panel.
B. At this time, be careful not to damage the 2 hooks (a) of
the it. (See fig.3)
C. Release 3 screws (D) and remove the Cover Bottom (3).
CABINET
(A)
(A)
(A)
HOOK (a)
(2)
(1)
(3)
FRONT PANEL
2 HOOKS
Fig.1
(D)
2. MAIN CIRCUIT BOARD
(B)
COVER BOTTOM
(D)
A. Inset and press a rod in the Emergency Eject Hole and
then the CD Tray will open in the direction of arrow (2).
B. Release 2 screws (B).
C. Remove the Main Circuit Board.
(D)
(C)
(C)
Fig.3
4. BASE PICK-UP
(B)
A. Remove the Base Pick-up (4).
MAIN CIRCUIT BOARD
(4)
BASE PICK-UP
(2)
Emergency Eject Hole
Fig.2
Fig.4
5
DESCRIPTION OF CIRCUIT
1. APC (Automatic Power Control) Circuit
1-1. APC Circuit Constitution
IC201 SSI3723
PN201
DVD-LD(LASER DIODE)
14
15
LD
DVDMD
DVDLD
Monitor
Diode
23
DVD PD
21
DVD LD
Vcc
5V
C233
R213
Q202
C234
CD-LD(LASER DIODE)
10 CDMD
Monitor
Diode
9
LD
24 CD PD
Vcc
5V
CDLD
R202
22
C203
CD LD
Q201
C207
PICK-UP Unit
1-2. APC Circuit Operation
It drives the LD to the constant current and adjusts the LD input current , so that the output current is
constant.
IC201 (SSI3723) Pin 23 , 24 : PD IN, Monitor Input of Laser diode APC
IC201 (SSI3723) Pin 21 , 22 : LD OUT, External Current Driver Control output of the LD (Laser Diode)
The detect current from the monitor diode converts to the I/V (Current/Voltage) at the external resistor.
Beforehand, it adjusts a fixed level over for a standard GND.
If this voltage inputs to the PD IN (IC201 Pin 23, 24), it is amplified about 36.4 times (about 31.2dB).
So this voltage outputs from the LD OUT (IC201 Pin 21, 22).
The LD driving element (Q201/Q202) uses the TR more than 200hfe, and controls LD OUT (IC201 Pin 21,
22) connected to the base of Q201/Q202.
The APC control for the each DVD/CD sets Register of the IC201 (SSI3723) according to Disc in the
µ-COM.
15
2. RF Amplifier Circuit
2-1. RF AMP Constitution
IC201
SSI3723
Pick-up Unit
PN201
E
A
C
B
F
F
1
13
11
16
17
19
20
D
C
B
A
CD (A, B, C)
13 14
15 16
DVD (A, B, C, D)
9 10
11 12
GCA
3 4
5 6
GCA
AMP
AGC
BUFF
40 FE
To IC301 3
MUX
4
4
DVD
(A2, B2, C2, D2)
E
SUM
AMP
Phase
Detector
EQ
MUX
1
18
CD (E, F)
12
17
18
GCA
39 TE
To IC301 143
AMP
AGC
DVD RF
1
MUX
RF SIN
63
ATT
57 RF AC
To IC301 13
To IC401 117
64
RF DC
16
EQ
3. Focus/Tracking/Sled Servo Circuit
3-1. FOCUS, TRACKING & SLED SERVO PROCESS
FOCUS & TRACKING SERVO PROCESS
IC201
RF AMP
SSI3723
Pick - Up
E
CD(A. B. C. E. F)
A
(A. B. C)
C
B
FOCUS
ERROR
DETECTOR
(A. B. C.D)
5
FE
F
E-F
F
Generating
TE
DVD(A. B. C. D.)
D
C
B
A
6
E
Generating
(A2. B2. C2 .D2) DPD TE
TE/
DPD TE
SELECTOR
TE
FOCUS &
TRACKING
ACTUATOR
IC301
CD/DVD SERVO & DSP
CXD3011R
T+
T-
F+
TE
FE
F-
SLED
Control
Signal
IC601
DRIVE
BA5918
A/D
LEVEL SHIFT
LEVEL SHIFT
FAO
DIGITAL
EQUALIZER
D/A
(AUTO ADJUSTMENT
CIRCUIT)
TAO
IC601
SLED(Feed) SERVO PROCESS
LEVEL SHIFT
SLED MOTOR
FEED. MOTOR+
M
SAO
DRIVE
BA5918
FEED. MOTOR-
Photo Interrupter
5V
PHO - Vcc
Q502/Q503
PHO - C
Q501
2SC4617(BR)
SLED CLK
IC501
u-COM
17
3-2. Focus Servo for CD/DVD
Focus Servo for CD/DVD is based on focus error signal generated from RF AMP (SSI3723). It standardizes the
laser beam (CD : A, B,C, DVD : A, B,C,D) radiated from the pick-up.
Each other focus gain or path is made at the SSI3723 (IC201) according to the disc, Focus Error signal
output from the FE terminal and input to Servo IC (IC301 CXD3011R).
After the first amplification of this signal, the signal is converted to A/D and input to Digital Equalizer Block
assigned the most important part at the Focus Servo, and generates the focus servo with coefficient value
set at the µ-COM through the Digital Filter.
At this Digital Equalizer, auto adjustment for Focus Balance or Focus Loop Gain occurs and the basic offset
value for pick-up is accepted on the balance mode, and set the focus standard level to this value.
After the signal for Focus Servo is converted to the D/A and output through FAO (IC301 CXD3011R 113 ).
This signal drives Focus Actuator through the Focus Drive IC (IC601:BA5918FP).
3-3. Tracking Servo for CD/DVD
For Tracking Servo, CD uses 3 Beam method (E-F), DVD uses DPD (Differential Phase Detect) method
[Phase (A+C) - Phase (B+D)]
According to the disc, Tracking Error is set at SSI3723, Gain or Path differs from each other, and the
generated signal output through the TE terminal.
This signal input to TE of IC301, after the first amplification, and converted to A/D.
The signal converted to A/D input to the Digital Equalizer assigned the most important part at the Tracking
Servo, Tracking Servo Gain is generated with Digital Filter coefficient value set according to the disc at the
µ-COM.
* Tracking signal is converted to D/A through the pin
(BA5918FP) tracking drive.
This drive drives the tracking actuator actually.
112 TAO terminal of IC301 and input to IC601
3-4. Sled Servo (Feed Servo) for CD/DVD
Sled servo operates related with a tracking servo basically
It goes with the progressive track speed according to the disc rotation speed.
Sled drive voltage is generated with a accumulated capacity of tracking error signal and is applied sled
movement voltage according to the track movement capacity, and this voltage outputs to the pin 111 SAO of
IC301. This value is the sled motor drove by the IC601 (Sled drive : BA5918FP). But, the shift speed
for pick-up is not controlled and broke with a only sled servo, itself, in the data access mode, and the
feedback is used according to the sled shift speed at this time. So, the accurated shift speed for
pick-up is controlled added to the sled signal.
The hall sensor is used in the feedback and SLEDCLK 95 output at the µ-COM (IC501) is used with it
in the sled kick or break.
17
4. Spindle Servo Circuit
4-1. SPINDLE SERVO PROCESS
SPINDLE SERVO PROCESS
IC201
RF AMP
SSI3723
PICK-UP
E
A C
B
F
RF
A, B, 2C
A+B+2C
CD RF
3
D
C
B
A
RF
A, B, C, D
A+B+C+D
DVD RF
4
CD RF
SPINDLE MOTOR
FG
Hall Sensor
Motor
Speed
Monitoring
IC501
u-com
IC301
DVD/CD SERVO &
CD DSP
CXD3011R
CD/
DVD
M
FG
PLL BLOCK
Q601
MDP
DVD RF
IC1
AN8473SA
Motor Drive
PLL BLOCK
U
V
W
LEVEL SHIFT
HU+
HUHV+
HVHW+
HW-
Gain
Ctrl
MDIN2
Spindle
Control
IC601
Drive(Amp)
SPO
IC401
DVD DSP
CXD1867R
4-2. Spindle Servo for CD/DVD
DVD-ROM consists of the three spindle control respectively.
(1) DVD x 8 : CAV (DVD Single, Dual Layer)
(2) CD x 12 (max.) : CAV (CD-DA, CD-RW, Video-CD (6-12 x), Host command stand-by of CD-ROM and
CD-R)
(3) CD x 24 (max.) : CAV (CD-R, CD-ROM play mode)
In the spindle speed control mode respectively.
CD x 12(Max)/CD x 24(Max) CAV drives CAV servo with PLL of RF data read and received MDP.
(Pin 117 of IC301)
DVD x 8 (Max) CAV drives CAV servo with FG signal and received MDP. (Pin 117 of IC301)
19
20
Motor
Drive
Generating
A/B/2C/E/F Signal
Pickup
Unit
CD
IC501
H8/3062
SICLK
SIXLT
SIDAT
SCLK
DATA [0..7]
ADR [0..8]
CD DATA
IC471
Buffer
CD Data Buffering
CD Data ECC
MA [0..8]
MDB [0..F]
Receive the order from Host
2’nd ECC
CD Data Buffering
Command
IC401
CXD1867R
CD-ROM Decoder
Data
and Host Interface
Status
CD Servo Control
CD Data Flow Control
Host Command Receive or Data/Status Transfer˚
CD TE/FE/SLED
Spindle Control
CD RF
IC301
CXD 3011R
CD DSP
IC201
SSI3723 RF
Signal processing IC
SDATA
EFM Demodulation
Error Correction
Generating Header Sync
Generating Subcode Sync
Generating RF Signal
Generating Tracking Error
Generating Focusing Error
DESCRIPTION OF DATA PROCESSING
1. CD Data Processing Flow
Motor
Drive
Generating
A/B/E/F Signal
Pickup
Unit
DVD
Sled Control
Focus Control
Tracking Control
Spindle Control
CXD 3011R
CD DSP
DVD
TE/FE/Sled/
Spindle control
Error Signal
SSI3723 RF
Signal processing IC DVD RF
Generating RF Signal
Generating Tracking Error
Generating Focusing Error
Buffer
DVD Data Buffering
MA [0..8]
MDB [0..F]
Data/
Status
Receive the Command from Host
DVD Data Buffering
Copy Protection Control
Command
DVD Servo Control
DVD Data Flow Control
Host Command Receive or Data/Status transfer
H8/3062
DATA [0..7]
ADR [0..8]
CXD1867R
DVD DSP
EFM Demodulation
EDC + ECC processing
Generating DVD ID Sync
2. DVD Data Processing Flow
21
3. Copy Protection and Regional Code Management Block
Block Diagram
Change the "KEY"
HOST DVD
PLAYER
(MPEG2
DECODER)
CXD 1867R
Scrambled MPEG Data
H8/3062
KEY Management Control
Brief Process
1. Regional Code for DVD Disc
– DVD-ROM drive transfers the regional code of the control data to host by the command of host, the DVD
player of host reads the regional code, and plays title in the case of allowed regional code only.
2. Management of DVD Disc for the scrambled of data
(1) DVD-ROM and DVD player of host generate the “KEY 1” respectively, transfer to opposite part, the
“KEY 2” is received, recognizes the data transfer or not with this value, and generates the bus key
encoded the data.
(2) Encoded “Disc Key” and “Title Key” host is transfer with the bus Key.
(3) DVD player of host reads the key value, and uses the value to restore the scrambled data.
* Refer to the next page for the details.
22
4. About Prevention the DVD-ROM from to be copy
A data is able to encode and record in the disc, if a copyright holder wants to prevent the disc from copying.
In case of a disc enhanced movie of 3 titles......
DISC KEY (2048 Bytes) is used to encode the whole contents in the disc and TITLE
KEY (5 Bytes) is used to encode the title respectively.
So, the data is encoded and stored in a disc through the unknown algorithms
with a disc key and title key. (At this time, the disc key and title key are stored
in a disc.)
…As above, the disc is able to copy when the disc key and title key are
opened.
Then, ROM-DRIVE encodes the disc key and title key and transfers to MPEG2 board.
If you want to play the disc prevented from the copy......
First of all, ROM-DRIVE and MPEG-2 board identify with each other through the procedure as described
below.
AGID
HOST
ROM-DRIVE
Challenge key
MPEG-2
DECODER
encoded disc key, title key
1. Drive and host gives and takes the ID of 2bit. This ID is AGID (Authentication Grant ID).
The various decoder boards are attached to the host, in these, AGID sets the MPEG-2 board and drive.
2. After the AGID is set, MPEG-2 board generates the challenge key (10 Byte) and transfers to drive. The
board and drive generate key 1 (5Byte) with the challenge key respectively. (Of course, the Algorithm
generating the key 1 is not known.)
3. Compare with the generated key 1, if it corresponds each other, the first step of authentication is
completed. This is a course to identify the MPEG-2 board with a drive.
4. The second step of authentication is a course to identify a drive with the MPEG-2 board.
The dirve generates a challenge key and transfers it to the MPEG-2 board. The dirve and MPEG-2 board
generate the key 2 (5Byte) with the challenge key, compare with each other, and if it corresponds and the
secondary step of authentication is completed.
5. As above, the identification is completed.
6. The dirve and MPEG-2 board generate the Bus key with the key 1 and key 2 and own it.
7. Dirve encodes the disc key and title key with this Bus key and transfers to the MPEG-2 board.
8. The MPEG-2 board reads the encoded disc key and title key with the Bus key only.
9. MPEG-2 board lets data read from the drive to decode with the read disc key and title key and makes into
the video signal by decoding.
23
5. About the DVD-ROM Regional Code
Regional code
5
1
GRL
RUS
FIN
CAN
FST
LTU
2
BIR
POI
UKR
MNG
U.S.A
TUR
TKM
CHN
JRN
BHS
CUB
1
FGY
KOR
6
BMG
MIX
AFG
PAK
MMR
PRI. VIR
JPN
2
HKG TWN
MAC
PHL
3
1
MNP
GUM
MDI
PLW
PNG
1
5
2
4
AUS
ZAF
ISO
SWZ
NZL
4
DISC
The disc has
the regional
code of 8 bit.
Example)
The disc
manufactured
in the U.S.A,
has the
number one.
24
ROM - DRIVE
Transfer to
MPEG-2
Decoder
reading the
regional code.
MPEG-2 DECODER
VGA CARD
If the decoder is setting to the
regional decoder 1 for the
U.S.A. ...
Check the received regional
code to number 1, all or not,
transfer the data to VGA card
in accordance with only a case
among the three case.
MONITOR
Receiving
data from the
MPEG-2
decoder and
output
through the
monitor
A
IC601
BA5918FP
B
To CXD-3011R
(IC301)
5V
3.3V
To CXD1867
3.3VA
5VA
IC102
C
8
9
CS
VM22
SPINDLE
MOTOR
VM21
V
R6
0.22(1/4W)
ATAPI
I/F
DMA
I/F
A/V Dec.
I/F
Reset
&
Regulator
Q101
XC62H3302
IC801
BH3525FV
SLED (-)
SYSTEM
CONTROLLER
LED
SLED (+)
2
X501
EJECT
SW1
50MHz
PHO VCC
X301
33.86MHz
1
IC301
CXD-3011R
SLED (+)
SLED (-)
220
SW
VDD
GNC
NC
C6
ECC
Core
R3
IC402(1/2)
NJM
2100
SLED CLK
0.1u
BC2
33.86MHz
A31
A32
CD-ROM
Dec.
3
4
5
6
7
To Motor Drive
IC401/501
VREF1
CXD1867
VC(1.65V)
1
2
1 2 3RF4PLL
5 6 7CD-Audio
8 9 10 11 12 13 14 15 16
EFM/CIRC
DAC
C7
BC1
VPUMP
START
A21
PG2
DVD
Decode
PH-E
PH-C
PH-A
PH-K
GND
EJECT SW
LED
0.1u
C4
CD SERVO/DSP
SLED (-)
EJECT
LED
SLED (+)
SLED CLK
PHO VCC
SW
DRAM
512kB(4M)
M
Sled
Motor
FG
A22
Sync.Det
CN3
Sync. det
360
A11
PG1
0.1u
CLV
Servo
ECR
EC
H1H
A12
NC
EFM
Demod.
E
Tracking &
Focus coil
H1L
H2H
H2L
PWMSW
D1
6.2V
RF PLL
0.1u
SSP
R5
H1
H2
CLV
Servo
C2
100
0
H3H
VM11
VM12
IC401
CXD1867R
DVD SERVO/DSP
K
1
BEAD
H3
H3L
VH
IC1 AN8473SA
SF-HD4SSLG
C
Tracking &
Focus
220
R4
LASER
PICK-UP
A
Loading &
Sled Motor
Drive
Spindle
Motor
R1
R2
IC1
AN8473SA
47u/6.3V
40
39
38
37
CD-VC
36
35
34
P/UP-GND
33 P/UP-GND
32 CD-LD
31 CD-MD
30 CD-C
CD-A
CD-F
P/UP-VCC
P/UP-VCC
CD-VC
P/UP-GND
CN1
CD-B
MOTOR GND
MOTOR GND
MOTOR VCC
MOTOR VCC
EC
ECR
3
2
1
LED (+)
SLED (-)
SLED (+)
8
FG
7 PWR SAVE
6 SLED CLOCK
5
PHO VCC
4 EJECT SW
14
13
12
11
10
9
29
28
To
CD-E
Main
CD-B
Board
DVD-MD
27 DVD-MD
DVD-LD 26 DVD-LD
DVD-C
25 DVD-C
DVD-B
24 DVD-B
DVD-RF 23 DVD-RF
DVD-A
22 DVD-A
DVD-D 21 DVD-D
DVD-VC
20 DVD-VC
T (+)
19
T (+)
F (-)
18
F (-)
F (+)
17
F (+)
T (-)
16
T (-)
15 LEAD IN SW
CD-LD
CD-MD
CD-C
CD-E
CD-F
CD-A
DVD, CD DISK
DVD-LD
DVD-C
DVD-B
DVD-RF
DVD-A
DVD-D
DVD-LD-GND
DVD-VC
DVD-VCC
T (+)
F (-)
F (+)
T (-)
+
Spindle
Motor
Drive
L2
2
C03
VREF
1.35V
TO
P-UP
CD-A
1
CD-F
2
3
4
CD-VC
5
6
CD-LD
7
CD-MD
8
9
CD-C
10
CD-E
11
CD-B
12
13
14
15 DVD-MD
16
17
DVD-LD
18
DVD-C
19
DVD-B
20
DVD-RF
21
DVD-A
22
DVD-D
23
24
DVD-VC
25
26
T(+)
27
F(-)
28
F(+)
29
T(-)
30
+
1
47u/6.3V
3
2
CN2
CD/DVD
RF AMP
EQ.
C3
IC201
SP3723
2200p
4
C5
5
CD-A
CD-F
NC
CD-VCC
CD-VC
CD-GND
CD-LD
CD-MD
NC
CD-C
CD-E
CD-B
CD-VR
DVD-VR
DVD-MD
DVD-HFM
DVD-LD-GND
SPINDLE MOTOR ASSY CIRCUIT
IC471
PN701
H
O
S
T
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
I/F
Authentication
IC501
H/8/3062
X501
20MHz
Audio
Line
Amp
IC101
RS5510H003C
+5V
GND
FROM HOST
ADAPTOR
D
62
MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN
DESCRIPTION
IC201 (SSI3723) : RF Signal Processing for CD/DVD
RFAC
DIP
DIN
Block Diagram
FNN
FNP
AIP
AIN
ATON
ATOP
It amplifies or equalize the RF signal from Pick-up, and generate the TE (Tracking Error) and FE
(Focus Error) signal for Servo respectively.
The TE signal uses the DPD (Differential Phase Detect) method for DVD and 3 Beam method for CD.
DVD FE = (A+C) - (B+D)
CD FE = F - E
2. FCCR b7-0
3. FBCR b6-0
DVDRFP
DVDRFN
PROGRAMMABLE
EQUALIZER
FILTER
DIFFERENTIATOR
AGC
IMPUT
BIAS
ATT
MUX
5. RFCR b3
AGC HOLO
3. FBCR b7
OUTPUT INHIBIT
FULL WAVE
RECTIFIER
RFSIN
4
2
5. RFCR b5-4
INPUT IMP SEL
+ SSOUT
4. SIGR b7-4
ATT
5. RFCR b7-6
2
INPUT IMP
SEL
4. SIGR b3
INPUT SEL
-
2
13. CAR b1-0
w/LPF
A
A
MUX
+
+
GCA
w/LPF
GCA
B
CD_A
B
B+D
+
+
C
RX
13. CAR b3-2
SIGDET
2
C
15. CCR-b4-0
5
SUM
Amp
+
GCA
GCA
D
GCA
+
+
CD_D
GCA
GCA
5
PII
6. FOCR b3-0
10. PIOR b4-0
70kHz
+
+
FE
4
Offset
cancel
LPF
PI
TOPHOLD
TPH
9. CTCR b7
BCA DET
COMP
+
2
A+D
CD_C
Offset
cansel
LPF
4
6. FOCR b7-4
+
+
+/- 6dB, 4bit
70kHz
+/- 4dB
w/LPF
GCA
4. SIGR b2-0
12dB is added
@high gain mode
(16. CDR b4=1)
GCA
CD_B
+
-
Level
DAC
GCA
D
BYP
AGCO
Clamp
& Env
Inv.
A+C
w/LPF
AGC
CHARGE
PUMP
17. CER b6
FAST Attack
17. CER b5
SLOW decay
14. CBR b3-2
+
+
B+C
TOPHOLD
Buff
TOPHOLD
4. SIGR b2-0
+
Offset
cancel
6dB
Amp
RFDC
4
CE
GCA
+/- 6dB, 4bit
PI
FE
TE
CE
V25
V125
V25/3
12dB is added
@high gain mode
(16. CDR b4=1)
6dB is added
@high gain mode
(16. CDR b4=1)
9. CTCR b3-0
5
17. CER b4-0
1. PDCR b3
CD/DVD
MNTR
Control
MNTR
3
10. PIOR b7-5
GCA
CD_E
+/- 4dB
CD_F
GCA
GCA
3
4
5. RFCR b2-0
+3dB
18. CFR b2-0
CE-ATT
+
18. CFR b3
CEPOL
LCP
3
LPF
ATT
Pol sel.
Buff (-12dB)
LCN
14. CBR b5-4
2
SEL
16. CDR b5
HLDEN
8. TRCR2 b3-0
12dB is added
@high gain mode
(16. CDR b4=1)
CP
CN
Comp
A2
GCA
EQ
B2
GCA
EQ
C2
GCA
EQ
D2
GCA
EQ
PHASE
DETECTOR
SUB
MUX
+
+
1. PDCR b3
CD/DVD
PHASE
DETECTOR
OFFSET
Cancel
LPF
TE
RST
GCA
TE
for TE, FE & CE
3
6
output ref.
18. CFR b7-5
16. CDR b1
8. TRCR2 b7 18. CFR b4 7. TRCR b5-0
CEFDB
CP/CN
for PI output ref.
Low Imp
V25/2
VC
V25/3
5. RFCR b2-0
8. TRCR2 b6-4
7. TRCR b7
7. TRCR b6
VCI for servo input
VC
VC=VPB/2
12. MRCR2 b4 MIR ONLVL
15. CCR b7 DISK DET
16. CDR b3
LD H/L
V125
V25
3
3
DFT
2
14. CBR b1-0
-6dB @normal
3
SEL
DAC
15. CCR b5
APC SEL
DVD/CD
12. MRCR2 b3-2
Sink current
2
DVD/PD
Dual APC
AGCO
CDPD
BOTTOM
ENVELOPE
CONTROL
12. MRCR2 b1-0
15. CCR b6 Disk Det High Gain Signals
Mirr gain
To each block
@CCR b7 Disk Det=1
16. CDR b7
11. MRCR b7-5
Mirro Clamp ON
12. MRCR2 b7
11. MRCR b1-0
Comp offset & hys
11. MRCR b3-2
Input Imp
Mirr LPF
Pll
2
MIRR
2
COMP
PEAK/
BOTTOM
HOLD
15. CCR b7
DISK DET
MUX
SDEN
SERIAL PORT
REGISTER
SDATA
SCLK
V33
V33 for Output buff
INPUT
BUFF
12. MRCR2 b6-5
2
16. CDR b2
16. CDR b6
LINKEN
11. MRCR b4
internal FDCHG
VNB
VNA
VPB
VPA
MIRR
LINK
MB
MP
MLPF
MIN
MEVO
MEV
DVDLD
CDLD
LDON
25
IC201 (SSI3723)
•
Pin Description
POWER SUPPLY PINS
Pin No.
Name
Type
Description
58
VPA
–
Power supply pin for the RF block and serial port
19
VPB
–
Power supply pin for the servo block
51
VNA
–
Ground pin for the RF block and serial port
25
VNB
–
Ground pin for the servo block
45
V33
–
Power supply pin for the output buffers
36
V25
–
Reference power supply for the servo output
INPUT PINS
Pin No.
1,2
Name
DVDRFP,DVDRFN
Type
Description
I
RF SIGNAL INPUTS: Differential RF signal attenuator input pins.
63
RFSIN
I
RF SIGNAL INPUT: Single-ended RF signal attenuator input pin.
59,60
AIP, AIN
I
AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.
54,55
DIP, DIN
I
9, 10, 11, 12
A, B, C, D
I
3, 4, 5, 6
A2, B2, C2, D2
I
13, 14, 15, 16 CD_A, B, C, D
I
ANALOG INPUTS FOR RF SINGLE BUFFER: Differential analog inputs to the
RF single-end output buffer and full wave rectifier.
PHOTO DETECTOR INTERFACE INPUTS: Inputs from the main beam Photo
detector matrix outputs.
PHOTO DETECTOR INTERFACE INPUTS: AC coupled inputs for the DPD
from the main beam Photo detector matrix outputs.
CD PHOTO DETECTOR INTERFACE INPUTS : CD_A, B, C, D come from
the CD main beam Photo detector matrix outputs.
CD PHOTO DETECTOR INTERFACE INPUTS: CD side beam photo dector
17, 18
CD_E, F
I
31
MIN
I
23
DVDPD
I
APC INPUT: DVD APC input pin from the monitor photo diode.
24
CDPD
I
APC INPUT: CD APC input pin from the monitor photo diode.
26
LDON
I
33
LINK
I
outputs and used for the CD tracking detection.
RF SIGNAL INPUT FOR MIRROR: AC coupled inputs for the mirror detection
circuit from MEVO.
APC OUTPUT ON/OFF: APC output control pin. A high level activates LD
output. (open low)
LINKING SIGNAL INPUT PIN: In the linking area. This pin goes high and the
26
Mirror and TE outputs are disabled. When the link signal is enabled. (open low)
OUTPUT PINS
Pin No.
Name
Type
61,62
ATOP/ATON
O
DIFFERENTIAL ATTENUATOR OUTPUTS: Attenuator outputs.
52,53
FNP, FNN
O
DIFFERENTIAL NORMAL OUTPUTS: Filter normal outputs.
57
RFAC(SIGO)
O
SINGLE-ENDED NORMAL OUTPUT: Single-ended RF output.
64
RFDC
O
RF SIGNAL OUTPUT: Single-ended RF summing output reference to VPB-2.4(V).
40
FE
O
FOCUSING ERROR SIGNAL OUTPUT: Focus error output reference to V125.
39
TE
O
TRACKING ERROR SIGNAL OUTPUT: Tracking error output reference to V125.
41
CE
O
CENTER ERROR SIGNAL OUTPUT: Center error output reference to V125.
32
MEVO
O
RFDDC BOTTOM ENVELOPE OUTPUT: Bottom envelope, PI or bottom
clamped RF envelope signal output for Mirror detection.
Description
34
DFT
O
DEFECT OUTPUT: CMOS output (V33 or VPB). When the PI signal level is
below the detection level or when the Rf signal level is below the detection level,
the DFT output goes high. This output is selected by serial port.
27
MIRR
O
MIRROR DETECT OUTPUT: Mirror detect comparator output. CMOS
output(V33 or VPB).
38
PI
O
PULL-IN SIGNAL OUTPUT: The summing signal output of A, B, C, D or CD_A,
B, C, D. Reference to V25/3.
21
DVDLD
O
APC OUTPUT: DVD APC output pin to control the laser power.
22
CDLD
O
APC OUTPUT: CD APC output pin to control the laser power.
42
MNTR
O
MONITOR OUTPUT: Monitor Output signal is selected by PIOR bit7-5
ANALOG PINS
Pin No.
Name
Type
56
BYP
–
The RF AGC integration capacitor CBYP. is connected between BYP and VPA.
7
CP
–
DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is
connected between CN.
8
CN
–
DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is
connected between CP.
44
LCP
–
LENS SHIFT OFFSET CANCEL LPF PIN: The external capacitance is connected
between LCN.
43
LCN
–
LENS SHIFT OFFSET CANCEL LPF PIN: The external capacitance is connected
between LCP.
28
MP
–
MIRR TOP HOLD PIN: The external capacitance is connected to VPB.
29
MB
–
MIRR BOTTOM HOLD PIN: The external capacitance is connected to VPB.
50
MEV
–
RFDC BOTTOM ENVELOPE PIN: The external capacitance is connected to VPA.
30
MLPF
–
MIRROR LPF PIN: An external capacitance is connected to VPB.
35
TPH
–
PI TOP HOLD PIN: An external capacitance is connected to VPB.
20
VC
–
REFERENCE VOLTAGE OUTPUT: This pin provides the DC bias reference
Voltage (VPB/2). Output impedance is less than 50Ω.
37
V125
–
REFERENCE VOLTAGE OUTPUT: DC bias voltage output and it is also used for
servo output reference. (V25/2)
49
RX
–
REFERENCE RESISTOR INPUT: An external 12.0kΩ, 1% resistor is connected
from this pin to ground to establish a precise PTAT (proportional to absolute
temperature) reference current for the filter.
Description
27
SERIAL PORT PINS
28
Description
Pin No.
Name
Type
48
SDEN
I
SERIAL DATA ENABLE: Serial enable CMOS input. A high level input
enables the serial port. (not to be left open)
47
SDATA
I/O
SERIAL DATA: Serial data bidirectional CMOS pin(V33). NRZ programming
data for the internal registers is applied to this input. (not to be left open)
46
SCLK
I
SERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is
synchronized with the data applied to SDATA. (not to be left open)
IC501 (H8/3062) : µ-COM
It Controls the total system giving or taking the data from the peripheral ICS.
•
Pin Description
Pin
H8/3062
DRD-8080B
No.
pin name
pin name
Description
I/O
1
Vcc
VCC1
5V
I
2
PB-0
RCLK
SP3723 control clock
O
3
PB-1
LDON
APC output On/Off to SP3723
O
4
PB-2
XCS
Chip select to CXD1867
I
5
PB-3
DSPMUTE
Mute signal to CXD3011R
O
6
PB-4
CD/DVD
Spindle drive Gain Change
O
7
PB-5
PWRCTL_3V
3.3V Control(IC102)
O
8
PB-6
XRST
Reset out to CXD3011R, 1867R
O
9
PB-7
LED
Access LED
O
10 FWE
FWE
Flash memory writing enable input from Q201 emitter
I
11 Vss
VSS1
GND
I
12 P9-0
SIDATA
Serial Data signal to CXD3011R
O
13 P9-1
SCLK/TXD
Serial data signal to CXD3011R
O
14 P9-2
XILAT
Serial data latch output
O
15 P9-3
SQCK/RXD
Sub Q serial clock to CXD3011R
O
16 P9-4
SICLK
Serial clock signal to CXD3011R
O
17 P9-5
FOK input signal from CXD3011R
O
18 P4-0
NFOK
_
NC
O
19 P4-1
_
NC
O
20 P4-2
CD_H
_
“H” output at CD Mode
O
NC
O
GND
I
23 P4-4
VSS2
_
NC
O
24 P4-5
AUDMUTE
Audio Mute Control
O
25 P4-6
PWRCTL_5V
5V Control (Q101, Q102)
O
26 P4-7
FWEON
Flash memory writing enable output to Q201 base
O
27 D8
D0
Data bus to CXD1867R
I/O
28 D9
D1
I/O
29 D10
D2
I/O
30 D11
D3
I/O
31 D12
D4
I/O
32 D13
D5
I/O
33 D14
D6
I/O
34 D15
D7
I/O
35 Vcc
VCC2
5V
I
36 P1-0
A0
Address bus to CXD1867R
O
37 P1-1
A1
O
38 P1-2
A2
O
21 P4-3
22 Vss
29
Pin
No.
H8/3062
DRD-8080B
pin name
pin name
Description
I/O
39 P1-3
A3
O
40 P1-4
A4
O
41 P1-5
A5
O
42 P1-6
A6
O
43 P1-7
A7
O
44 VSS
VSS3
GND
I
45 P2-0
A8
O
46 P2-1
CGFS
CD GFS signal from CXD3011R
I
47 P2-2
MAnSL
IDE jumper input (H:Slave, L:Master)
I
48 P2-3
SENS
SENS input signal from CXD3011R
I
49 P2-4
DGFS
DGFS input signal from CXD1867R
I
50 P2-5
SQSO
sub Q data from CXD3011R
I
51 P2-6

NC
52 P2-7
LOADIN
Tray closed S/W input
53 P5-0

NC
54 P5-1

NC
55 P5-2

NC
56 P5-3

NC
57 Vss
VSS4
GND
I
58 P6-0
XWAIT
Wait signal to CXD1867R
O
59 P6-1
RDE
SP3723 enable data
O
60 P6-2
RDATA
SP3723 control data
O
61 P6-7

NC
O
62 /STBY
/STBY
Hardware standby mode transition input
I
63 /RES
/RES(RESET)
Reset input from reset part
I
64 NMI
LOADIN
Tray closed S/W input.
65 Vss
VSS5
GND
I
66 EXTAL
EXTAL
Connect to X-TAL (20MHz)
I
67 XTAL
XTAL
Connect to X-TAL (20MHz)
I
68 Vcc
VCC3
5V
I
69 /AS

NC
70 /RD
XRD
Read signal to CXD1867R
O
71 /HWR
XWR
Write signal to CXD1867R
O
72 /LWR

NC
73 MD0
MD0
Operating mode control 0
I
74 MD1
MD1
I
75 MD2
MD2
I
76 Avcc
AVCC
5V
I
77 Vref
VREF
Referance voltage for A/D, D/A converters
I
78 P7-0
FE
Focus error A/D analog input from SP3723
I
79 P7-1

NC
I
80 P7-2

NC
I
81 P7-3
LOADKEY
Load key input from SW1(Lead in SW)
I
30
I
I
Pin
H8/3062
DRD-8080B
No.
pin name
pin name
Description
I/O
82 P7-4
APEO
Absolute phase error signal from CXD1867R
I
83 P7-5

NC
I
84 P7-6
TESTMD
MD test signal input
I
85 P7-7

NC
O
86 Avss
AVSS
GND
I
87 P8-0
XINT0
Int0 request from CXD1867R
I
88 P8-1
XINT1
Int1 request from CXD1867R
I
89 P8-2
EJECT-SW
Eject key input.
I
90 P8-3
SCOR
Sub code sync input signal from CXD1867R & CXD3011R
I
91 P8-4

NC
92 Vss
VSS6
GND
I
93 PA-0
COUT
COUT from CXD3011R
I
94 PA-1
PWRCTL-PHO
PHO Vcc control output (Q502)
O
95 PA-2
SLEDCLK
Sled motor rotation senser clock input
I
96 PA-3
FG0
Spindle motor rotation sensor clock input
I
97 PA-4
FG1
Spindle motor rotation sensor clock input
I
98 PA-5
MIRR
MIRR input from SP3723
I
99 PA-6
BCARF
BCARF input from SP3723
I
100 PA-7
DRVMU1
Actuator driveIC(IC601) & Spindle driveIC(IC1) Mute control.
O
31
IC401 (CXD1867R) : LSI processing for DVD-ROM Drive Signal
XRAS
XMOE
MA9/mnt0
MA10/mnt1
MA11/mnt2
91 92
93
RFDCC
116
RFIN
117
PDO
130
RF
Asymmetry
MDB[F:0]
XCAS
94
MA[8:0]
XMWR
95 78
ASF2
76
ASF1
111 113 114 115
DASYO
DASYI
Block Diagram
79, 80,
82~87, 89
66~69, 71, 73~75, 96, 97, 99,
101, 102, 104~106
DMA Controller
(Priority resolve & Sequencer)
23 XHRS
124
VCOR1
120
VCOIN
121
MDPOUT
144
MDSOUT
142
CLVS
140
MDIN1
138
MDIN2
137
SPO
135
VC2
136
GFS
107
APEO
109
GSCOR
MDAT
LRCK
163
C2PO
155
WFCK
151
SCOR
150
SBIN
148
EXCK
147
XRCI
153
DDAT
159
DLRC
162
DBCK
157
24, 26, 27,
29~32, 34,
35, 37,
HDB[F:0]
39~41,
43~45
ATAPI
or
DMA
or
Video
Sector ID
Detect
Spindle
Control
65 DASP
CD-ROM
Main Data
ECC & EDC
53 XHAC
ATAPI
Registers
56, 59, 60
48 XHWR
Descramble
160
158
HOST
I/F
VCO
146
BCLK
32
EFM+
Demodulator
49 XHRD
ATAPI
Packet
FIFO
Subcode
Deinterleave & ECC
63 HCS1
62 HCS0
164 XRST
CDDSP
I/F
SYNC Control
Internal Clock
169 XTL2
CD ESP
170 XTL1
Authentication
CPU I/F, DMA Controller
DAC
I/F
167
18
17
1, 2, 4, 172~176
5, 7, 9~14
19
20
21
16
XWAIT
LPF5
XINT1
125
46 HDRQ
SYNC Detect
XINT0
VC1
54 HINT
DMA
FIFO
XCS
126
55 XS16
A[7:0]
16
127
LPF2
51 REDY
D[7:0]
LPF1
PLL
XRD
132
XWR
131
FDO
XTAL
PDHVCC
57 XPDI
DVD
Main Data
ECC & EDC
HA[2:0]
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
I/O
D5
D6
Vss*
D7
A0
VDD*
A1
VDD5V*
A2
A3
A4
A5
A6
A7
Vss*
XWAIT
XRD
XWR
XCS
XINT0
XINT1
VDD*
XHRS
HDB7
Vss*
HDB8
HDB6
VDDS*
HDB9
HDB5
HDBA
HDB4
Vss*
HDBB
HDB3
VDD*
HDBC
VDDS*
HDB2
HDBD
HDB1
Vss*
HDBE
HDB0
HDBF
HDRQ
VDDS*
XHWR
XHRD
VDD*
I/O
I/O

I/O
I

I

I
I
I
I
I
I

I/O
I
I
I
O
I/O

I
I/O

I/O
I/O

I/O
I/O
I/O
I/O

I/O
I/O

I/O

I/O
I/O
I/O

I/O
I/O
I/O
O

I/O
I/O

INPUT
[V]
3.3
3.3
DGND
3.3
3.3
3.3
3.3
5.0
3.3
3.3
3.3
3.3
3.3
3.3
DGND
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5.0
5.0
DGND
5.0
5.0
5.0
5.0
5.0
5.0
5.0
DGND
5.0
5.0
3.3
5.0
5.0
5.0
5.0
5.0
DGND
5.0
5.0
5.0
5.0
5.0
5.0
5.0
3.3
OUTPUT
Current
-4mA/4mA
-4mA/4mA

-4mA/4mA











-4mA/4mA



-8mA/8mA
-8mA/8mA


-4mA/12mA

-4mA/12mA
-4mA/12mA

-4mA/12mA
-4mA/12mA
-4mA/12mA
-4mA/12mA

-4mA/12mA
-4mA/12mA

-4mA/12mA

-4mA/12mA
-4mA/12mA
-4mA/12mA

-4mA/12mA
-4mA/12mA
-4mA/12mA
-4mA/12mA

-4mA/12mA
-4mA/12mA

I/O buffer
5V tolerant
5V tolerant

5V tolerant
5V tolerant

5V tolerant

5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant

5V tolerant
5V tolerant
5V tolerant
5V tolerant

5V tolerant

ATAPI
ATAPI

ATAPI
ATAPI

ATAPI
ATAPI
ATAPI
ATAPI

ATAPI
ATAPI

ATAPI

ATAPI
ATAPI
ATAPI
Comment
PULL UP
ATAPI
ATAPI
ATAPI
ATAPI

ATAPI
ATAPI

33
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
34
Name
I/O
REDY
Vss*
XHAC
HINT
XS16
HA1
XPD1
VDDS*
HA0
HA2
Vss*
HCS0
HCS1
VDD*
DASP
MDB0
MDB1
MDB2
MDB3
Vss*
MDB4
VDD5V*
MDB5
MDB6
MDB7
XMWR
VDD*
XRAS
MA0
MA1
Vss*
MA2
MA3
MA4
MA5
MA6
MA7
VDD*
MA8
Vss*
MA9/mnt0
MA10/mnt1
MA11/mnt2
XMOE
XCAS
MDB8
MDB9
Vss*
MDBA
VDD*
MDBB
O

I
I/O
O
I
I/O

I
I

I
I

I/O
I/O
I/O
I/O
I/O

I/O

I/O
I/O
I/O
I/O

I/O
O
O

O
O
O
O
O
O

O

O
I/O
I/O
O
O
I/O
I/O

I/O

I/O
INPUT
[V]
5.0
DGND
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
DGND
5.0
5.0
3.3
5.0
3.3
3.3
3.3
3.3
DGND
3.3
5.0
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
DGND
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
DGND
3.3
3.3
3.3
3.3
3.3
3.3
3.3
DGND
3.3
3.3
3.3
OUTPUT
Current
-4mA/12mA


-4mA/12mA
-4mA/12mA

-4mA/12mA







-4mA/12mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA

-4mA/4mA

-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA

-4mA/4mA
-4mA/4mA
-4mA/4mA

-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA

-4mA/4mA

-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA

-4mA/4mA

-4mA/4mA
I/O buffer
ATAPI

ATAPI
ATAPI
ATAPI
ATAPI
ATAPI

ATAPI
ATAPI

ATAPI
ATAPI

ATAPI
5V tolerant
5V tolerant
5V tolerant
5V tolerant

5V tolerant

5V tolerant
5V tolerant
5V tolerant
5V tolerant

5V tolerant













5V tolerant
5V tolerant


5V tolerant
5V tolerant

5V tolerant

5V tolerant
Comment
PULL UP
PULL UP
PULL UP
Pin No.
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Name
I/O
MDBC
VDD5V*
MDBD
MDBE
MDBF
GFS
Vss*
APE0
VDD*
DASYO
GNDA5*
ASF1
ASF2
DASY1
RFDCC
RFIN
VccA5*
VccA4*
VCOR1
VCOIN
GNDA4*
GNDA3*
LPF5
VC1
LPF2
LPF1
VccA3*
VccA2*
PDO
PDHVCC
FDO
GNDA2*
GNDA1*
SPO
VC2
MDIN2
MDIN1
VccA1*
CLVS
Vss*
MDSOUT
VDD*
MDPOUT
DFCT/LINK
GSCOR
EXCK
SBIN
Vss*
SCOR
WFCK
VDD5V*
I/O

I/O
I/O
I/O
I/O

O

O




























I/O

I/O

I/O
I/O
I/O
O
I

I
I

INPUT
[V]
3.3
5.0
3.3
3.3
3.3
3.3
DGND
3.3
3.3
3.3
AGND
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
AGND
AGND
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
AGND
AGND
3.3
3.3
3.3
3.3
3.3
3.3
DGND
3.3
3.3
3.3
5.0
5.0
5.0
5.0
DGND
5.0
5.0
5.0
OUTPUT
Current
-4mA/4mA

-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA

-8mA/8mA

-8mA/8mA




























-4mA/4mA

-4mA/4mA

-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA





I/O buffer
5V tolerant

5V tolerant
5V tolerant
5V tolerant

































5V tolerant

5V tolerant

5V tolerant
5V tolerant
5V tolerant

5V tolerant

5V tolerant
5V tolerant

Comment
Hystelesis type
Hystelesis type
Hystelesis type
Hystelesis type
Hystelesis type

35
Pin No.
Name
I/O
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
XRC1
VDDS*
C2PO
VDD*
DBCK
BCLK
DDAT
MDAT
Vss*
DLRC
LRCK
XRST
IFS0
IFS1
XTAL
Vss*
XTL2
XTL1
VDD*
D0
D1
D2
D3
D4
I

I

O
I
O
I/O

O
I
I
I
I
I

O
I

I/O
I/O
I/O
I/O
I/O
36
INPUT
[V]
5.0
5.0
5.0
3.3
5.0
5.0
5.0
5.0
DGND
5.0
5.0
5.0
3.3
3.3
5.0
DGND
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
OUTPUT
Current




-4mA/4mA

-4mA/4mA
-4mA/4mA

-4mA/4mA









-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
-4mA/4mA
I/O buffer
Comment
5V tolerant

5V tolerant


5V tolerant

5V tolerant

Hystelesis type
5V tolerant








5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Hystelesis type
Hystelesis type
Hystelesis type
Hystelesis type
Hystelesis type
IC1 (AN8473SA) : Spindle Motor Drive IC
Block Diagram
VDD
VDD
BC2 BC1
16
START
14
10
H1L
H2H
H2L
H3H
H3L
VH
Spindle Speed
EC
Control INPUT
ECR
Heat
Protection
OSC
FG
H1H
12
Voltage
Boost
Start/Stop
11
VPUMP
13
7
Amp
6
Hall
Amp
Matrix
5
4
Drive
Output
Circuit
Divide
Circuit
Amp
2
PWMOUTL
Hall
Bias
Absolute
Value
9
18
VM22
32
VM11
31
VM12
27
A11
28
A12
24
A21
25
A22
21
A31
22
A32
23
PG2
MOTOR
26 PG1
FF
8
VM21
PWMOUTU
3
1
17
X5
19
CS
SRESET
Vt
PWMSW
30
•
PWM Freq.
Change
Vc1
15
SSET
GND
Pin Description
Description
Pin No.
Pin Name
Pin No.
Pin Name
Description
1
VH
Hall bias
17
VM21
Motor Vcc-2
2
H3L
Hall3 input, negative
18
VM22
Motor Vcc-2
3
H3H
Hall3 input, positive
19
CS
Current sensing pin
4
H2L
20
NC
NC
5
H2H
21
A31
Drive output3
6
H1L
22
A32
Drive output3
7
H1H
23
PG2
Power Current sensing pin2
8
EC
Torque control input
24
A21
Drive output2
9
ECR
Torque control VREF
25
A22
Drive output2
10
FG
FG output
26
PG1
Power Current sensing pin1
Start/Stop control
27
A11
Drive output1
Boostor Pin
11
Start
12
VPUMP
28
A12
Drive output1
13
BC1
Boostor C connection
29
NC
NC
14
BC2
Boostor C connection
30
PWMSW
15
GND
GND
31
VM12
Motor Vcc-1
16
VDD
Power supply, 5V
32
VM11
Motor Vcc-1
Change PWM Freq.
37
• IC601 (BA5918FP) : Focus/Tracking/SLED Control Drive IC
Block Diagram
22
21
20
19
18
17
16
10K
10K
10K
10K
+
10K
10K
LEVEL
SHIFT
LEVEL
SHIFT
+
-
LEVEL
SHIFT
LEVEL
SHIFT
10K
10K
10K
Vcc
+
-
STBY
10K
+
10K
10K
10K
3
4
5
6
7
8
9
10
11
10K
+
+
-
2
10K
10K
+
1
14
10K 10K
10K
10K
15
+
-
+
+
-
Vcc
+
-
23
10K
12
+
-
24
+
25
10K
13
Pin Description
Pin No. Pin Name
Function
Functio
Pin No.
Pin Name
Vcc
14
V04(+)
Driver CH4 noninverted output
Bias amplifier input
15
V04(-)
Driver CH4 inverted output
1
VCC
2
BIAS.IN
3
VIN1
Driver CH1 input
16
V03(+)
4
VIN2
Driver CH2 input, gain adjustment pin
17
V03(-)
5
VIN2
Driver CH2 input
18
Vcc
Vcc
6
GND
Substrate Ground
19
GND
Substrate Ground
7
GND
Substrate Ground
20
0P IN (+)
0p-amp input, positive
8
STBY
Input for stand-by control
21
0P IN (-)
0p-amp input, negative
9
Vcc
Vcc
22
0P OUT
0p-amp output
10
V02(-)
23
VIN3
Driver CH3 input
11
V02(+)
24
VIN3
Driver CH3 input,gain adjustment pin
12
V01(-)
13
V02(+)
25
VIN4
Driver CH4 input
* Symbol of + and - (output of DRIVERS) means polarity to input pin.
(For example if voltage of pin 3 is high, pin 13 is high.)
38
IC301 (CXD3011R) : DSP
The CXD3011R is a Digital Signal Processor(DSP) LSI for CD players.
This LSI incorporates a Digital Servo, Digital Filter and 1-Bit DAC.
XTLO
XTLI
VPCO1
VPCO2
XTSL
PCMDI
BCKI
LRCKI
DTSO
XWO
RMUTO
LMUTO
Block Diagram
83
84 5
6 51
30 32 28
122 74 75 76
* : Asymmetry
Correction
DAC BLOCK
EXCK
SBSO
SQCK
SQSO
MDP
MDS
MON
FSW
Clock
Generator
135
57
32K RAM
79
PWMLP
PWMLN
PWMRP
PWMRN
25
PSSL
82
8Fs Digital Filter
+
1 bit DAC
136
88
80
58
59
OSC
Address
generator
Digital PLL
Vari-Pitch
double
speed
132
131
10
9
EFM
Demodulator
8
8
11
13
15
16
*
D/A
Sync
protector
MUX
DA16(48PCM)
DA15(48BCK)
33 DA14(64PCM)
34 DA13(64BCK)
35 DA12(64LRCK)
38~42, DA11~DA01
44~49
29
Priority
encoder
31
Serial/parallel
processor
7
134
Register
MCKO
V16M
VCKI
FSTIO
C4M
C16M
VCTL
PDO
VCOI
VCOO
PCO
FILI
FILO
CLTV
RFAC
ASYI
ASYO
ASYE
WFCK
SCOR
52
data
processor
24
Timing
Generator1
64
65
66
68
Subcode Q
processor
117
Selector
69
118
116
Error Rate
Counter
Digital Out
CLV
62
DOUT
MD2
61
99
DATA
CLOK
XLAT
95
SENS
102
COUT
MIRR
DFCT
FOK
98
Timing
Generator2
processor
MUTE
Peak
detector
Error
corrector
Subcode
P~W
processor
67
65
CPU
100
interface
CAV
processor
107
Noise
Shaper
PWMI
129
TEST
TEST2
TEST3
XRST
133
Servo
auto
18~times
oversampling
filter
sequencer
SIGNAL PROCESSOR BLOCK
123
124
Servo
Interface
71
SERVO BLOCK
ADIO
140
RFDC
CE
TE
SE
FE
VC
141
142
143
MIRR
DFCT
FOK
OpAmp
A/D
AnaSw CONVERTER
2
3
103
104
105
SERVO DSP
FOCUS SERVO
TRACKINGSERVO
SLED SERVO
DAC
OpAmp
113
FOCUS
TRACKING
SLED
112
111
FAO
TAO
SAO
22 43 60 94 130 17 137 93 81 82 115
23 50 77 101 121 12 139 86 78 85 110
114
DVDD1
DVDD2
DVDD3
DVDD4
DVDD5
AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
AVDD6
DV SS1
DV SS2
DV SS3
DV SS4
DV SS5
AV SS1
AV SS2
AV SS3
AV SS4
AV SS5
AV SS6
BSSD
4
39
IC301 CXD3011R
•
Pin Description
Pin No.
40
Symbol
I/O
Description
2
SE
I
Sled error signal input.
3
FE
I
Focus error signal input.
4
VC
I
Center voltage input.
5
VPCO1
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output.
6
VPCO2
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E
command FCSW.
7
VCTL
I
8
FILO
O
9
FILI
I
10
PCO
O
11
CLTV
I
12
AVss1
13
RFAC
I
EFM signal input.
14
BIAS
I
Asymmetry circuit constant current input.
15
ASYI
I
Asymmetry comparator voltage input.
16
ASYO
O
17
AVDD1
Analog power supply.
22
DVDD1
Digital power supply.
23
DVss1
Digital GND.
24
ASYE
I
Asymmetry circuit on/off (low = off, high = on).
25
PSSL
I
Audio data output mode switching input (low: serial, high: parallel).
26
WDCK
O
1, 0
D/A interface for 48-bit slot. Word clock f = 2Fs.
27
LRCK
O
1,0
D/A interface for 48-bit slot. LR clock f =Fs.
28
LRCK1
I
29
DA16
O
30
PCMDI
I
31
DA15
O
32
BCK1
I
33
DA14
O
1, 0
DA14 output when PSSL = 1, 64-bit slot serial data output (two’ complement,
LSB first) when PSSL = 0.
34
DA13
O
1,0
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
35
DA12
O
1, 0
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
38
DA11
O
1, 0
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
39
DA10
O
1, 0
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
40
DA09
O
1, 0
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
41
DA08
O
1, 0
DA08 output when PSSL = 1, GFS output when PSSL = 0.
42
DA07
O
1, 0
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
Wide-band EFM PLL VCO2 control voltage input.
Analog
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
1, Z, 0
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
1, 0
EFM full-swing output (low = Vss, high = VDD)
LR clock input to DAC (48-bit slot).
1, 0
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two’s complement,
MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
1, 0
DA15 output when PSSL = 1, 48-bit slot bit clock output whe PSSL = 0.
Bit clock input to DAC (48-bit slot).
Pin No.
Symbol
I/O
Description
43
DVDD2
44
DV06
O
1, 0
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
45
DA05
O
1, 0
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
46
DA04
O
1, 0
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
47
DA03
O
1, 0
48
DA02
O
1, 0
49
DA01
O
1, 0
50
DVss2
51
XTSL
I
52
MCKO
O
1, 0
Clock output. Inverted output of XTLI.
57
FSTIO
I/O
1, 0
Digital servo clock input/output.
(2/3 frequency division for XTLI pin is internally connected.)
58
C4M
O
1, 0
1/4 frequency division output for XTLI pin. Changes with variable pitch.
59
C16M
O
1, 0
16.9344MHz output. Changes simultaneously with variable pitch.
60
DVDD3
61
MD2
I
62
DOUT
O
63
MUTE
I
64
WFCK
O
1, 0
WFCK (Write Frame Clock) output.
65
SCOR
O
1, 0
Outputs a high signal when either suvcode sync S0 or S1 is detected.
66
SBSO
O
1, 0
Sub P to W serial output.
67
EXCK
I
68
SQSO
O
69
SQCK
I
SQSO readout clock input.
70
SCSY
I
GRSCOR resynchronization input. Normally low, resynchronization is executed
when high.
71
XRST
I
System reset. Reset when low.
74
XWO
I
Audio DAC sync window open input. Normally high, window open when low.
75
RMUTO
O
1, 0
Audio DAC right channel zero detection flag.
76
LMUTO
O
1, 0
Audio DAC left channel zero detection flag.
77
DVss3
Digital GND.
78
AVss4
Analog GND.
79
PWMRN O
1, Z, 0
Audio DAC PWM output. Right channel, reversed pahse.
80
PWMRP
1, Z, 0
Audio DAC PWM output. Right channel, forward phase.
81
AVDD4
82
AVDD5
Master clock power supply.
83
XTLO
O
84
XTLI
I
85
AVss5
Digital GND.
Crystal selection input.
O
Digital Out on/off control (low = off, high = on).
1, 0
Digital Out output.
Mute (low:off, high:on).
SBSO readout clock input.
1, 0
1, 0
Sub-Q 80-bit, PCM peak and level data 16-bit outputs.
Master clock crystal oscillation circuit output.
Master clock crystal oscillation circuit input.
Master clock GND.
41
Pin No.
42
Symbol
I/O
Description
86
AVss3
Analog GND.
87
PWMLP
O
1, Z, 0
Audio DAC PWM output. Left channel, forward phase.
88
PWMLN
O
1, Z, 0
Audio DAC PWM output. Left channel, reverse phase.
93
AVDD3
94
DVDD4
95
SENS
O
96
SCLK
I
SENS serial data readout clock input. Set to high when not used.
97
ATSK
I
Anti-shock pin. Set to low when not used.
98
DATA
I
Serial data input from CPU.
99
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
100
CLOK
I
Serial data transfer clock input from CPU.
101
DVss4
102
COUT
I/O
1, 0
Track count signal I/O.
103
MIRR
I/O
1, 0
Mirror signal I/O.
104
DFCT
I/O
1, 0
Defect signal I/O.
105
FOK
I/O
1, 0
Focus OK signal I/O.
106
TESO
O
107
FSW
O
110
AVss6
111
SAO
O
Sled filter DAC anlog output.
112
TAO
O
Tracking filter DAC analog output.
113
FAO
O
Focus filter DAC analog output.
114
BSSD
I
Constant current input for servo filter DAC anlog output.
115
AVDD6
116
MON
O
1, 0
Spindle motor on/off control output.
117
MDP
O
1, Z, 0
Spindle motor servo control output.
118
MDS
O
1, Z, 0
Spindle motor servo control output.
119
LOCK
I/O
1, 0
120
SSTP
I
121
DVss5
122
DTS0
I
Test pin. Normally fixed to low.
123
TES2
I
124
TES3
I
129
PWMI
I
Spindle motor external pin input.
130
DVDD5
131
VCOO
O
132
VCOI
I
1, Z, 0
SENS output to CPU.
Digital GND.
TEST pin. Leave this open.
1, Z, 0
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
Analog GND.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high.
Disc innermost track detection signal input.
Digital GND.
1, 0
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
Pin No.
Symbol
I/O
133
TEST
I
134
PDO
O
135
VCKI
I
136
V16M
O
137
AVDD2
138
IGEN
Description
1, Z, 0
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
Set VCKI to low when the external clock is not input to this pin.
1, 0
Wide-band EFM PLL VCO2 oscillation output.
I
Connects the operational amplifier current soource reference resistance.
AVss2
_
Analog GND.
140
ADIO
O
_
Operational amplifier output.
141
RFDC
I
RF signal input.
142
CE
I
Center servo analog input.
143
TE
I
Tracking error signal input.
139
* In the CXD3011R, the following pins are NC.
Pins 1, 18 to 21, 36, 37, 53 to 56, 72, 73, 89 to 92, 108, 109, 125 to 128 and 144.
Notes :
• The 64-bit slot is a LSB first, two’s complement output. The 48-bit slot is a MSB first, two’s complement
output.
• GTOP is used to monitor the frame sync protection status. (High : Sync protection window released)
• XUGF is the frame sync obtained from EFM signal, and is negative pulse. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM
signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the +28F jitter margin.
43
TROUBLESHOOTING GUIDE
Reset or Power ON.
Are the pin 38 ~ 42
of PN 701 +5V respectively
after the power cable
connecting?
(Check it after connecting the power cable only no interface cable)
NO
• Check the power short.
• Check PC power cable, power
supply and fuse.
OK
Repair PC power supply.
YES
Is the pin 1 of
IC102 3.3V?
NO
Replace IC101 (3.3V Regulator).
Check the 6 , 7 pin of
YES
IC402. (1.65V)
Is the pin 36 of
IC201 1.65V?
OK
NO
Check the VREF line.
Between 36 pin (VREF) of
IC301 and 4 pin (VC)
of IC301.
YES
NO
Is the pin 3 of
IC101 3.3V?
NO
Replace IC101 (3.3V Regulator).
YES
Do the X401, and
X301 oscillating?
NO
Replace X401, and X301 when
the power supply of IC401 and
IC301 is OK.
YES
Does the pin 63
of IC501 change 0V to 5V at
the power supply initial
input mode?
NO
Replace IC501 when the IC101
(3.3V Regulator & Reset IC) is
non-ok.
YES
Does the tray open or
close?
YES
A
44
NO
Refer to “Tray open / close
doesn’t work.”
Replace IC402
A
Is the Laser Diode
“ON”?
NO
Refer to “Laser Diode is not on.”
YES
Does the Focus move
up and down?
NO
Refer to “Servo part is
abnormal”.
YES
Is the TOC area
on the disc read? (Does
the LED Blink?)
NO
Refer to “Disc Reading
operation is abnormal.”
45
Tray open(eject) doesn’t work.
Does the
waveform appear at
the IC501 pin 89 when push
the SW602 (open/close)?
NO
Check and replace the Eject
SW or peripheral resistor and
pattern short.
5V
Push period
YES
Does the
waveform appear
at the R602 connected to
IC601 pin 4, that is connected
to IC601 reversely?
NO
Check and replace the R602,
or pattern short.
normal
YES
Does the
IC301 pin 111
appear in the open(eject)
mode ?
NO
Check and replace the IC301.
YES
Does the
signal appear
at the IC601 pin 10
and 11?
Pin 10
Pin 11
YES
B
46
NO
Check the cold soldering for
the IC601 and then replace
IC601.
B
Is the
connecting status normal
between the PN201
and sled(Feed)
motor?
NO
the PN201 and FPC
connecting status and then
replace Sled(Feed) motor.
YES
Open(eject) mode is normal.
47
Laser Diode is not ON.
C
NO
Does the focusing
actuator move up and
down?
Refer to “Reset or Power ON”.
YES
CD PART
DVD PART
Is the PN201
pin 15 about 2V at the
initial power on mode?
NO
Does the
signal appear at IC201
Pin 21?
YES
NO
5V
3V
OK
YES
Does the
Pin 26?
LD ON
5V
NO
0V
YES
the transistor Q202 and then
replace Q202.
NO
Is the collector of
transistor Q202 about
2V?
YES
Replace the Pick-up.
48
IC201.
IC501.
C
Is the PN201
pin 9 about 2V
at the initial power on mode?
NO
YES
Does the
Pin 22?
NO
5V
OK
3V
YES
NO
the transistor Q201 and then
replace Q201.
Is the collector of
transistor Q201 about
2V?
YES
Replace the Pick-up.
Does the
Pin 26?
LD ON
NO
5V
0V
YES
IC501.
IC201.
49
Check the CD RF SIGNAL.
Does the RF out signal
output?
(IC301 pin 64 : CD RF)
NO
• Check the cold soldering for
the IC301 pin 13, 14, 15, 16.
• Check the FPC connecting
status PN 201.
• Check the pick up.
YES
Does the RF
signal output at the
IC201 Pin 57?
(RF Level : about 1.0V)
NO
the C208, C212.
• Replace IC201.
YES
Does the
RF signal input to the
IC301 Pin 13?
50
NO
Check the cold soldering for the
C319.
Check the DVD RF signal.
Does the RF out signal
output from the pick-up?
(IC201 pin 1 : DVD RF)
NO
the IC201 pin 1, 2, 3.
status PN201.
• Check the pick up.
YES
Does the RF signal output
from the IC201 pin57?
(RF Level : about 1.0V)
NO
• Check the cold soldering for the
C215, C214, C218, C219, C220,
C221.
• Replace IC301.
YES
Does the RF signal
output from the IC401
pin117?
NO
R404, C404 and IC401.
51
Disc Rotation is unstable.
Does the spindle
motor kick signal and
driving signal output from
the IC401 pin135(SPD0)?
<Fig.1>
NO
IC401 and then replace IC401.
<Fig. 1>
YES
Does the
spindle driving signal
output from IC601 normally?
(IC601 Pin 22)
<Fig.2>)
NO
<Fig. 2>
R604 , R607, R606, R611,
C604, C607 and IC601 and then
replace IC601.
YES
Does the
PN201 spindle driving
signal output from pin31,32
normally? <Fig. 2>
(For CD and DVD)
YES
Replace the Spindle motor.
52
NO
PN201 and connecting status
FPC.
Servo part is abnormal.
Insert a disc.
YES
Does the pick-up slide
inner track?
NO
status PN201.
the pin 10, 11 of IC601.
YES
NO
Refer to “Spindle motor
Rotation is failed”.
Does the disc rotate?
YES
NO
Refer to “Laser Diode is not
ON”.
Is the Laser Diode on?
YES
NO
A
Does the focus move up
and down?
YES
Is the FOK signal “H”?
(IC301 Pin 105)
NO
B
YES
Does the disc rotate in
high speed repeatedly?
NO
C
YES
NO
Is the GFS signal “H”?
CD: CGFS
IC301 Pin 41
DVD: DGFS
IC401 Pin 107
YES
IC301 and IC401.
OK
53
A
Check the FAO signal.
(IC301 Pin 113 )
V
NO
1.65V
Check the circuit between the
IC601 Pin 24 and R601
and the IC301 Pin 113.
T
YES
the IC601(BA5918FP)
pin 13, 14.
Replace IC601.
B
IC201 Pin 1, 38, 40, 63 and C215,
C217 and IC301 Pin 3, 141.
C
Does the square wave
output at the PN201 Pin
33(FG)?
NO
Check the FG signal line.
54
YES
the PN201(pin 33) and IC501
Pin 96, 97.
Spindle Motor Rotation is
failed.
Check the spindle drive
signal.
(IC401 BA6664 Pin 22)
V
1.65V
T
100ms
NO
Does the above
signal output after the
tray close?
the IC601(BA5918FP) and
periphrals.
YES
Check the MDP signal.
(IC401 CXD1867R Pin 135)
Is the disc rotation OK?
NO
Does the above
signal output after the
tray close?
YES
Replace the
IC601(BA5918FP).
NO
Check the cold soldering
for the IC401(CXD1867R).
for the IC601 (BA5918FP)
and PN201 Pin 27~33.
YES
Check the X-tal oscillating
(33.8688MHz) at the IC301
(CXD3011R) Pin 83 and 84.
Check the IC301
(CXD3011R) Pin 83, 84 and
99 (µ-com I/F line).
for the IC501(H8/3062)
µ-com.
Check the Main FPC and
spindle motor ASS’Y.
Replace the Main FPC.
Replace the Spindle Motor
Ass’y.
55
No Audio output.
Insert the audio disc.
Does the
Line out?
YES
Check the Line out cable.
NO
Is the
pin 4 of IC801 is the
”High”?
NO
Check the MICOM IC501 pin 24
and R801.
YES
Does the
Audio signal output at
the C802 and C808?
YES
PN701, PN1~4.
NO
Does the
Audio signal inputted at pin 6, 7,
10, 11, of IC801?
YES
Check the IC801 and
peripheral components.
NO
Does the
Audio signal output at
IC301 pin 79,80 and
87, 88?
YES
Replace IC801
NO
Does the
pin 27, 29 and 31 of
IC301?
NO
Check the servo part.
56
YES
Replace R318, R317 and
R316.
Mute on “L”.
Mute off “H”.
72
BA6664FM
MOTOR DRIVE
Spindle
Motor
Tray
Motor
BA5983FM
F.T.S.T DRIVE
FCS
TRK
SLED
Motor
Laser
Power
BA5925
Sled
Speed
Optical
Pick-up
KRS-202A/220C
AT93C86
1kB
EEPROM
Address/Data
OPC/ROPC
Circuit
Timing Signals
Audio
Mute
H/P Amp
DSP+Servo
DECODER
ENCODER
ATIP Demodulator
Write Strategy
I/F
OTI9790
Data
I/F
Cable
Line Out
Headphone
Jack
L,R
L,R
2MB
DRAM
H
O
S
T
1. Block Diagram of CD-R/RW Drive
M62352
12ch
8bit DAC
H8/3062
System
Controller
20MHZ
RF/Servo Signal
17.43MHz
CPLD
Laser Control
S/H Signal Gen.
S/H
CXA2551R
RF Amp
Wobble
ALPC
33.86MHz
BLOCK DIAGRAM
12V
Act _Mute
UA[0:8], UAD[0:15]
URDY, URD, UWR
/UCS0, 1
DSP/Servo
/ATAPI
/PRST
IC201
OTI-9790
8V
IC511
NJM7808
Regulator
IC501 BA5983
FCS/TRK/SLD/TRY
Driver
8V
IC512
NJM7808
Regulator
+12V
L101
Bead
GND
41
44
/EPCS
SDATA, SCLK
/DACS
SDATA, SCLK
/CXACS
/RESET
RESET
IC302
AT93C86
EEPROM
IC409
M62352
DAC
2V_ACT
32
OP Amp
NJM3414
IC514
2V
CXA2551 ASP
IC401
(3.9V)
4V
BA3939
Regulator
BA033S
Regulator
XC61AN
3.3V
IC103
IC102
IC101
SDATA, SCLK
L102
Bead
IC301
HD64F3062
µ-COM
GND
PN201
42 43
+5V
From HOST
2.5V
5V
2. Power Block Diagram
73
74
MD
U,V,W
HU,HV,HW
TRY+/SLD+/FCS+/TRK+/-
A,B,C,D,E,F,G,H
IC510
BA6664
Drive
IC501
BA5983
Drive
HA+/H1+/-,H2+/-
IC401
CXA2551
ASP
IC403
NJM3404
EC
IC508
BU4053
IC412
TC7W08
IC509
NJM3404
SPDL FG
SLO
DMO
FAO/TAO
/UCS0,1,URDY,URD,UWR
UA[0:8],UAD[0:15]
BS
RX
RPBC
TEBC
TE
TX
CE
WBLIN
WGATE,LDON
EFCK,EEPS
EFM1,2,3
IC411
NJM3404
IC601
XC9536
CPLD
IC414
NC7SZ66
IC409
M62352,DAC
IC301
HD64F3062
µ-COM
SLD_MOV
IC509
BA5925
Sled Speed
SLD FG
TRY CTL
MPXO
IC403
NJM3404
IC404
NJM2903
RECD1,2,XTOR
PHO1
RFRP,RFCT
CE
ATFG
TZC
TE
FE
WFPDSH, RFPDSH, WBLSH, SPDSH, MPDSH
W/XR, OSCEN,ENBL,ODON
IC201
OTI-9790
3. System Control Block Diagram
MD
VWDC2
WREF
RPOWER
VRDC, VWC1
FPDO
A,B,C,D,E,F,G,H
IC409
M62352
DAC
IC401
CXA2551
ASP
H/P Out
SDATA,SCLK
/DACS
BLEBEL0
BETA,ASYM1,2
EQRFN,EQRFP
RRF
RRFIN
PHO1
IC801
H/P Amp
Line out
IC301
HD64F3062
µ-COM
IC405
BU4052B
IC413
EL2245CS
IC403
NJM3403
ERGCNT,WBLON
WFPDSH,RFPDSH,WBLSH,SPDSH,MPDSH
W/XR,OSCEN,ENBL,ODON
Q804
Mute Control
/UCS0,1,URDY,URD,UWR
UA[0:8],UAD[0:15]
(1.2V)
Rout
Lout
BS
WGATE,LDON
EFCK,EEPS
EFM1,2,3
EFM(RFAC)
RFDC(1V)
IC601
XC9536
CPLD
IC201
OTI-9790
4. Write/Read Block Diagram
75
5. Block Diagram
5
* CED-8080B : Optical Pick-up KRS-202A
* CED-8083B : Optical Pick-up KRS-220C
33.86MHz
I/F
cable
H
O
S
T
OTI9790
CXA2551R
RF Amp.
Wobble
ALPC
4
*Optical
Pick-up
KRS-202A/220C
Disc
Motor unit
GRS-R02A/
OSM-32A
3
SPINDLE
MOTOR
FOCUS
COIL
DSP + Servo
DECODER
ENCODER
ATIP Demodulator
Write Strategy
I/F
SLED
MOTOR
CPLD
Command
LOADING
MOTOR
20MHz
H8/3062
System
Controller
BA6664FM
MOTOR DRIVE
DRAM
Data
Laser
Control
TRACKING
COIL
Data
AUDIO
Circuitry
Beta
BA5983FM
F.T.S.F DRIVE
Headphone
Jack
RF
ROPC
Circuit
R-ch
A1,A2, B Level
L-ch
2
+8V
A
76
+3.3V
3.9V Reg.
+3.9V
Line-out
8V Reg.
1
3.3V Reg.
+5V
+5V
GND
GND
GND
GND
+12V
+12V
B
C
D
EXPLODED VIEW
436
5
436
436
001
011
013
4
010
436
012
006
008
436
007
009
3
PBM00(MAIN C.B.A)˚
A01
2
004
435
435
435
435
003
435
005
1
A00
A
6
B
C
D

DRN 8080B본문_수출

Transcription

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