compal confidential

Transcription

compal confidential

A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : JAL10
PCB NO : LA4151P(DAA00000Q1L)
BOM P/N :
1
M09 Lola UMA
uFCBGA Mobile Penryn
Intel Cantiga GM + ICH9M
2
2
2008-07-4
REV : 1.0
@ : Nopop Component
1@ : Use TCM only
2@ : Use TAA only
3@ : Use BROADCOM TPM only
4@ : Use without TAA only
5@ : Use with BKT only
6@ : Use without BKT only
7@ : Use disable TPM only
8@ : Use with TCM depop
9@ : Use with ZTE TCM
10@ : Use with Jetway TCM
3
4
3
4
MB PCB
Part Number
DELL CONFIDENTIAL/PROPRIETARY
Description
DAA00000Q1L
PCB 03S LA-4151P REV0 M/B
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Cover Sheet
Size
Document Number
Date:
Friday, July 04, 2008
Rev
1.0
LA-4151P
Sheet
E
1
of
57
A
B
C
D
E
Block Diagram
Compal confidential
Model : JAL10
FAN
Thermal
GUARDIAN III
EMC4002
+FAN1_VOUT
page 18
1
+3.3V_SUS
+1.5V_RUN
22X22mm
Pentium-M
Penryn -4MB
uFCBGA SFF CPU
+VCC_CORE
+5V_RUN page 29
RGB
Vedio Switch
TS3DV520ERHUR
+3.3V_RUN
SVID
page 20
page6
1
H_D#(0..63)
System Bus
FSB 800/1066 MHz
LVDS
RGB
+3.3V_M
page 7
page 7,8,9
956pin
H_A#(3..35)
CRT CONN
+1.05V_VCCP
+1.05V_VCCP
page 18
On daughter board
Clock Generator
CK505
SLG8LP554
CPU ITP Port
INTEL
+3.3V_RUN
RGB
SVID
Memory BUS
(DDR3) +1.5V_MEM
25X27mm
DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
800 / 1066MHz
page 16,17
+1.5V_MEM
+0.75V_DDR_VTT
Cantiga SFF
+1.8V_RUN
+1.5V_MEM
DPB
+1.5V_RUN
D PC
1363pin BGA
+VCC_GFXCORE
+1.05V_M
SD/MMC/MMC+
CONN
+1.05V_VCCP
page 10,11,12,13,14,15
SATA4
E-SATA
+3.3V_RUN page 27
2
PCI BUS
DOCKING
PORT
USB[3]
DMI
+3VRUN 33MHz
page 31
ExpressCard
USB[8,9]
PCIE4
PCIE2
USB[7]
PCI Express BUS
Mini Card 1
WWAN
+3.3V_WLAN
+1.5V_RUNpage 21
USB[4]
S-ATA 0/1
SPI
ODD
LPC BUS
USH TPM1.2
SSX35BCB
BCM5880
73S8009CN
W25X32VSSIG
+3V_RUN
33MHz
page 24
+3.3V_LAN
RFID
On daughter board
USBH
Trough FPC
SMBUS
LVDS CONN
+PWR_SRC
+5V_ALW
+3.3V_RUN
BKT CONN
+3.3V_BKT_PWR page 39
4
+RTC_CELL
+3.3V_ALW
Camera Card
page 19
USB[11]
Trough Cable BC BUS
BKT_USBBIO
Biometric
+3.3V_RUN
ECE1077
Touch Pad Stick
page 29
+3.3V_ALW
page 35
page 35
+3.3V_RUN
page 26
Azalia Codec
92HD71B
3V/5V
BATT IN
page 42
page 45
CHARGER
1.5V/1.05V
page 43
page 46
Power Sequence
page 41
DC IN
page 41
page 34
+3.3V_ALW
page 34
BC BUS
BC BUS
ECE1088
B
RJ45
SNIFFER
DAI
S SM2602
SMSC SIO
ECE5028
+3.3V_RUN page 21
DOCK
+3.3V_ALW page 33
Dig. MIC
+3.3V_ALW
page 35
page 19
Trough cable
Int.KBD &
Stickpage 35
4
Title
Block Diagram
Size
38
Document Number
Rev
1.0
LA-4151P
C
3
+3.3V_RUN page 21
Date:
A
+3.3V_ALW pg 21
page 21
HeadPhone &
MIC Jack
SST25VF016B
page 37
Power On/Off
SW & LEDpage
+5V_RUN
+3.3V_RUN
+VDDA
page 21
page 44
VCORE (IMVP-6)
LAN SWITCH
PI3L500-AZFEX
AMP & INT.
Speaker
DOCK LPC BUS
page 19
Trough FPC
1.8V/0.75V
SMSC KBC
MEC5035
USB[10]
page 32
Trough BTB
+3.3V_ALW
+1.8V_LAN_M
+1V_LAN_M page 21
S-HDD
page 24
+3.3V_LAN
SPI
page 21
+5V_HDD
W25X32VSSIG
Trough FPC
USB Ports X1
SATA0
16M 4K section
+3.3V_RUN
+2.5V_RUN
+1.2V_RUN page 32
+5V_RUN
+3.3V_RUN page 32
+5V_MOD
page 26
2
page 29
Intel Boaz
82567LM
SATA1
page 30
USB[6]
Smartpage
Card
32
+1.05V_VCCP
R SIDE
On daughter board
Trough BTB
+3V_RUN/ +1.5V_RUN 100MHz
GLCI/LCI
page 22,23,24,25
page 30
BKT_USBH
USB[5]
3
Azalia I/F
TPM1.2
For China
+3.3V_RUN
USB[0]
+5V_ALW
Option
BlueTooth
+3.3V_RUN
+1.5V_RUN page 21
48MHz
INTEL
+RTC_CELL
+3.3V_ALW_ICH ICH9-M SFF
+3.3V_RUN
569pin BGA
+1.5V_RUN
Trough BTB
+3.3V_RUN/ +1.5V_RUN 100MHz
Trough FFC
PCIE1
Mini Card2
WLAN
IEEE1394
page 21
+3.3V_RUN page 27
+3.3V_RUN
+1.5V_RUN
page 28
SATA3
DOCK LPC BUS
16X16mm
R5C833
page 29
USB Ports X1
+5V_ALW
+1.5V_RUN
100MHz
IDSEL:AD17
(PIRQC#,PIRQD#,GNT#1,REQ#1)
DAI
L SIDE
D
Sheet
E
2
of
57
5
4
3
2
POWER STATES
USB PORT#
SLP
S3#
SLP
S4#
SLP
S5#
S4
STATE#
SLP
M#
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
HIGH
S3 (Suspend to RAM) / M1
LOW
HIGH
HIGH
HIGH
S4 (Suspend to DISK) / M1
LOW
HIGH
HIGH
S5 (SOFT OFF) / M1
LOW
HIGH
S3 (Suspend to RAM) / M-OFF
LOW
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
Signal
State
D
C
1
ALWAYS
PLANE
M
PLANE
SUS
PLANE
RUN
PLANE
ON
ON
ON
ON
HIGH
ON
ON
ON
LOW
HIGH
ON
ON
LOW
LOW
HIGH
ON
HIGH
HIGH
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
CLOCKS
0
JUSB1 (Ext Right Side Top)
ON
1
BLT mode
OFF
ON
2
None
ON
OFF
ON
3
JESATA1 (Ext Left Side Bottom)
ON
ON
OFF
ON
4
WLAN
ON
OFF
ON
OFF
OFF
5
WWAN
LOW
ON
OFF
OFF
OFF
OFF
6
BT
LOW
ON
OFF
OFF
OFF
OFF
7
Express card
8
DOCKING
9
DOCKING
10
USH->BIO
11
Camera
ICH9-M
PM TABLE
power
plane
+15V_ALW
+3.3V_SUS
+5V_ALW
+1.5V_MEM
DESTINATION
+5V_RUN
+3.3V_M
+3.3V_M
+3.3V_RUN
+1.05V_M
+1.05V_M
+3.3V_ALW_ICH
+2.5V_RUN
+3.3V_RTC_LDO
+1.5V_RUN
(M-OFF)
+3.3V_RUN_
WWAN_PWR
+3.3V_RUN_
BKT_PWR
D
C
+1.8V_RUN
+0.75V_DDR_VTT
State
B
+VCC_GFXCORE
+3.3V_BKT
_PWR
+VCC_CORE
+INV_PWR_SRC
+1.05V_VCCP
+LCDVDD
PCI EXPRESS
DESTINATION
Lane 1
MINI CARD-1 WWAN
S0
ON
ON
ON
ON
ON
ON
Lane 2
MINI CARD-2 WLAN
S3
ON
ON
OFF
ON
OFF
OFF
Lane 3
None
S5 S4/AC
ON
OFF
OFF
ON
OFF
OFF
Lane 4
EXPRESS CARD
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
OFF
Lane 5
None
BlackTop mode
ON
OFF
OFF
OFF
OFF
ON
Lane 6
10/100/1G LAN
B
PCI TABLE
PCI DEVICE
IDSEL
REQ#/GNT#
PIRQ
R5C833
AD17
REQ#1 / GNT#1
PIRQ[C..D]
A
A
Title
Index and Config.
Size
4
3
2
Rev
1.0
LA-4151P
Date:
5
Document Number
Sheet
1
3
of
57
5
4
RUN_ON
3
FDS4435
Q16
2
1
+INV_PWR_SRC
ADAPTER
D
GFX_CORE_ON
D
ADP3209
(PU15)
+VGFX_COREP
BlackTop function
+PWR_SRC
RUN_ON&BKT_GPIO4
BATTERY
STS11NF30L
(Q145)
+5V_RUN_
BKT_PWR
+15V_ALW
RUN_ON
STS11NF30L
(Q55)
ALWON
CHARGER
ISL6260
MAX8794
(PU12)
(PU7)
TPS51100D
GQRG4
(PU14)
+5V_ALW
VT351FC
(PU25,PU26)
ISL6236
(PU2)
MAX8511(LDO)
ALWON
C
(Q60)
+5V_ALW
+3.3V_SUS
+VCC_CORE
+1.8V_RUN
+0.75V_DDR_VTT
+1.05V_M
+1.5V_MEM
SI4336DY
(Q128)
3.3V_RUN_ON
ENAB_3VLAN
DDR_ON
M_ON
0.75V_DDR_VTT_ON
1.8V_RUN_ON
IMVP_VR_ON
3.3V_SUS_ON
SI3456BDV
(PU2)
1.05V_RUN_ON
ISL6236
1.5V_RUN_ON
BKT_GPIO2
BlackTop function
+3.3V_LAN
+1.05V_VCCP
+3.3V_RUN
REGCTL_PNP18
On I/O board
REGCTL_PNP1
MODC_EN
HDDC_EN
RUN_ON
TPA6040
(U9)
SI4336DY
(Q61)
SI4336DY
(Q140)
+1.5V_RUN
SI4336DY
Q67
SI3456BDV
(Q29)
C
3.3V_RUN_ON&BKT_GPIO3
STS11NF30L
(Q44)
B
SI3456BDV
(Q32)
+1.5V_ALW_HDA
(U103)
+3.3V_ALW
ALW_ON
+5V_RUN
BCP69
(Q4)
BCP69
(Q3)
+3.3V_RUN_
BKT_PWR
SI3456BDV
(Q143)
SI4336DY
(Q137)
+3.3V_RUN_
WWAN_PWR
+3.3V_BKT_PWR
+1V_LAN_M
A
+5V_HDD
+5V_MOD
B
+1.8V_LAN_M
A
+VDDA
on I/O board
Title
Power Rail
Size
4
3
2
Rev
1.0
LA-4151P
Date:
5
Document Number
Sheet
1
4
of
57
5
4
3
+3.3V_ALW
2.2K
G16
ICH_SMBCLK
A13
ICH_SMBDATA
2
1
2.2K
2.2K
2N7002
+3.3V_M
2.2K
MEM_SCLK
197
MEM_SDATA
195
DIMMA
SMBUS Address[A0h]
2N7002
10K
ICH9-M
197
D
+3.3V_ALW_ICH
10K
E18
AMT_SMBCLK
A24
AMT_SMBDAT
195
DIMMB
SMBUS Address[A4h]
D
8.2K
93
2A
94
+5V_ALW
8.2K
2A
6
DOCK_SMB_CLK
6
5
DOCK_SMB_DAT
5
1A
SMBUS Address[48h]Dock_APR
DOCKING
1A
SMBUS Address[70h]DOCK_SPR
8.2K
+3.3V_ALW
8.2K
8
LCD_SMBCLK
6
7
LCD_SMDATA
5
1B
C
1B
INVERTER
(JLVDS)
C
SMBUS Address[58h]
2.2K
+3.3V_ALW
2.2K
KBC
1C
112
PBAT_SMBCLK
1C
111
PBAT_SMBDAT
100 ohm
100 ohm
3
4
BATTERY
CONN
SMBUS Address[16h]
2.2K
2.2K
2.2K
10
1D
9
1D
2N7002
+3.3V_ALW
2.2K
BKT_SMBCLK
27
99
BKT_SMBDAT
29
1E
BKT
CONN
1F
98
97
8
Express card
SMBUS Address[TBD]
2.2K
SMBUS Address[TBD]
2.2K
B
1F
7
EXP_SMBDATA
2N7002
100
1E
+3.3V_SUS
EXP_SMBCLK
CARD_SMBCLK
2N7002
CARD_SMBDAT
2N7002
WLAN_SMBCLK
30
WLAN_SMBDATA
32
2.2K
96
2N7002
95
2N7002
1H
B
WLAN
SMBUS Address[TBD]
2.2K
MEC 5035
1G
+3.3V_WLAN
+3.3V_RUN
MINI_SMBCLK
30
MINI_SMBDATA
32
WWAN
SMBUS Address[TBD]
2.2K
2.2K
2.2K
12
CKG_SMBDAT
13
CKG_SMBCLK
1H
+3.3V_ALW
2.2K
2N7002
1H
2N7002
+3.3V_M
CLK_SDATA
17
CLK_SCLK
16 CLK GEN
SMBUS Address[a2h]
9
A
106
10
Charger
105
1J
Dedicated JTAG
A
2N7002
1J
2N7002
SMBUS Address[12h]
DAI
103
Title
1K
102
1K
Dedicated JTAG
SMBUS TOPOLOGY
SMBUS Address[35h]
Size
Document Number
Rev
1.0
LA-4151P
Date:
5
4
3
2
Sheet
1
5
of
57
5
4
3
+3.3V_M
1
2
1
2
2
1
2
1
2
1
2
1
2
C7
0.1U_0402_16V4Z~D
1
C6
0.1U_0402_16V4Z~D
2
C5
0.1U_0402_16V4Z~D
2
1
+CK_VDD_MAIN
1
C4
0.1U_0402_16V4Z~D
2
BK2125HS601-T 0805~D
C3
0.1U_0402_16V4Z~D
2
1
L1
C2
10U_0805_10V4Z~D
R2
2.2K_0402_5%~D
1
R1
2.2K_0402_5%~D
6
<21,34,46> CKG_SMBDAT
D
1
C1
0.1U_0402_16V4Z~D
+3.3V_M
2
+CK_VDD_MAIN
CLK_SDATA
Q1A
2N7002DW-T/R7_SOT363-6~D
D
+CK_VDD_48
1
*
CPU
MHz
SRC
MHz
PCI
MHz
0
0
0
266
100
33.3
0
0
1
133
100
33.3
0
1
0
200
100
33.3
1
0
1
166
100
1
2
1
U1
1
2
2
X1
14.31818MHz_20P_1BX14318CC1A~D
2
1
C16
33P_0402_50V8J~D
33.3
+CK_VDD_A
2
2.2_0603_5%~D
1
R12
1
R14
2 +CK_VDD_REF
0_0603_5%~D
2 +CK_VDD_48
0_0603_5%~D
1
49
54
65
VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC
30
36
VDD_PCI
VDD_PCI
12
VDD_CPU
18
VDD_REF
40
VDD_A
7
SLG8LP554VTR VSS_A
8
0
333
100
33.3
1
0
1
100
100
33.3
1
1
0
400
100
33.3
CLK_XTAL_IN
Place crystal within
500 mils of CK505
C17
33P_0402_50V8J~D
2
1
CLK_ICH_48M
CPU_MCH_BSEL0
CPU_MCH_BSEL1
<8,10> CPU_MCH_BSEL2
CPU_MCH_BSEL2
1
1
<24> CLK_ICH_14M
<30> CLK_TCM_14M
<33> CLK_SIO_14M
@ R55
10K_0402_5%~D
<10> MCH_DREFCLK
2
2
2
1
1
2 33_0402_5%~D
2.2K_0402_5%~D
1
11
MCH_BCLK
10
MCH_BCLK#
CPU_0
14
CPU_BCLK
CPU_0#
13
CPU_BCLK#
CPU_ITP/SRC_10
6
CPU_ITP
CPU_ITP#/SRC_10#
5
CPU_ITP#
SRC_9
3
PCIE_MINI1
SRC_9#
2
PCIE_MINI1#
CLKREQ_9#
72
MINI1CLK_REQ#
SRC_8
70
PCIE_MINI2
2
1
CLK_ICH_14M
R33
CLK_TCM_14M1@R1114
CLK_SIO_14M
R35
1
1
1
MCH_DREFCLK
1
2
2 22_0402_5%~D
2 22_0402_5%~D
22_0402_5%~D
2
33_0402_5%~D
2
33_0402_5%~D
R32
R38
R41
1
2
1
19
XTAL_OUT
41
USB_48MHz/FSLA
45
FSL_B/TEST_MODE
23
REF_0/FSL_C/TEST_SEL
FSC
CLK_PCI_5035
CLK_PCI_ICH
33_0402_5%~D
22_0402_5%~D
22_0402_5%~D
22_0402_5%~D
33_0402_5%~D
PCI_SIO
34
PCICLK4/FCT_SEL
PCI_TPM
33
PCICLK3
PCI_DOCKING
32
PCICLK2/TME
PCI_EC
27
PCICLK1
CLKREF
22
REF_1
DOT96
43
DOT_96/27M
DOT96#
44
DOT_96#/27M_SS
PCI_ICH
37
33_0402_5%~D
33_0402_5%~D
CLK_PWRGD
<24> CLK_PWRGD
XTAL_IN
FSA
10K_0402_5%~D
1
1
2
2
2
MCH_DREFCLK#
<22> CLK_PCI_ICH
2
39
9
+3.3V_RUN
1
R1112
10K_0402_5%~D
TME
0
PIN 32
overclocking enabled
2
2
1
R43
10K_0402_5%~D
MINI1CLK_REQ#
PCI_DOCKING
1
*
overclocling disabled
1
R4
MINI2CLK_REQ# 1
R5
CLK_3GPLLREQ# 1
R6
SATA_CLKREQ#
1
R7
EXPCLK_REQ#
1
R356
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
CLK_SCLK
16
CLK_SDATA
1
R46
10K_0402_5%~D
2
+3.3V_RUN
A
*
1
R54
10K_0402_5%~D
2
PCIE_MINI2#
MINI2CLK_REQ#
SRC_7
66
PCIE_ICH
PCIE_ICH#
SRC_7#
67
CLKREQ_7#
38
SRC_6
63
SRC_6#
64
CLKREQ_6#
62
CKPWRGD/PD#
SRC_5
60
SRC_5#
61
CLKREQ_5#
29
NC
SRC_4
58
PCIE_EXP
59
PCIE_EXP#
CLKREQ_4#
57
EXPCLK_REQ#
SRC_3
55
MCH_3GPLL
56
SMBDAT
4
VSS_SRC
SRC_3#
15
VSS_CPU
CLKREQ_3#
28
21
VSS_REF
SRC_2
52
VSS_PCI
SRC_2#
53
35
VSS_PCI
CLKREQ_2#
26
0
Pin 5/6 as SRC_10
42
VSS_48
1
Pin 5/6 as CPU_ITP
68
VSS_SRC
73
THRM_PAD
FCTSEL1
0=UMA
PIN43
PIN44
PIN47
PIN48
DOT96T
DOT96C
96/100M_T
96/100M_C
27M_out
27M SSout
SRCT0
SRCC0
PCIE_SATA
PCIE_SATA#
47
LCD_CLK#/SRC_0#
48
1
R11
1
R13
CLK_MCH_BCLK
2
33_0402_5%~D
CLK_MCH_BCLK#
2
33_0402_5%~D
1
R15
1
R16
CLK_CPU_BCLK
2
33_0402_5%~D
CLK_CPU_BCLK#
2
33_0402_5%~D
1
@ R18
1
@ R21
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
C
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP
2
33_0402_5%~D
CLK_CPU_ITP#
2
33_0402_5%~D
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
1
R23
1
R25
CLK_PCIE_MINI1
2
33_0402_5%~D
CLK_PCIE_MINI1 <21>
CLK_PCIE_MINI1#
2
33_0402_5%~D
CLK_PCIE_MINI1# <21>
1
R28
1
R31
CLK_PCIE_MINI2
2
33_0402_5%~D
CLK_PCIE_MINI2#
2
33_0402_5%~D
1
R34
1
R36
CLK_PCIE_ICH
2
33_0402_5%~D
CLK_PCIE_ICH#
2
33_0402_5%~D
MINI1CLK_REQ# <21>
CLK_PCIE_MINI2 <21>
CLK_PCIE_MINI2# <21>
MINI2CLK_REQ# <21>
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
1
R408
1
R415
CLK_PCIE_EXP
2
33_0402_5%~D
CLK_PCIE_EXP#
2
33_0402_5%~D
CLK_PCIE_EXP <28>
CLK_PCIE_EXP# <28>
EXPCLK_REQ# <28>
CLK_PCIE_SATA
2
33_0402_5%~D
CLK_PCIE_SATA#
2
33_0402_5%~D
SATA_CLKREQ#
2
475_0402_1%~D
DREF_SSCLK
2
33_0402_5%~D
DREF_SSCLK#
2
33_0402_5%~D
50
51
46
<24>
H_STP_CPU# <24>
CLK_MCH_3GPLL
2
33_0402_5%~D
CLK_MCH_3GPLL#
2
33_0402_5%~D
2CLK_3GPLLREQ#
475_0402_1%~D
SRC_1/SATA
CLKREQ_1#
H_STP_PCI#
1
R45
MCH_3GPLL#
1
R47
CLK_3GPLLREQ#_R 1
R48
SRC_1#/SATA#
LCD_CLK/SRC_0
2
B
SRC_4#
SMBCLK
31
PCI_SIO
*
69
71
PIN 37
ITP_EN
PCI_ICH
17
SRC_8#
CLKREQ_8#
PCICLK_F0/ITP_EN
+3.3V_RUN+3.3V_M
@
H_STP_CPU#
VDD_48
CLK_XTAL_OUT
0_0402_5%~D
R26 2
R30 2
R29 1
1@ R986 1
CLK_PCI_DOCK
R27 1
R37
<10> MCH_DREFCLK#
B
1
CLK_PCI_5028
CLK_PCI_PCM
CLK_PCI_TPM
<34> CLK_PCI_5035
FSA
R19
R22
R24
<33> CLK_PCI_5028
<27> CLK_PCI_PCM
<32> CLK_PCI_TPM
<30> CLK_PCI_TPM_CHA
<31> CLK_PCI_DOCK
@ R51
10K_0402_5%~D
2
R17
<24> CLK_ICH_48M
+3.3V_M
20
H_STP_PCI#
CPU_1
2
0
25
24
CPU_1#
C
1
PCI_STP#
CPU_STP#
1
C15
0.047U_0402_16V4Z~D
FSA
CLKSEL0
1
R10
C10
0.1U_0402_16V4Z~D
FSB
CLKSEL1
2
C9
0.1U_0402_16V4Z~D
FSC
CLKSEL2
2
1
C14
4.7U_0603_6.3V4Z~D
2
1
@
+CK_VDD_REF
C13
0.047U_0402_16V7K~D
CLK_SCLK
C12
0.047U_0402_16V4Z~D
Q1B
2N7002DW-T/R7_SOT363-6~D
4
C11
4.7U_0603_6.3V4Z~D
3
<21,34,46> CKG_SMBCLK
1
5
+3.3V_M
1
R49
1
R52
SATA_CLKREQ#_R 1
R53
DOT96_SSC
1
R523
DOT96_SSC#
1
R670
CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>
CLK_3GPLLREQ# <10>
CLK_PCIE_SATA <23>
CLK_PCIE_SATA# <23>
SATA_CLKREQ# <24>
A
DREF_SSCLK <10>
DREF_SSCLK# <10>
SLG8LP554VTR_QFN72_10X10~D
1=DIS
0=UMA
1=Disc. GRFX down
Title
Clock Generator
Size
4
3
2
Rev
1.0
LA-4151P
Date:
5
Document Number
Sheet
1
6
of
57
<10> H_ADSTB#1
H_STPCLK#
H_INTR
H_NMI
H_SMI#
F8
C9
C5
E5
STPCLK#
LINT0
LINT1
SMI#
H_BR0#
B40
D8
H_IERR#
H_INIT#
LOCK#
N1
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
G5
K2
H4
K4
L1
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
H2
F2
H_HIT#
H_HITM#
AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
J7
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
CONTROL
H_BR0# <10>
H_INIT#
<23>
H_LOCK#
<10>
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
<10>
<10>
<10>
<10>
<10>
2
R56
1
56_0402_5%~D
+1.05V_VCCP
H_HIT#
<10>
H_HITM# <10>
R997
ITP_BPM#0
R998
ITP_BPM#1
R999
ITP_BPM#2
R1000
ITP_BPM#3
R1001
ITP_BPM#4
R1002
ITP_BPM#5
H_RESET#
R57
ITP_TDO
1
2 0_0402_5%~D ITP_BPM_R#0
1
2 0_0402_5%~D ITP_BPM_R#1
1
2 0_0402_5%~D ITP_BPM_R#2
1
2 0_0402_5%~D ITP_BPM_R#3
1
2 0_0402_5%~D ITP_BPM_R#4
1
1
2 0_0402_5%~D ITP_BPM_R#5
H_RESET_R#
2
ITP_TCK
124_0402_1%~D
CLK_CPU_ITP
<6> CLK_CPU_ITP
CLK_CPU_ITP#
<6> CLK_CPU_ITP#
1
2
R58
22.6_0402_1%~D
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
+1.05V_VCCP
GND6
M2
@
MOLEX_52435-2891_28P~D
C
R59
56_0402_5%~D
ITP_DBRESET# <24>
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
D38
BB34
BD34
B10
H_THERMDA
2
H_THERMDC
H_THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
+1.05V_VCCP
EC_CPU_PROCHOT#
THERMAL
A35
C35
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_THERMDA <18>
1
R61
+1.05V_VCCP
@ C18
100P_0402_50V8K~D
1
H_THERMDC <18>
H_THERMTRIP# <18>
CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>
+1.05V_VCCP
RESERVED
V2
Y2
AG5
AL5
J9
F4
H8
A20M#
FERR#
IGNNE#
BR0#
IERR#
INIT#
ITP_DBRESET#
H_DEFER# <10>
H_DRDY# <10>
H_DBSY# <10>
D
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
GND7
C7
D4
F10
H_DEFER#
H_DRD Y#
H_DBSY#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
H_A20M#
H_FERR#
H_IGNNE#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
N5
F38
J1
DEFER#
DRDY#
DBSY#
H_ADS# <10>
H_BNR# <10>
H_BPRI# <10>
1
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
2
H_THERMTRIP# should connect
to ICH9 and GMCH without
T-ing(no stub )
1
2
Place near JITP within 100mil
2 H_THERMTRIP#
56_0402_5%~D
H_RESET#
51_0402_1%~D
@ R1059
C20
0.1U_0402_16V4Z~D
H_STPCLK#
H_INTR
H_NMI
H_SMI#
AN1
AK4
AG1
AT4
AK2
AT2
AH2
AF4
AJ5
AH4
AM4
AP4
AR5
AJ1
AL1
AM2
AU5
AP2
AR1
AN5
H_ADS#
H_BNR#
H_BPRI#
C19
0.1U_0402_16V4Z~D
<23>
<23>
<23>
<23>
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
M4
J5
L5
ADS#
BNR#
BPRI#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
ICH
<23> H_A20M#
<23> H_FERR#
<23> H_IGNNE#
R1
R5
U1
P4
W5
ADDR GROUP 1
C
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
JITP1
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
2
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
P2
V4
W1
T4
AA1
AB4
T2
AC5
AD2
AD4
AA5
AE5
AB2
AC1
Y4
XDP/ITP SIGNALS
<10>
<10>
<10>
<10>
<10>
1
U62A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
ADDR GROUP 0
<10> H_ADSTB#0
2
+1.05V_VCCP
<10> H_A#[3..35]
D
3
29
4
30
5
1
R62
ITP_TDO
2
56_0402_5%~D
1
R64
ITP_TMS
2
39_0402_5%~D
1
R67
ITP_TCK
2
27_0402_5%
Place close to JITP within 200ps = 1000 mil
+3.3V_ALW_ICH
B
PENRYN SFF_UFCBGA956~D
Layout Note: for ITP700Flex debug port with a XDP based Run Control Tools
1
R60
ITP_DBRESET#
2
150_0402_5%~D
B
ITP_BPM#[0..5], TCK, and TMS routings
must be a maximum of 1.5ns = 7500 mil
Place close to JITP within 1ns = 5000 mil
+1.05V_VCCP
ITP_BPM#[0..5], and TCK to FBO routings
must be length matched to within 50ps = 250 mil
@ R977
ITP_BPM#5
51_0402_1%~D
Place close to CPU within 200 mil
Place R67 close to JITP pin 5
+1.05V_VCCP
TCK to FBO routing should refer to debug port design guide
H_RESET# should be routed from GMCH with split to ITP conn. Refer to DG page #56
Depop JITP, C19,C20,R62, R64, R67, R977, R65, R66
1
R65
ITP_TDI
2
150_0402_5%~D
1
R66
ITP_TRST#
2
649_0402_1%~D
when JIP connector is depopulated
Place close to CPU within 200ps = 1000 mil
A
A
5
4
3
2
Title
Penryn Processor(1/2)
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
7
of
57
5
4
3
2
1
+VCC_CORE
+VCC_CORE
U62C
D
<10> H_D#[0..63]
U62B
1
<10,23,45>
<23>
<10>
<23>
<10>
<45>
2
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
1
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PW RGOOD
H_CPUSLP#
H_PSI#
2
G7
B8
C41
E7
D10
BD10
1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
2
COMP0
COMP1
COMP2
COMP3
1
DATA GROUP 2
AE43
AD44
AE1
AF2
2
BSEL[0]
BSEL[1]
BSEL[2]
COMP[2]
COMP[3]
COMP[0]
MISC COMP[1]
R71
27.4_0402_1%~D
A37
C37
B38
H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DINV#3 <10>
R70
54.9_0402_1%~D
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
R69
27.4_0402_1%~D
PAD~D T138
AW43
E37
D40
C43
AE41
AY10
AC43
AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37
H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DINV#2 <10>
R68
54.9_0402_1%~D
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DATA GROUP 3
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30
VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016
J11
E11
G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37
VCCA[01]
VCCA[02]
D
+1.05V_VCCP
1
+
2
B34
D34
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
BD8
BC7
BB10
BB8
BC5
BB4
AY4
VCCSENSE
BD12
VCCSENSE
VSSSENSE
BC13
VSSSENSE
C
CRB was 270uF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
<45>
<45>
<45>
<45>
<45>
<45>
<45>
VCCSENSE
<45>
VSSSENSE
<45>
1
2
1
2
C23
10U_0805_10V4Z~D
P44
V40
V44
AB44
R41
W41
N43
U41
AA41
AB40
AD40
AC41
AA43
Y40
Y44
T44
U43
W43
R43
AP44
AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
C22
0.01U_0402_16V7K~D
+V_CPU_GTLREF
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
C21
220U_D2_4VY_R15M~D
<10> H_DSTBN#1
<10> H_DSTBP#1
<10> H_DINV#1
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GROUP 1
C
F40
G43
E43
J43
H40
H44
G39
E41
L41
K44
N41
T40
M40
G41
M44
L43
K40
J41
P40
DATA GROUP 0
<10> H_DSTBN#0
<10> H_DSTBP#0
<10> H_DINV#0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
F32
G33
H32
J33
K32
L33
M32
N33
P32
R33
T32
U33
V32
W33
Y32
AA33
AB32
AC33
AD32
AE33
AF32
AG33
AH32
AJ33
AK32
AL33
AM32
AN33
AP32
AR33
AT34
AT32
AU33
AV32
AY32
BB32
BD32
B28
B30
B26
D28
D30
F30
F28
H30
H28
D26
F26
H26
K30
K28
M30
M28
K26
M26
P30
P28
T30
T28
V30
V28
P26
T26
V26
Y30
Y28
AB30
+1.5V_RUN
Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.
B
TEST1
TEST2
FSB
BCLK
533
133
BSEL2
BSEL1
BSEL0
0
1
1
1
1
@ R833
1
R76
VSSSENSE
2
100_0402_1%~D
Reserve for testing
only
2
27.4_0402_1%~D
Route VCCSENSE and VSSSENSE trace at
27.4 ohms, 7 mils spacing and R75&R76
keep to pad max 1 inch
1
0
VCCSENSE
2
100_0402_1%~D
R77
1K_0402_1%~D
+V_CPU_GTLREF
2
166
0
1
R75
+1.05V_VCCP
@
667
VCCSENSE=18mils
+VCC_CORE
Place CAP close to the TEST4 pin
Make sure TEST4 routing is reference
to GND and away from other noisy signals.
800
200
0
1
0
1067
266
0
0
0
A
R78
2K_0402_1%~D
2
A
C1101
0.1U_0402_16V4Z~D
2
Place R75 and R76 near CPU
TEST3
TEST5
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
TEST4
1
B
1
2
1
1
@ R73
1K_0402_5%~D
@ R72
1K_0402_5%~D
2
PAD~D T2
PAD~D T3
Length match within 25 mils, Z0=27.4 ohm
Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)
5
4
3
2
Title
Penryn Processor(2/2)
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
8
of
57
5
4
3
2
1
U62E
D
C
+VCC_CORE
+1.05V_VCCP
U62F
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21
D
+VCC_CORE
Place these inside 1
socket cavity on L8
(North side
Secondary)
2
1
C24
10U_0805_4VAM~D
2
1
C25
10U_0805_4VAM~D
1
C26
10U_0805_4VAM~D
2
1
C27
10U_0805_4VAM~D
2
C28
10U_0805_4VAM~D
2
1
1
2
C29
10U_0805_4VAM~D
2
1
C30
10U_0805_4VAM~D
2
1
C31
10U_0805_4VAM~D
2
1
C32
10U_0805_4VAM~D
2
C33
10U_0805_4VAM~D
+VCC_CORE
socket cavity on L8
(Sorth side
Secondary)
2
1
C34
10U_0805_4VAM~D
2
1
C35
10U_0805_4VAM~D
1
C36
10U_0805_4VAM~D
2
1
C37
10U_0805_4VAM~D
2
C38
10U_0805_4VAM~D
2
1
1
2
C39
10U_0805_4VAM~D
2
1
C40
10U_0805_4VAM~D
2
1
C41
10U_0805_4VAM~D
2
1
C42
10U_0805_4VAM~D
2
C43
10U_0805_4VAM~D
+VCC_CORE
socket cavity on L8
(North side
Primary)
2
1
C44
10U_0805_4VAM~D
2
1
C45
10U_0805_4VAM~D
1
C46
10U_0805_4VAM~D
2
@
C48
10U_0805_4VAM~D
2
1
@
C49
10U_0805_4VAM~D
2
+VCC_CORE
socket cavity on L8
(Sorth side
Primary)
2
1
@
C50
10U_0805_4VAM~D
2
@
C51
10U_0805_4VAM~D
1
2
1
C52
10U_0805_4VAM~D
@
C53
10U_0805_4VAM~D
2
1
2
@
C54
10U_0805_4VAM~D
1
2
C
@
C55
10U_0805_4VAM~D
High Frequence Decoupling
+VCC_CORE
South Side Secondary
1
+
2
10uF 0805 X6S -> 85 degree C
1
+
2
1
+
2
C58
270U_D_2VM_R4.5M~D
B42
F44
D44
D42
F42
H42
K42
M42
P42
T42
V42
Y42
AB42
AD42
AF42
AH42
AK42
AM42
AP42
AY44
AV44
AT42
AV42
AY42
BA43
BB42
C39
E39
G37
H38
J39
L39
M38
N39
R39
T38
U39
W39
Y38
AA39
AC39
AD38
AE39
AG39
AH38
AJ39
AL39
AM38
AN39
AR39
AR37
AT38
AU39
AU37
AW39
AW37
BA39
BC41
BD40
BD38
B36
H34
D36
K34
M34
M36
P34
T34
V34
T36
Y34
AB34
AD34
Y36
AD36
AF34
AH34
AH36
AK34
AM34
AP34
C57
270U_D_2VM_R4.5M~D
+1.05V_VCCP
1
2
1
C62
0.1U_0402_10V7K~D
1
C63
0.1U_0402_10V7K~D
2
2
1
C64
0.1U_0402_10V7K~D
2
1
C65
0.1U_0402_10V7K~D
1
C66
0.1U_0402_10V7K~D
2
Place these inside
socket cavity on L8
(North side
Secondary)
C67
0.1U_0402_10V7K~D
2
B
+VCC_CORE
2
1
@
2
1
@
2
1
@
2
1
@
2
1
@
2
1
@
2
1
C1185
1U_0402_6.3V6K~D
1
@
C1184
1U_0402_6.3V6K~D
2
C1183
1U_0402_6.3V6K~D
1
@
C1182
1U_0402_6.3V6K~D
2
C1181
1U_0402_6.3V6K~D
1
@
C1180
1U_0402_6.3V6K~D
2
C1179
1U_0402_6.3V6K~D
High Frequence CAP for ULV CPU
@
+VCC_CORE
@
2
1
@
2
1
@
2
1
@
2
1
@
2
1
@
2
1
@
2
1
1
@
2
1
@
2
1
C1189
1U_0402_6.3V6K~D
1
2
C1188
1U_0402_6.3V6K~D
2
C1199
1U_0402_6.3V6K~D
@
C1198
1U_0402_6.3V6K~D
1
C1197
1U_0402_6.3V6K~D
2
C1196
1U_0402_6.3V6K~D
@
C1195
1U_0402_6.3V6K~D
1
C1194
1U_0402_6.3V6K~D
2
@
C1187
1U_0402_6.3V6K~D
1
C1186
1U_0402_6.3V6K~D
2
+VCC_CORE
C1193
1U_0402_6.3V6K~D
VCCP_017
VCCP_018
VCCP_019
VCCP_020
AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
AJ35
AF36
AL35
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
W13
W11
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
AU11
L9
L7
N9
N7
R9
R7
U9
U7
W9
W7
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13
C1192
1U_0402_6.3V6K~D
AF38
AG37
AJ37
AK38
A
U62D
VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
VCCP_039
VCCP_040
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCCP_047
VCCP_048
VCCP_049
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCCP_082
VCCP_083
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCCP_116
VCCP_117
VCCP_118
VCCP_119
VCCP_120
VCCP_121
VCCP_122
VCCP_123
VCCP_124
VCCP_125
VCCP_126
VCCP_127
VCCP_128
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145
C1178
1U_0402_6.3V6K~D
+1.05V_VCCP
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCC_176
VCC_177
VCC_178
VCC_179
VCC_180
VCC_181
VCC_182
VCC_183
VCC_184
VCC_185
VCC_186
VCC_187
VCC_188
VCC_189
VCC_190
VCC_191
VCC_192
VCC_193
VCC_194
VCC_195
VCC_196
VCC_197
VCC_198
VCC_199
VCC_200
VCC_201
VCC_202
VCC_203
VCC_204
VCC_205
VCC_206
VCC_207
VCC_208
VCC_209
VCC_210
VCC_211
VCC_212
VCC_213
VCC_214
VCC_215
VCC_216
VCC_217
VCC_218
VCC_219
VCC_220
C1191
1U_0402_6.3V6K~D
BD28
BB26
BD26
B22
B24
D22
D24
F24
F22
H24
H22
K24
K22
M24
M22
P24
P22
T24
T22
V24
V22
Y24
Y22
AB24
AB22
AD24
AD22
AF24
AF22
AH24
AH22
AK24
AK22
AM24
AM22
AP24
AP22
AT24
AT22
AV24
AV22
AY24
AY22
BB24
BB22
BD24
BD22
B16
B18
B20
D16
D18
F18
F16
H18
H16
D20
F20
H20
K18
K16
M18
M16
K20
M20
P18
P16
T18
T16
V18
V16
P20
T20
V20
Y18
Y16
AB18
AB16
AD18
AD16
Y20
AB20
AD20
AF18
AF16
AH18
AH16
AF20
AH20
AK18
AK16
AM18
AM16
AP18
AP16
AK20
AM20
AP20
AT18
AT16
AV18
AV16
AY18
AY16
AT20
AV20
AY20
BB18
BB16
BD18
BD16
BB20
BD20
AM14
AP14
AT14
AV14
AY14
BB14
BD14
C1177
1U_0402_6.3V6K~D
AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4
C1190
1U_0402_6.3V6K~D
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
C1176
1U_0402_6.3V6K~D
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
C56
270U_D_2VM_R4.5M~D
B
G25
G23
G21
J25
J23
J21
L25
L23
L21
N25
N23
N21
R25
R23
R21
U25
U23
U21
W25
W23
W21
AA25
AA23
AA21
AC25
AC23
AC21
AE25
AE23
AE21
AG25
AG23
AG21
AJ25
AJ23
AJ21
AL25
AL23
AL21
AN25
AN23
AN21
AR25
AR23
AR21
AU25
AU23
AU21
AW25
AW23
AW21
BA25
BA23
BA21
BC25
BC23
BC21
C17
C19
E19
E17
G19
G17
J19
J17
L19
L17
N19
N17
R19
R17
U19
U17
W19
W17
AA19
AA17
AC19
AC17
AE19
AE17
AG19
AG17
AJ19
AJ17
AL19
AL17
AN19
AN17
AR19
AR17
AU19
AU17
AW19
AW17
BA19
BA17
BC19
BC17
C11
C15
E15
G15
H10
M12
J15
L15
N15
M10
T12
R15
U15
W15
T10
Y12
AD12
@
@
A
Title
CPU Bypass
Size
Document Number
Date:
Rev
1.0
LA-4151P
5
4
3
2
Sheet
1
9
of
57
5
4
3
2
1
U78B
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
J13
L13
C13
G13
G15
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_AVREF
H_DVREF
B42
D42
B50
D50
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
R49
P50
PEG_CLK
PEG_CLK#
AG55
AL49
AH54
AL47
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
AG53
AK50
AH52
AL45
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
AG49
AJ49
AJ47
AG47
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
AF50
AH50
AJ45
AG45
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
<7>
<7>
<7>
<7>
<7>
<47>
<47>
<47>
<47>
<47>
<47> GFX_VR_ON
+1.05V_M
<7>
<7>
<7>
1
2
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
<24> CL_CLK0
<24> CL_DATA0
<24,34> ICH_CL_PWROK
<24> CL_RST0#
<21>
<21>
<21>
<21>
G33
G37
F38
F36
G35
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_ON
G39
GFX_VR_EN
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF
AK52
AK54
AW40
AL53
AL55
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#
F34
F32
B38
A37
C31
K42
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
MCH_TSATN#
D10
TSATN#
ICH_AZ_MCH_BITCLK
ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDIN2
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC
ICH_AZ_MCH_BITCLK
ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDIN2
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC
R685 1
2 33_0402_5%~D ICH_AZ_MCH_SDIN2_R
C29
B30
D28
A27
B28
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
1
2
C
2
MCH_TSATN#
3
1
2 2
B
R104
E
330_0402_5%~D
Q4
MMST3904-7-F_SOT323-3~D
5
1 2
1
R101
54.9_0402_1%~D
HD support 1.5V
ME_JTAG_TCK
1
ME_JTAG_TDI @ R804 1
ME_JTAG_TDO @ R805 1
ME_JTAG_TMS @ R806 1
@ R807
MCH_TSATN_EC <33>
THERMTRIP_MCH#
PLTRST1#_R
C
2
B
1
R102
2
R100
2
56_0402_5%~D
1
100_0402_5%~D
C1108 1
R946 12K_0402_5%~D
SM_PWROK 1
2 4 O
IN1
1
IN2
R947
10K_0402_5%~D
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
T123
T124
T125
T126
PAD~D
PAD~D
PAD~D
PAD~D
SIO_SLP_S4#
2 0.1U_0402_16V4Z~D
1DDR_ ON
@ R1007 1
2 1.5V_POK1
DDR_ON
<34,36,44>
2 0_0402_5%~D
1.5V_POK1
<34,43>
U80
74AHC1G08GW_SOT353-5~D
C
K26
G23
G25
J25
L25
L27
F24
D24
D26
J23
B26
A23
C23
B24
B22
K24
C25
L23
L33
K32
K34
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
J35
F6
J39
L39
AY39
BB18
K28
K36
PM_SYNC#
H_DPRSTP#
PM_EXTTS#0
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T14 PAD~D
T15 PAD~D
CFG5
<12>
CFG6
<12>
CFG7
<12>
T16 PAD~D
CFG9
<12>
CFG10
<12>
T18 PAD~D
CFG12
<12>
CFG13
<12>
T21 PAD~D
T22 PAD~D
CFG16
<12>
T23 PAD~D
T24 PAD~D
CFG19
<12>
CFG20
<12>
CFG5
CFG6
CFG7
CFG9
CFG10
CFG12
CFG13
CFG16
CFG19
CFG20
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
PM_SYNC#
<24>
H_DPRSTP# <8,23,45>
PM_EXTTS#0 <16,17,18>
I CH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
A7
A49
A52
A54
B54
D55
G55
BE55
BH55
BK55
BK54
BL54
BL52
BL49
BL7
BL4
BL2
BK2
BK1
BH1
BE1
G1
Notes refer
page 12
ICH_PWRGD <24,37>
THERMTRIP_MCH# <18>
DPRSLPVR
<24,45>
2
R84
+3.3V_RUN
+1.5V_MEM
R88
1K_0402_1%~D
SMRCOMP_VOH
1
+3.3V_RUN
R93
3.01K_0402_1%~D
R156
30K_0402_5%~D
GFX_VR_ON
2
1
2
SMRCOMP_VOL
R97
1K_0402_1%~D
R157
100K_0402_5%~D
1
2
1
2
A
<22,28>
E
Q3
MMST3904-7-F_SOT323-3~D
4
3
2
B
1
10K_0402_5%~D
+1.05V_VCCP
PLTRST1#
2
2 100_0402_5%~D
2 100_0402_5%~D
2 100_0402_5%~D
100_0402_5%~D
+3.3V_ALW_ICH
<24,34> SIO_SLP_S4#
CANTIGA GMCH SFF_FCBGA1363~D
3
1
1
1
2
1
C74
0.1U_0402_16V4Z~D
R95
100_0402_1%~D
2
AN45
AP44
AT44
AN47
C76
2.2U_0603_6.3V6K~D
H_SWNG
R99
1K_0402_5%~D
+1.05V_VCCP
R98
1K_0402_5%~D
R91
221_0402_1%~D
2
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
PAD~D
PAD~D
PAD~D
PAD~D
C75
0.01U_0402_16V7K~D
<23>
<23>
<23>
<23>
<23>
+3.3V_RUN
1
T10
T11
T12
T159
@
+1.05V_VCCP
A
TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25
HDA
1
2
2
C73
0.1U_0402_16V4Z~D
R94
2K_0402_1%~D
BB20
BE19
BF20
BF18
PM_EXTTS#0
+H_VREF
1
RSVD22
RSVD23
RSVD24
RSVD25
PAD~D
C72
2.2U_0603_6.3V6K~D
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
<6> CLK_3GPLLREQ#
<24> MCH_ICH_SYNC#
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
T9
2
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
TP_MCH_RSVD20
5
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#
AW42
D
P
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
RSVD20
G
SM_RCOMP_VOH
SM_RCOMP_VOL
+V_DDR_MCH_REF BC51
SM_PWROK
AY37
499_0402_1%~D
BH20
SM_DRAMRST#
BA37
PAD~D
3
BK32
BL31
T8
C71
0.01U_0402_16V7K~D
2
SM_RCOMP
SM_RCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
TP_MCH_RSVD17
NC
R90
1K_0402_1%~D
BL25
BK26
<8>
<8>
<8>
<8>
1
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
SMRCOMP
SMRCOMP#
J9
1
<8>
<8>
<8>
<8>
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
RSVD17
2
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
<24>
<24>
<24>
<24>
BJ17
BJ19
BC17
BE17
PAD~D
PAD~D
1
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
M_ODT0
M_ODT1
M_ODT2
M_ODT3
T158
T6
2
L3
M2
Y2
AF2
<24>
<24>
<24>
<24>
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
TP_MCH_RSVD14
TP_MCH_RSVD15
1
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
BK18
BK16
BE23
BC19
C27
D30
2
<8>
<8>
<8>
<8>
<24>
<24>
<24>
<24>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
RSVD14
RSVD15
1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
2
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
<24>
<24>
<24>
<24>
BC35
BE33
BE37
BC37
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
1
<6> MCH_DREFCLK
<6> MCH_DREFCLK#
<6> DREF_SSCLK
<6> DREF_SSCLK#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
T150
T151
T152
T153
T154
T155
T156
T157
T5
CLK
1
2
<16,17> SM_DRAMRST#
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
TP_MCH_RSVD1
TP_MCH_RSVD2
TP_MCH_RSVD3
TP_MCH_RSVD4
TP_MCH_RSVD5
TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8
TP_MCH_RSVD9
2
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
K2
N3
AA3
AF4
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
1
2
R81
H_ADS#
<7>
H_ADSTB#0
<7>
H_ADSTB#1
<7>
H_BNR#
<7>
H_BPRI#
<7>
H_BR0#
<7>
H_DEFER#
<7>
H_DBSY#
<7>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
H_DPWR#
<8>
H_DRDY#
<7>
H_HIT#
<7>
H_HITM# <7>
H_LOCK# <7>
H_TRDY#
<7>
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_RS#0
H_RS#1
H_RS#2
1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
<6> CLK_MCH_3GPLL
<6> CLK_MCH_3GPLL#
L9
N7
AA7
AG3
F4
F2
G7
<16>
<16>
<17>
<17>
BA31
BC25
BC33
BB24
J43
L43
J41
L41
AN11
AM10
AK10
AL11
F12
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
DMI
2
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_RS#_0
H_RS#_1
H_RS#_2
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
GRAPHICS VID
+H_VREF
L17
K18
+1.05V_VCCP
H_CPURST#
H_CPUSLP#
1
C70
0.1U_0402_16V4Z~D
J11
G9
+V_DDR_MCH_REF
R87
510_0402_5%~D
H_RESET#
H_CPUSLP#
<16>
<16>
<17>
<17>
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
ME
<7>
H_RESET#
<8> H_CPUSLP#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
SMRCOMP
1
80.6_0402_1%~D
SMRCOMP#
1
80.6_0402_1%~D
2
R79
2
R80
R83
1K_0402_1%~D
B
<16>
<16>
<17>
<17>
+1.5V_MEM
2
H_SWING
H_RCOMP
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPW R#
H_D RDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
BB32
BA25
BA33
BA23
PM
B6
D4
F10
A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8
<7>
<16>
<16>
<17>
<17>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
CFG
2
24.9_0402_1%~D
H_SWNG
+H_RCOMP
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
C69
0.1U_0402_16V4Z~D
C
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
L15
B14
C15
D12
F14
G17
B12
J15
D16
C17
D14
K16
F16
B16
C21
D18
J19
J21
B18
D22
G19
J17
L21
L19
G21
D20
K22
F18
K20
F20
F22
B20
A19
1
D
J7
H6
L11
J3
H4
G3
K10
K12
L1
M10
M6
N11
L7
K6
M4
K4
P6
W9
V6
V2
P10
W7
N9
P4
U9
V4
U1
W3
V10
U7
W11
U11
AC11
AC9
Y4
Y10
AB6
AA9
AB10
AA1
AC3
AC7
AD12
AB4
Y6
AD10
AA11
AB2
AD4
AE7
AD2
AD6
AE3
AG9
AG7
AE11
AK6
AF6
AJ9
AH6
AF12
AH4
AJ7
AE9
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
C68
0.1U_0402_16V4Z~D
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1
R82
H_A#[3..35]
U78A
H_D#[0..63]
HOST
<8>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
RSVD
Place close to U78.
F34,F32,B38,A37
<16>
<16>
<17>
<17>
MISC
1 SDVO_CTRLCLK
2.2K_0402_5%~D
1 SDVO_CTRLDATA
2.2K_0402_5%~D
1 DDPC_CTRLCLK
2.2K_0402_5%~D
1 DDPC_CTRLDATA
2.2K_0402_5%~D
2
2
R180
2
R181
2
R182
2
R183
DDR CLK/ CONTROL/COMPENSATION
+3.3V_RUN
Title
Cantiga(1 of 6)
Size
Document Number
Date:
Re v
1.0
LA-4151P
Sheet
1
10
of
57
4
3
SA_BS_0
SA_BS_1
SA_BS_2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
BH22
BK20
BL15
SA_RAS#
SA_CAS#
SA_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AT50
BB50
BB46
BE39
BB12
BE7
AV10
AR9
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
C
<16> DDR_A_MA[0..14]
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
B
BC23
BF22
BE31
BC31
BH26
BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
MEMORY
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SYSTEM
<16> DDR_A_DQS#[0..7]
DDR_A_DQS0
AR47
DDR_A_DQS1
BA45
DDR_A_DQS2
BE45
DDR_A_DQS3
BC41
DDR_A_DQS4
BC13
DDR_A_DQS5
BB10
DDR_A_DQS6
BA7
DDR_A_DQS7
AN7
DDR_A_DQS#0 AR49
DDR_A_DQS#1 AW45
DDR_A_DQS#2 BC45
DDR_A_DQS#3 BA41
DDR_A_DQS#4 BA13
DDR_A_DQS#5 BA11
DDR_A_DQS#6
BA9
DDR_A_DQS#7
AN9
DDR
<16> DDR_A_DQS[0..7]
A
<16> DDR_A_DM[0..7]
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
AP46
AU47
AT46
AU49
AR45
AN49
AV50
AP50
AW47
BD50
AW49
BA49
BC49
AV46
BA47
AY50
BF46
BC47
BF50
BF48
BC43
BE49
BA43
BE47
BF42
BC39
BF44
BF40
BB40
BE43
BF38
BE41
BA15
BE11
BE15
BF14
BB14
BC15
BE13
BF16
BF10
BC11
BF8
BG7
BC7
BC9
BD6
BF12
AV6
BB6
AW7
AY6
AT10
AW11
AU11
AW9
AR11
AT6
AP6
AL7
AR7
AT12
AM6
AU7
<17> DDR_B_BS0
<17> DDR_B_BS1
<17> DDR_B_BS2
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
<17> DDR_B_RAS#
<17> DDR_B_CAS#
<17> DDR_B_WE#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
BJ13
BK12
BK38
SB_BS_0
SB_BS_1
SB_BS_2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
BE21
BH14
BK14
SB_RAS#
SB_CAS#
SB_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
AP52
AY54
BJ49
BJ43
BH12
BD2
AY2
AJ3
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AR53
BA53
BH50
BK42
BH8
BB2
AV2
AM2
AT54
BB54
BJ51
BH42
BK8
BC3
AW3
AN3
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
BJ15
BJ33
BH24
BA17
BF36
BH36
BF34
BK34
BJ37
BH40
BH16
BK36
BH38
BJ11
BL37
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
<17> DDR_B_DM[0..7]
<17> DDR_B_DQS[0..7]
<17> DDR_B_DQS#[0..7]
<17> DDR_B_MA[0..14]
B
BC21
BJ21
BJ41
MEMORY
<16> DDR_A_RAS#
<16> DDR_A_CAS#
<16> DDR_A_WE#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
SYSTEM
<16> DDR_A_BS0
<16> DDR_A_BS1
<16> DDR_A_BS2
1
DDR_B_D[0..63] <17>
U78E
DDR_A_D[0..63] <16>
U78D
D
2
DDR
5
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AP54
AM52
AR55
AV54
AM54
AN53
AT52
AU53
AW53
AY52
BB52
BC53
AV52
AW55
BD52
BC55
BF54
BE51
BH48
BK48
BE53
BH52
BK46
BJ47
BL45
BJ45
BL41
BH44
BH46
BK44
BK40
BJ39
BK10
BH10
BK6
BH6
BJ9
BL11
BG5
BJ5
BG3
BF4
BD4
BA3
BE5
BF2
BB4
AY4
BA1
AP2
AU1
AT2
AT4
AV4
AU3
AR3
AN1
AP4
AL3
AJ1
AK4
AM4
AH2
AK2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
D
C
B
A
A
Title
Cantiga(2 of 6)
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
11
of
57
5
4
3
2
1
+VCC_PEG
2
Strap Pin Table
U78C
R105
49.9_0402_1%~D
@ R1011
1
Apply CIS
BIA_PWM
PANEL_BKEN_MCH
L_CTRL_CLK
D38
C37
K38
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
2 10K_0402_5%~D
<39> LDDC_CLK_MCH
<39> LDDC_DATA_MCH
L_CTRL_DATA
LDDC_CLK_MCH
LDDC_DATA_MCH
L37
J37
L35
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
<19>
1
R688
ENVDD
ENVDD
L_IBG
2
2.4K_0402_1%~D
The value is recommended per Intel
LCD_ACLK-_MCH
LCD_ACLK+_MCH
LCD_A0-_MCH
LCD_A1-_MCH
LCD_A2-_MCH
<40> LCD_A0-_MCH
<40> LCD_A1-_MCH
<40> LCD_A2-_MCH
LCD_A0+_MCH
LCD_A1+_MCH
LCD_A2+_MCH
<40> LCD_A0+_MCH
<40> LCD_A1+_MCH
<40> LCD_A2+_MCH
CRT_RED
CRT_HSYNC
Apply CIS
<20> CRT_VSYNC
CRT_VSYNC
1
R480
2
R672
1
R673
1
2
1
2
2
CRT_GRN
<20>
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
F44
G47
F40
A45
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
B40
A41
F42
D48
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
D40
C41
G43
B48
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
J27
E27
G27
TVA_DAC
TVB_DAC
TVC_DAC
F26
TVA_RTN
B34
D34
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLU
J29
CRT_BLUE
CRT_GRN
G29
CRT_GREEN
CRT_RED
F30
CRT_RED
E29
CRT_IRTN
G_CLK_DDC2
G_DAT_DDC2
2 CRT_HSYNC_R
30_0402_1%~D
1 CRT_IREF
976_0402_1%~D
2CRT_VSYNC_R
30_0402_1%~D
D36
C35
J33
D32
G31
VGA
<20>
G45
F46
G41
C45
TV
CRT_BLU
R1105 75_0402_5%~D
<20> CRT_HSYNC
<20>
R1106 75_0402_5%~D
B
R1107 75_0402_5%~D
1
C
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDS
<40> LCD_ACLK-_MCH
<40> LCD_ACLK+_MCH
B36
F50
H46
P44
K46
D46
B46
D44
B44
GRAPHICS
@R1010 1
<19> BIA_PWM
<33> PANEL_BKEN_MCH
2 10K_0402_5%~D
PCI-EXPRESS
D
Low = DMI x 2
DMI X2 Select
CFG6
iTPM Host
Interface
Low = iTPM enable
Low = TLS cipher suite with no confidentiality
CFG7
Management
Engine Crypto
Strap
CFG9
PCI Express
Graphic Lane
CFG16
FSB Dynamic
ODT
Low=Dynamic ODT Disable
CFG19
DMI Lane
Reversal
Low=Normal (default)
CFG20
SDVO/PCIE
Concurrent
Operation
Low=Only SDVO or PCIEx1 is
operational (default)
High=SDVO and PCIEx1 are operating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Device Present
High = DMI x 4 (Default)
1
+3.3V_RUN
CFG5
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
PEGCOMP
PEG_COMPI
PEG_COMPO
U45
T44
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54
DPB_LANE_N0 C716
DPB_LANE_N1 C717
DPB_LANE_N2 C718
DPB_LANE_N3 C719
DPC_LANE_N0 C720
DPC_LANE_N1 C721
DPC_LANE_N2 C722
DPC_LANE_N3 C723
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52
DPB_LANE_P0
DPB_LANE_P1
DPB_LANE_P2
DPB_LANE_P3
DPC_LANE_P0
DPC_LANE_P1
DPC_LANE_P2
DPC_LANE_P3
DPB_AUX#
DPB_AUX#
DPC_DOCK_AUX#
<21>
DPC_DOCK_AUX# <21>
DPB_AUX
DPB_HPD#
DPB_AUX
DPB_HPD#
DPC_DOCK_AUX
DPC_DOCK_HPD#
<21>
<21>
DPC_DOCK_AUX <21>
DPC_DOCK_HPD# <21>
SDVO_CRTL_DATA
DDPC_CTRLDATA
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DPB_LANE_N0_C
DPB_LANE_N1_C
DPB_LANE_N2_C
DPB_LANE_N3_C
DPC_LANE_N0_C
DPC_LANE_N1_C
DPC_LANE_N2_C
DPC_LANE_N3_C
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
High = iTPM disable(Defult)
D
High = TLS cipher suite with
confidentiality(Default)
Low = Reverse Lane
High = Normal Operation(Default)
High=Dynamic ODT Enable(default)
High=Lane Reversed
Low=DisplayPort disabled (default)
C
High=DisplayPort device present
XOR/ALLZ/Clock Un-gating
CG13
CG12
0
0
configuration
Reserved
1
0
XOR Mode Enabled
0
1
All-Z Mode Enabled
1
1
Normal Operation(default)
CG10(PCIE Loopback enable)
C724
C725
C726
C727
C728
C729
C730
C731
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
Low= Enables
High= Disable(default)
DPB_LANE_P0_C
DPB_LANE_P1_C
DPB_LANE_P2_C
DPB_LANE_P3_C
DPC_LANE_P0_C
DPC_LANE_P1_C
DPC_LANE_P2_C
DPC_LANE_P3_C
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<10>
CFG5
<10>
CFG6
<10>
CFG7
<10>
CFG9
<10>
CFG16
<10>
CFG10
<10>
CFG12
<10>
CFG13
CFG5
@ R106
CFG6
@ R107
CFG7
@ R108
CFG9
@ R109
CFG16
@ R110
1
2 2.21K_0402_1%~D
1
2 2.21K_0402_1%~D
1
2 2.21K_0402_1%~D
1
2 2.21K_0402_1%~D
1
2 2.21K_0402_1%~D
B
CFG[5:16] have internal pullup
CFG10 1
@ R979
CFG12 1
@ R980
CFG13 1
@ R981
2 2.21K_0402_1%~D
CFG19 1
@ R111
CFG20 1
@ R112
2 4.02K_0402_1%~D
2 2.21K_0402_1%~D
2 2.21K_0402_1%~D
1
1
+3.3V_RUN
+3.3V_RUN
G_CLK_DDC2
6
2
1
CLK_DDC2
<10>
CFG19
<10>
CFG20
2 4.02K_0402_1%~D
CLK_DDC2 <20>
Q123A
2N7002DW-T/R7_SOT363-6~D
CFG[19:20] have internal pulldown
+3.3V_RUN
5
1
R679
1
R680
1
R681
1
R682
CRT_BLU
2
150_0402_1%~D
CRT_GRN
2
150_0402_1%~D
CRT_RED
2
150_0402_1%~D
ENVDD
2
100K_0402_5%~D
R676
2.2K_0402_5%~D
1
2
@ R860
0_0402_5%~D
2
2
R675
2.2K_0402_5%~D
A
G_DAT_DDC2
4
1
@ R861
Q123B
2N7002DW-T/R7_SOT363-6~D
DAT_DDC2
3
A
DAT_DDC2 <20>
2
0_0402_5%~D
Title
Cantiga(3 of 6)
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
12
of
57
5
4
+1.05V_VCCP
3
2
1
U78H
CRB 270uF
CRT
PLL
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_NCTF_3
VCCA_SM_NCTF_4
VCCA_SM_NCTF_5
VCCA_SM_NCTF_6
VCCA_SM_NCTF_7
VCCA_SM_NCTF_8
VCCA_SM_NCTF_9
VCCA_SM_NCTF_10
AT24
AR24
AT22
AR22
AT21
AR21
AT19
AR19
AT18
AR18
A SM
AXF
SM CK
HV
PEG
1
2
C117
0.1U_0402_16V4Z~D
1
2
1
2
AH12
VCCD_PEG_PLL
AE43
2
DMI
1
2
1
2
1
+1.05V_M
1
2
2
0_1210_5%~D
2
+1.05V_M_PEGPLL
M46
L45
2
1
2
+1.05V_M_MPLL
+1.05V_M
L4
2
1
BLM18AG121SN1D_0603~D
1
2
139.2mA Max.
1
2
+
2
+1.05V_M
2
+1.05V_M_DPLLB
64.8mA Max.
1
2
1
L5
LQH32CNR15M33L_1210~D
R120
0_0603_5%~D
C
+1.05V_MPLL
1
2
+1.05V_M
L45
1
2
10UH_LB2012T100MR_20%_0805~D
1
Rating current 125mA
C133
22U_0805_6.3VAM~D
+1.05V_M
L46
1
2
10UH_LB2012T100MR_20%_0805~D
1
Rating current
+
2
125mA
B
+1.5V_MEM
1
LVDS
VTTLF
1
+1.05V_M_DPLLA
+1.05V_M
VCCD_LVDS_1
VCCD_LVDS_2
+1.05V_M_HPLL
24mA Max.
+1.8V_RUN_LVDS @
PJP61
1
+1.5V_SM_CK
2
1
L7
LQM21FN1R0N00 _0805~D
Rdc=0.1~0.2,rated
current=220mA(MAX)
C147
10U_0805_4VAM~D
2
1+1.5V_SM_CKG
1
2
+1.8V_RUN
2
+VCC_TX_LVDS
2
1
L47
HK1608R10J-T_0603~D
PAD-OPEN 1x1m
1
2
1
2
22U_0805_6.3V6M~D
C745
VCCD_HPLL
+
64.8mA Max.
1
R119
2
C744
1000P_0402_50V7K~D
AU27
AU28
AU29
AU31
AT31
AR31
AT29
AR29
AT28
AR28
AT27
AR27
2
1
2
+1.05V_M_SM_CK
VCCA_SM_CK_4
VCCA_SM_CK_3
VCCA_SM_CK_2
VCCA_SM_CK_1
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
2
0_0805_5%~D
1
2
1
+1.05V_M
R116
+1.05V_M_A_SM 1
C146
0.1U_0402_16V4Z~D
2
2
R121
1_0603_5%~D
2
1
+1.8V_RUN
60.31mA Max.
1
2
C743
1U_0603_10V4Z~D
C144
0.47U_0402_10V4Z~D
1
C143
0.47U_0402_10V4Z~D
2
C142
0.47U_0402_10V4Z~D
1
VTTLF1
VTTLF2
VTTLF3
+1.05V_M_PEGPLL
2
1
C740
220U_D2_4VY_R15M~D
AW24
AU24
AW22
AU22
AU21
AW20
AU19
AW18
AU18
AW16
AU16
AT16
AR16
AU15
AT15
AR15
AW14
+3.3V_RUN
1
1_0402_5%~D
C742
0.1U_0402_16V4Z~D
AG43
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_12
VCCA_SM_13
VCCA_SM_14
VCCA_SM_15
VCCA_SM_16
VCCA_SM_17
+1.5V_RUN
+1.5V_RUN
2
1
L44
BLM18PG181SN1_0603~D
C132
0.1U_0402_16V4Z~D
VCCA_PEG_PLL
2
0_0402_5%~D
2
0_0402_5%~D
C140
0.1U_0402_16V4Z~D
GMCH_VTTLF1 K14
GMCH_VTTLF2 Y12
GMCH_VTTLF3 P2
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
D
2
2
1
C141
0.1U_0402_16V4Z~D
C137
0.1U_0402_16V4Z~D
AM44
AN43
AL43
1
R778
1
@ R779
C739
220U_D2_4VY_R15M~D
+VCC_DMI
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
+
C131
4.7U_0603_6.3V6M~D
C136
0.1U_0402_16V4Z~D
AB44
Y44
AC43
AA43
+VCC_PEG
+VCCA_PEG_BG
C741
0.1U_0402_16V4Z~D
VCC_HV_1
VCC_HV_2
1
+1.05V_VCCP
Follow ERB,CRB option
@ C145
to select +1.05V_M or 220U_D2_4VY_R15M~D
+1.05V_VCCP
1
VCCA_PEG_BG
AJ43
C118
10U_0805_4VAM~D
2
1 +1.05V_MPEG
R117
C130
0.1U_0402_16V4Z~D
C33
A33
2
+1.05V_M_PEGPLL
L3
BLM21PG221SN1D_0805~D
1
2
1
A PEG A LVDS
TV
D TV/CRT HDA
2
C120
100U_D2E_6.3VM_R15M~D
VCC_TX_LVDS
+1.05V_M
1
@ C129
2.2U_0603_6.3V6K~D
T41
V44
C128
22U_0805_6.3V6M~D
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
VSSA_LVDS
+VCC_TX_LVDS
C127
0.1U_0402_16V4Z~D
BK24
BL23
BJ23
BK22
U43
U41
@ C124
22U_0805_6.3V6M~D
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCCA_LVDS1
VCCA_LVDS2
C123
22U_0805_6.3V6M~D
M25
N24
M23
1
+VCC_PEG
PJP1
PAD-OPEN1x1m
2
1
+1.05V_M
@ L6
LBC2518T91NM_1210~D
+VCC_TX_LVDS
13.2mA Max.
C122
4.7U_0603_6.3V6M~D
+VCC_TX_LVDS
2
+1.05V_M_MPLL
2
VTT
VCCD_TVDAC
118.8mA Max.
1
+1.05V_M_HPLL
2
2
1
@ R115
0_1210_5%~D
C738
0.1U_0402_16V4Z~D
VCCD_QDAC
+1.5V_SM_CK
B
AF10
AE1
C121
1U_0603_10V4Z~D
2
C126
1U_0603_10V4Z~D
@ C125
10U_0805_4VAM~D
+VCC_AXF
1
0_1210_5%~D
1
1
2
VCCA_HPLL
VCCA_MPLL
2
2
1
C737
0.01U_0402_25V7K~D
N34
+1.05V_M
1
+1.05V_M_DPLLB
2
1
C119
0.1U_0402_16V4Z~D
VCC_HDA
2
C
+3.3V_RUN
VCCA_DPLLB
L49
+
2
+1.05V_M
+1.5V_RUN_QDAC
POWER
2
+1.05V_M_DPLLA
2
1
1
2
R114
0_1210_5%~D
C113
22U_0805_6.3V6M~D
A31
N32
2
R118
J45
2
+VCC_DMI
C112
4.7U_0603_6.3V6M~D
VCCA_TV_DAC
VCCA_DPLLA
1
Rating current 125mA
C736
1000P_0402_50V7K~D
1
C998
+1.5V_RUN_QDAC
1
1
+VCC_PEG
C111
220U_D2_4VY_R15M~D
2
K30
1
L31
M33
C733
0.1U_0402_16V4Z~D
+1.5V_RUN
0.1U_0402_16V4Z~D
2
1
+3.3V_CRT_DAC
VCCA_DAC_BG
VSSA_DAC_BG
+3.3V_RUN
L43
1
2
10UH_LB2012T100MR_20%_0805~D
+3.3V_CRT_DAC
J31
C732
0.01U_0402_25V7K~D
1
C116
2.2U_0603_6.3V6K~D
2
C115
4.7U_0603_6.3V6M~D
C114
4.7U_0603_6.3V6M~D
1
+3.3V_CRT_DAC
VCCA_CRT_DAC
C735
0.1U_0402_16V4Z~D
D
2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
C734
0.01U_0402_25V7K~D
2
1
C110
0.47U_0402_10V4Z~D
+
C109
220U_D2_4VY_R15M~D
1
R13
T12
R11
T10
R9
T8
R7
T6
R5
T4
R3
T2
R1
+1.05V_VCCP
+3.3V_RUN
2
1+VCCPRUN 1
2
@ D1
RB751V_SOD323-2~D
@ R122
10_0603_5%~D
Follow CRB to
VCC_HV(C33,A33)
A
A
Title
Cantiga(4 of 6)
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
13
of
57
5
4
3
2
1
U78G
+VCC_GFXCORE
2
Layout Note:
Place close to GMCH
2
1
2
C156
0.1U_0402_10V7K~D
1
Layout Note:
Inside GMCH cavity.
VCC GFX
VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80
AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15
AJ40
AH40
AG40
AE40
AD40
AC40
AA40
Y40
AN35
AM35
AJ35
AH35
AD35
AC35
W35
AM34
AL34
AJ34
AH34
AG34
AE34
AD34
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
AC34
AA34
VCC_35
VCC_36
Y34
W34
AM32
AL32
AJ32
AH32
AE32
AD32
AA32
AM31
AL31
AJ31
AH31
AM29
AL29
AM28
AL28
AJ28
AM27
AL27
AM25
AL25
AJ25
AM24
N36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
D
VCC CORE
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
+1.05V_M
VCC NCTF
2
1
2
AT41
AR41
AN41
AJ41
AH41
AD41
AC41
Y41
W41
AT40
AM40
AL40
POWER
2
1
C155
0.22U_0402_10V4Z~D
VCC GFX NCTF
1
1
C154
0.22U_0402_10V4Z~D
2
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34
B
1
2
1
2
1
2
1
2
1
2
1
2
C163
1U_0402_6.3V4Z~D
1
A
Title
Cantiga(5 of 6)
Size
4
3
2
Document Number
Rev
1.0
LA-4151P
Date:
5
C
C162
1U_0402_6.3V4Z~D
AU45
BF52
BB38
BA19
BE9
AU9
AL9
C161
0.47U_0402_10V4Z~D
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
C160
0.22U_0402_10V4Z~D
VCC SM LF
VCC GFX
1
2
R123
0_0402_5%~D
C159
0.22U_0402_10V4Z~D
<47> VCC_AXG_SENSE
<47> VSS_AXG_SENSE
2
1
2
Layout Note:
Inside GMCH
cavity for VCC_AXG.
2
A
1
C158
0.1U_0402_10V7K~D
VCC_AXG_SENSE
VSS_AXG_SENSE
2
C157
0.1U_0402_10V7K~D
AG13
AE13
1
1
C153
22U_0805_6.3VAM~D
B
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61
2
C753
22U_0805_6.3VAM~D
2
W32
AG31
AE31
AD31
AC31
AA31
Y31
W31
AH29
AG29
AE29
AD29
AC29
AA29
Y29
W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27
Y27
W27
AH25
AD25
AC25
W25
AJ24
AH24
AG24
AE24
AD24
AC24
AA24
Y24
W24
AM22
AL22
AJ22
AH22
AG22
AE22
AD22
AC22
AA22
AM21
AL21
AJ21
AH21
AD21
AC21
AA21
Y21
W21
AM16
AL16
+
C752
10U_0805_10V4Z~D
2
1
C1106
0.1U_0402_10V7K~D
C1105
0.1U_0402_10V7K~D
1
+VCC_GFXCORE
1
C751
0.1U_0402_10V7K~D
+VCC_CM_BF24
+VCC_CM_BL19
CRB 270uF
C750
0.1U_0402_10V7K~D
CRB use
C
+1.05V_M
C749
1U_0603_10V4Z~D
C1110
2
0.1U_0402_10V7K~D
2
C1102
0.1U_0402_10V7K~D
1
C1104
0.1U_0402_10V7K~D
C1103
0.1U_0402_10V7K~D
1
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
C748
0.47U_0402_10V4Z~D
+VCC_CM_BB36
+VCC_CM_BE35
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
C152
220U_D2_4VY_R15M~D
Layout Note:
Place close to GMCH
C151
22U_0805_6.3V6M~D
+
2
C150
22U_0805_6.3V6M~D
1
1
C148
330U_D2_2.5VY_R15M
2
C149
0.1U_0402_10V7K~D
D
+VCC_CM_BB36 BB36
+VCC_CM_BE35 BE35
AW34
AW32
BK30
BH30
BF30
1
1
BD30
BB30
AW30
2
2
BL29
BJ29
BG29
BE29
+VCC_CM_BC29 BC29
BA29
Layout Note:
AY29
Place on the edge
BK28
BH28
BF28
BD28
BB28
+VCC_CM_BB16
BL27
+VCC_CM_BC29
BJ27
BG27
BE27
BC27
1
1
BA27
AY27
AW26
2
2
+VCC_CM_BF24 BF24
+VCC_CM_BL19 BL19
+VCC_CM_BB16 BB16
VCC SM
+1.5V_MEM
POWER
U78F
T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18
Sheet
1
14
of
57
5
4
3
2
1
U78J
U78I
C
B
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS
VSS NCTF
D
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13
VSS_359
VSS_360
VSS_361
VSS_362
N42
N40
N38
M39
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7
BL55
BL1
A55
D1
B55
B2
A4
VSS SCB
BA55
AU55
AN55
AJ55
AE55
AA55
U55
N55
BD54
BG53
AJ53
AE53
AA53
U53
N53
J53
G53
E53
K52
BG51
BA51
AW51
AU51
AR51
AN51
AL51
AJ51
AG51
AE51
AC51
AA51
W51
U51
R51
N51
L51
J51
G51
C51
BK50
AM50
K50
BG49
E49
C49
BD48
BB48
AY48
AV48
AT48
AP48
AM48
AK48
AH48
AF48
AD48
AB48
Y48
V48
T48
P48
M48
K48
H48
BL47
BG47
E47
C47
A47
BD46
AY46
AM46
AK46
AH46
BG45
AE45
AC45
AA45
W45
R45
N45
E45
BD44
BB44
AV44
AK44
AH44
AF44
AD44
K44
H44
BL43
BG43
AY43
AR43
W43
R43
M43
E43
AN25
AG25
AE25
AA25
Y25
E25
A25
BD24
AN24
AL24
H24
BG23
AY23
E23
BD22
BB22
AN22
Y22
W22
H22
BL21
BG21
AY21
AN21
AG21
AE21
M21
E21
A21
BD20
H20
BG19
AY19
M19
E19
BD18
N18
H18
BL17
BG17
AY17
M17
E17
A17
BD16
AN16
AG16
AE16
Y16
W16
N16
H16
BG15
AY15
AN15
AD15
AC15
R15
M15
E15
BD14
H14
BL13
BG13
AY13
AU13
AR13
AJ13
AC13
AA13
W13
U13
M13
E13
A13
BD12
AV12
AP12
AM12
AK12
AB12
V12
P12
H12
BG11
AG11
E11
BD10
AY10
AP10
H10
BL9
BG9
E9
A9
BD8
BB8
AY8
AV8
AT8
AP8
D
C
B
A
A
Title
Cantiga(6 of 6)
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
15
of
57
5
4
3
+V_DDR_MCH_REF
2
+1.5V_MEM
1
+1.5V_MEM
JDIMMA
<11> DDR_A_D[0..63]
<11> DDR_A_MA[0..14]
2
1
2
DDR_A_DM0
C165
<11> DDR_A_DQS[0..7]
1
C164
<11> DDR_A_DM[0..7]
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
<11> DDR_A_DQS#[0..7]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D13
D
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
Layout Note:
Place near JDIMMA
DDR_A_D20
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
+1.5V_MEM
2
DDR_A_D25
DDR_A_D30
1
C174
0.1U_0402_16V4Z~D
1
C173
2
0.1U_0402_16V4Z~D
1
C172
C171
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
DDR_A_D18
DDR_A_D19
DDR_A_DM3
DDR_A_D26
DDR_A_D27
2
<10> DDR_CKE0_DIMMA
<11> DDR_A_BS2
+1.5V_MEM
C
+
2
2
C1119
330U_D2_2.5VY_R15M
2
1
1
C1118
2
1
10U_0603_6.3V6M~D
C1117
2
1
10U_0603_6.3V6M~D
C1116
2
1
10U_0603_6.3V6M~D
C1115
1
10U_0603_6.3V6M~D
C1114
2
10U_0603_6.3V6M~D
C1113
10U_0603_6.3V6M~D
1
<10> M_CLK_DDR0
<10> M_CLK_DDR#0
<11> DDR_A_BS0
<11> DDR_A_WE#
<11> DDR_A_CAS#
<10> DDR_CS1_DIMMA#
2
2
1
2
C190
2.2U_0603_6.3V6K~D
1
C189
A
0.1U_0402_16V4Z~D
+3.3V_M
205
GND1
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
GND2
206
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D14
DDR_A_D15
D
DDR_A_DM1
SM_DRAMRST#
SM_DRAMRST# <10,17>
DDR_A_D9
DDR_A_D12
DDR_A_D22
DDR_A_D21
DDR_A_DM2
DDR_A_D16
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D24
DDR_A_D31
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA <10>
T161PAD~D
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
C
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0
<10>
M_ODT1
<10>
+V_DDR_MCH_REF
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D33
DDR_A_D38
DDR_A_D47
DDR_A_D45
1
2
1
2
C1089
2
1
C1155
2
1
10U_0603_6.3V6M~D
C1154
1
10U_0603_6.3V6M~D
C1153
2
10U_0603_6.3V6M~D
2
1
C1123
1U_0603_10V4Z~D
2
1
C1122
1U_0603_10V4Z~D
1
C1121
1U_0603_10V4Z~D
2
C1120
1U_0603_10V4Z~D
1
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C1088
B
73
75
77
79
81
DDR_A_MA12
83
DDR_A_MA9
85
87
DDR_A_MA8
89
DDR_A_MA5
91
93
DDR_A_MA3
95
DDR_A_MA1
97
99
M_CLK_DDR0
101
M_CLK_DDR#0
103
105
DDR_A_MA10
107
DDR_A_BS0
109
111
DDR_A_WE#
113
DDR_A_CAS#
115
117
DDR_A_MA13
119
DDR_CS1_DIMMA#
121
123
125
127
DDR_A_D32
129
DDR_A_D39
131
133
DDR_A_DQS#4
135
DDR_A_DQS4
137
139
DDR_A_D34
141
DDR_A_D35
143
145
DDR_A_D40
147
DDR_A_D41
149
151
DDR_A_DM5
153
155
DDR_A_D42
157
DDR_A_D43
159
161
DDR_A_D54
163
DDR_A_D49
165
167
DDR_A_DQS#6
169
DDR_A_DQS6
171
173
DDR_A_D50
175
DDR_A_D51
177
179
DDR_A_D56
181
DDR_A_D57
183
185
DDR_A_DM7
187
189
DDR_A_D58
191
DDR_A_D59
193
195
197
1
2
R128 10K_0402_5%~D199
201
1
2
R129 10K_0402_5%~D203
+0.75V_DDR_VTT
DDR_A_BS2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
0.1U_0402_16V4Z~D
+0.75V_DDR_VTT
DDR_CKE0_DIMMA
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
2.2U_0603_6.3V6K~D
Layout Note:
Place near JDIMMA.203,204
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D44
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D48
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0
MEM_SDATA
MEM_SCLK
PM_EXTTS#0
MEM_SDATA
MEM_SCLK
<10,17,18>
<17,24>
<17,24>
+0.75V_DDR_VTT
FOX_AS0A626-U4SN-7F
A
5
4
3
2
Title
DDRIII-SODIMM SLOT1
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
16
of
57
5
4
3
2
+V_DDR_MCH_REF
+1.5V_MEM
1
+1.5V_MEM
JDIMMB
+V_DDR_MCH_REF
D
<11> DDR_B_DQS[0..7]
2
1
2
DDR_B_DM0
C192
<11> DDR_B_DM[0..7]
1
0.1U_0402_16V4Z~D
<11> DDR_B_D[0..63]
C191
2.2U_0603_6.3V6K~D
<11> DDR_B_DQS#[0..7]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
<11> DDR_B_MA[0..14]
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
Layout Note:
Place near JDIMMB
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
D
DDR_B_DM1
SM_DRAMRST#
SM_DRAMRST# <10,16>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
+1.5V_MEM
DDR_CKE2_DIMMB
<10> DDR_CKE2_DIMMB
2
1
C201
C200
2
1
0.1U_0402_16V4Z~D
C199
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
1
C198
0.1U_0402_16V4Z~D
C
DDR_B_MA12
DDR_B_MA9
2
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
1
2
C1129
2
1
+
2
DDR_B_MA10
DDR_B_BS0
<11> DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
<11> DDR_B_WE#
<11> DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
<10> DDR_CS3_DIMMB#
DDR_B_D40
DDR_B_D41
Layout Note:
Place near JDIMMB.203,204
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
+0.75V_DDR_VTT
DDR_B_D50
DDR_B_D51
2
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
+3.3V_M
+3.3V_M
1
2
1
C216
1
C215
2
+0.75V_DDR_VTT
2.2U_0603_6.3V6K~D
R131
10K_0402_5%~D
A
0.1U_0402_16V4Z~D
R132
10K_0402_5%~D
2
1
2
1
C1134
1U_0603_10V4Z~D
2
1
C1133
1U_0603_10V4Z~D
1
C1132
1U_0603_10V4Z~D
2
C1131
1U_0603_10V4Z~D
1
205
GND1
GND2
206
PAD~D
C
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2
<10>
M_ODT3
<10>
+V_DDR_MCH_REF
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
1
2
1
2
C1091
DDR_B_D34
DDR_B_D35
B
DDR_CKE3_DIMMB <10>
T162
DDR_B_MA14
C1090
DDR_B_DQS#4
DDR_B_DQS4
DDR_CKE3_DIMMB
0.1U_0402_16V4Z~D
DDR_B_D32
DDR_B_D33
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
2.2U_0603_6.3V6K~D
C1130
330U_D2_2.5VY_R15M
2
1
10U_0603_6.3V6M~D
C1128
2
1
10U_0603_6.3V6M~D
C1127
2
1
10U_0603_6.3V6M~D
C1126
1
10U_0603_6.3V6M~D
C1125
10U_0603_6.3V6M~D
C1124
10U_0603_6.3V6M~D
2
M_CLK_DDR2
M_CLK_DDR#2
<10> M_CLK_DDR2
<10> M_CLK_DDR#2
+1.5V_MEM
1
DDR_B_BS2
<11> DDR_B_BS2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#0
MEM_SDATA
MEM_SCLK
PM_EXTTS#0 <10,16,18>
MEM_SDATA <16,24>
MEM_SCLK <16,24>
+0.75V_DDR_VTT
A
FOX_AS0A626-U8SN-7F
2
5
4
3
2
Title
DDRIII-SODIMM SLOT2
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
17
of
57
5
4
3
2
1
1
+3.3V_M
R134
8.2K_0402_5%~D
2
+3.3V_M
+1.05V_VCCP
R135
C
2.2K_0402_5%~D
1
2
2
B
E
Q5
MMST3904-7-F_SOT323-3~D
1
R136
10K_0402_5%~D
JFAN1
2
<7> H_THERMTRIP#
<22> FAN1_DET#
2
THERMATRIP2#
PWR_MON
Diode circuit at DP4/DN4 is used for skin
temp sensor (placed optimally between CPU,
MEM).
MCH and
Place C221 close to the
Guardian pins as possible.
R1032
<34> BC_DAT_EMC4002
0_0402_5%~D
2
R1033
Place under CPU
1
E
C224
2200P_0402_50V7K~D
1
U3
EMC4002
Place C224, C225 close to the Guardian pins as possible
10
11
<7> H_THERMDA
1
<7> H_THERMDC
REM_DIODE1_P
REM_DIODE1_N
2
Q9 Place near DIMM
1
C
+3.3V_M
1
1
C228
2200P_0402_50V7K~D
@ C227
100P_0402_50V8K~D
3
2
1
Place C227 close
to Q9
2
B Q9
MMST3904-7-F_SOT323-3~D
E
REM_DIODE3_P
REM_DIODE3_N
DP1/VREF_T
DN1/THERM
38
37
DP2
DN2
41
40
DP3/DN7
DN3/DP7
+3V_M_THRM
4
+RTC_CELL_R
1
2
C230
1U_0603_10V4Z~D
R142 0_0603_5%~D 1+RTC_CELL
C229
0.1U_0402_16V4Z~D
1
R146 1
R148
<34,37> 3.3V_M_PWRGD
<37> ICH_PWRGD#
21
18
2
2 1K_0402_5%~D 17
1K_0402_5%~D
THERMATRIP1#
22
THERMATRIP2#
23
THERMATRIP3#
24
VSET
42
1
B
+3V_M_THRM
+5V_RUN
R151
1.5K_0402_1%~D
2
R150
1
4.7K_0402_5%~D
DP4/DN8
DN4/DP8
44
43
DP5/DN9
DN5/DP9
47
46
DP6/VREF_T2
DN6/VIN2
1
2
R140
10KB_0603_1%_TSM1A103F34D3R~D
REM_DIODE4_P
REM_DIODE4_N
1
2
C226
0.1U_0402_16V4Z~D
1
2
ACAV_IN
@ R1081
2
LDO_SHDN#
19
VSET
LDO_POK
34
ADDR_MODE/XEN
LDO_SET
33
+3.3V_M
BC_INT#_EMC4002 <34>
POWER_SW#
<34,46>
1
10K_0402_5%~D
1
10K_0402_5%~D
2
R149
2
R145
1
@ R147
1
+3.3V_M
10K_0402_5%~D
THERM_STP#
2
+RTC_CELL
47K_0402_1%~D
<42>
At maximum load current of 600mA,the the
voltage drop across the should be keep
in the range of 0.5V to 1V
+3.3V_SUS
2.5V_RUN_PWRGD <33,37>
B
LDO_SET
+3.3V_RUN
VDD_5V
VDD_5V
VDD_3V
7
8
FAN_OUT
FAN_OUT
TACH1/GPIO3
CLK_IN/GPIO2
32
31
VDDL/VDD_3V2
28
LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2
29
30
TACH2/GPIO4
PWM2/GPIO1
16
13
+3V_LDOIN
+1.8V_RUN_LVDS
1
2
2
2
@
1
2
2
1
R152
0_1210_5%~D
+1.8V_RUN_LVDS
LDO_SET
1
49
EC_32KHZ_OUT
1
1
R153
15
14
VDDH/VDD_5V2
VDDH/VDD_5V2
R155
8.2K_0402_5%~D
A
THERMATRIP3#
10K
1
2
<= 4.7K +/- 5%
2N3904
2F(r/w)
2N3904
2E(r/w)
C240
0.1U_0402_16V4Z~D
18K
Thermistor
2F(r/w)
>= 33K
Thermistor
2E(r/w)
PM_EXTTS#0 <10,16,17>
2
5
POWER_SW# 4
1
IN2
2
O
3
2
*
IN1
P
Pull-up Resistor For Remote1 SMBUS
on ADDR_MODE/XEN mode
Address
G
1
+RTC_CELL
C1158 0.1U_0402_16V4Z~D
1
2
R154
+3.3V_M
2
@ R1063
2
@ R1064
1
1
R143
R144
2
1
2
1
0_0402_5%~D
0_0402_5%~D
DOCK_PWR_SW# <34>
Ra
5.1K_0402_1%~D
9
3.16K_0402_1%~D
<34> EC_32KHZ_OUT
FAN1_TACH_FB
1
10K_0402_5%~D
C233
0.1U_0402_16V4Z~D
2
+FAN1_VOUT
THERMTRIP1#
THERMTRIP2#
THERMTRIP3#
12
26
27
20
25
C232
10U_0805_10V4Z~D
2
1
ATF_INT#/BC-LINK_IRQ#
RTC_PWR3V
POWER_SW#
ACAVAIL_CLR
THERMTRIP_SIO/PWM1/GPIO5
SYS_SHDN#
VCC_PWRGD
3V_PWROK#
C239
0.1U_0402_16V4Z~D
1
2
R141
VCC
C238
10U_0805_10V6K~D
2
C237
10U_0805_10V4Z~D
1
3
6
5
+3.3V_RUN
C236
0.1U_0402_16V4Z~D
2
C235
10U_0805_10V4Z~D
1
Rset=1.5K,Tp=95degree
C234
0.1U_0402_16V4Z~D
2
2
C231
0.1U_0402_16V4Z~D
39
48
45
VSS
1
VIN1
VCP1
VCP2
1
2
R139
1.2K_0402_1%~D
2
2
2
C
SMDATA/BC-LINK_DATA
SMBCLK/BC-LINK_CLK
36
35
Place C228 close to the Guardian pins as possible
@C222
100P_0402_50V8K~D
THERMISTOR OPTION:
Single-ended routing to thermistor is permissible
(ground return). Place R139 and C226 near EMC4002
2
2
B
Q8
MMST3904-7-F_SOT323-3~D
Place C223 close to the Q8 as possible
C225
470P_0402_50V7K~D
2
Place C222 close to Q7 as
possible.
1
C
2
3
1
2200P_0402_50V7K~D
200K_0402_1%~D
C
1
E
<34> BC_CLK_EMC4002
2
Q7
MMST3904-7-F_SOT323-3~D
2
B
C221
1
<10> THERMTRIP_MCH#
@ C223
100P_0402_50V8K~D
C
1
2
3
2
MAX8731_IINP <46>
MOLEX_53780-0470
1
C220
0.1U_0402_16V4Z~D
<45>
MAX8731_IINP
2
4.7K_0402_5%~D
1
R1061
1
+1.05V_VCCP
R138
C
2.2K_0402_5%~D
1
2
2
B
E
Q6
MMST3904-7-F_SOT323-3~D
2
PWR_MON_GFX <47>
1
2
3
4
GND
GND
2
2
R137
8.2K_0402_5%~D
1
C219
1
D2
RB751S40T1_SOD523-2~D
1
2
3
4
5
6
1
1
22U_0805_6.3VAM~D
+3.3V_M
+FAN1_VOUT
FAN1_TACH_FB
1
2
D
C218
0.1U_0402_16V4Z~D
3
3
D
1
1
THERMATRIP1#
Rb
Voltage margining circuit
for LDO output. Adjustable
from 1.2 to 2.5V.
Ra=((LDO_OUT/1.2)-1)*Rb.
POWER_SW_IN# <34>
U93
0_0402_5%~D
0_0402_5%~D
5
4
3
2
Title
FAN & Thermal Sensor
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
18
of
57
A
5
4
3
2
1
LCD Power
+LCDVDD
S
SW_LVDS_A2+ <40>
SW_LVDS_A2- <40>
3
<33> LCD_VCC_TEST_EN
1EN_LCDPWR 2
SW_LVDS_A1+ <40>
SW_LVDS_A1- <40>
SW_LVDS_A0+ <40>
SW_LVDS_A0- <40>
LCD_SMBCLK
LCD_SMBDAT
I
2
ENVDD
1
2
1
D
3
D3 BAT54CW_SOT323~D
@
C241
0.1U_0402_16V4Z~D
Q15
DDTC124EUA-7-F_SOT323-3~D
G
<12>
LDDC_DATA_MCH_LVDS
LDDC_CLK_MCH_LVDS
LVDS_CBL_DET#
4
O
1
1
5
2
2
3
2
3
1
2
1
6 2
1
RB751V_SOD323-2~D
2
C242
0.1U_0402_25V4Z~D
5@ D68
Q12
1
SI3456DV-T1-E3_TSOP6~D
G
BKT_GPIO18 2
<35> BKT_GPIO18
SW_LVDS_ACLK+ <40>
SW_LVDS_ACLK- <40>
LDDC_DATA_MCH_LVDS <39>
LDDC_CLK_MCH_LVDS <39>
LVDS_CBL_DET# <22>
+3.3V_RUN_LVDS
LCD_SMBCLK <34>
LCD_SMBDAT <34>
+INV_PWR_SRC
1
2
2
+INV_PWR_SRC
C
1
R167
100K_0402_5%~D
2
C247
0.1U_0603_50V4Z~D
PWR_SRC_ON
+3.3V_RUN_LVDS
R1091
10K_0402_5%~D
2
JAE_SP07-12942-03
Q18
2N7002W-7-F_SOT323-3~D
3
2 +PWR_SRC_ON_F 1
100K_0402_5%~D
1
R168
S
+3.3V_RUN
BREATH_BLUE_LED <38>
BATT_YELLOW_LED <38>
BATT_BLUE_LED <38>
D
BREATH_BLUE_LED
BATT_YELLOW_LED
BATT_BLUE_LED
C245
0.1U_0402_16V4Z~D
+3.3V_RUN_BKT_PWR
+5V_ALW
1
<33>
8
7
6
5
1
2
3
D69
<35> BKT_GPIO14
D81
1
2
BIA_PWM
BKT_GPIO14
2
G
+LCDVDD
LCD_TST
5@ PJP52 PAD-OPEN 4x4m
1
2
+3.3V_RUN
1
LCD_TST
<21>
<21>
40mil
40mil
4
BIA_PWM_LCD
1
2
1
DMIC_CLK
DMIC0
@ Q16
FDS4435_NL_SO8~D
+PWR_SRC
+3.3V_RUN_LVDS
2
1
2
C246
0.1U_0603_50V4Z~D
C248
1000P_0402_50V7K~D
C
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R158
100K_0402_5%~D
R163
100K_0402_5%~D
G9
G8
G7
G6
G5
G4
G3
G2
G1
6
5
2
1
4
Q13B
2N7002DW-T/R7_SOT363-6~D
Q13A
2N7002DW-T/R7_SOT363-6~D
JLVDS1
R162
100K_0402_5%~D
Place near to JLVDS1
D
R161
470_0402_5%~D
2 LDDC_CLK_MCH_LVDS
2.2K_0402_5%~D
2 LDDC_DATA_MCH_LVDS
2.2K_0402_5%~D
1
R159
1
R160
+15V_ALW
1
+LCDVDD
51
50
49
48
47
46
45
44
43
+3.3V_ALW
D
+15V_ALW
+3.3V_RUN_LVDS
3
1 R1058 2
@ 100K_0402_5%~D
1 EN_INVPWR
<12>
RB751S40T1_SOD523-2~D
<21,33,36,37,39> RUN_ON
RUN_ON
FDS4435: P CHANNAL
2
BAT54CW_SOT323~D
+3.3V_RUN_LVDS
C244
0.1U_0402_16V4Z~D
2
+3.3V_RUN
R1096
0_0603_5%~D
2
1
+5V_RUN
<24>
USBP11+
USBP11-
USBP11+
1
USBP11-
4
@ L70
DLW21SN121SQ2L_4P~D
1
2 2
4
2
3
USBP11_D+
Dual layout for Q17
USBP11_D-
3
1
R1095
2
0_0402_5%~D
1
R1097
2
0_0402_5%~D
B
Overlap on Q16 for pop option
+PWR_SRC
Q17
SI3457DV-T1_TSOP6~D
1
@ U98
C1170
0.1U_0402_16V4Z~D
USBP11_D+
+15V_ALW
1
GND IO2
3
2
IO1
4
VIN
USBP11_D4
+CAMERA_VDD
6
5
2
1
+INV_PWR_SRC
1
3
G
PRTR5V0U2X_SOT143-4~D
R1098
100K_0402_5%~D
CCD_OFF
CCD_OFF
A
D
2
G
3
<33>
PWR_SRC_ON
JCAM
S
2N7002W-7-F_SOT323-3~D
Webcam PWR CTRL
1
2
Close to JLVD1.8,9,10
Q166
2
2
+CMOS_VDD
G
+LCDVDD
1
C1169
10U_1206_16V4Z~D
2
C1168
0.1U_0402_16V4Z~D
1
1
<24>
@ R1094
0_0603_5%~D
2
1
D
3
Close to JLVD1.25
1
Q165
PMV45EN_SOT23-3~D
S
+CAMERA_VDD
D
2
For Webcam
S
B
C243
0.1U_0402_16V4Z~D
1
+CAMERA_VDD
1
2
<22> CAM_CBL_DET#
C1171
0.1U_0402_25V4K~D
USBP11_DUSBP11_D+
CAM_CBL_DET#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
GND
GND
SI3457DV : P CHANNAL
A
TYCO_2041070-6
Title
LVDS Conn
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
19
of
57
2
1
+3.3V_RUN
U4
<12>
DAT_DDC2
<12> CLK_DDC2
<12> CRT_VSYNC
<12> CRT_HSYNC
<12>
CRT_RED
<12>
CRT_GRN
<12>
CRT_BLU
<33> CRT_SWITCH
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SEL
0
1
CRT
MB
Dock
TV
Dock
NA
46
45
41
40
35
34
30
29
25
26
DAT_DDC2_DOCK
CLK_DDC2_DOCK
VSYNC_DOCK
H SYNC_DOCK
RED_DOCK
GREEN_DOCK
BLUE_DOCK
NC
NC
NC
NC
52
5
54
51
B
DAT_DDC2_DOCK <31>
CLK_DDC2_DOCK <31>
VSYNC_DOCK <31>
HSYNC_DOCK <31>
RED_DOCK <31>
GREEN_DOCK <31>
BLUE_DOCK <31>
To Dock Conn.
+3.3V_RUN
1
TS3DV520ERHUR_QFN56_11X5~D
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
C266
0.1U_0402_16V4Z~D
SEL
1
6
9
13
16
21
24
28
33
39
44
49
53
55
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
C265
0.1U_0402_16V4Z~D
17
To MB CRT Conn.
C264
0.1U_0402_16V4Z~D
CRT_SWITCH
B
DAT_DDC2_CRT <29>
CLK_DDC2_CRT <29>
VSYNC_CRT <29>
HSYNC_CRT <29>
RED_CRT
<29>
GREEN_CRT <29>
BLUE_CRT
<29>
C263
0.1U_0402_16V4Z~D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DAT_DDC2_CRT
CLK_DDC2_CRT
VSYNC_CRT
HSYNC_CRT
RED_CRT
GREEN_CRT
BLUE_CRT
C262
0.1U_0402_16V4Z~D
2
3
7
8
11
12
14
15
19
20
48
47
43
42
37
36
32
31
22
23
C261
0.1U_0402_16V4Z~D
DAT_DDC2
CLK_DDC2
CRT_VSYNC
CRT_HSYNC
CRT_RED
CRT_GRN
CRT_BLU
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
C260
0.1U_0402_16V4Z~D
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C259
10U_0805_10V4Z~D
4
10
18
27
38
50
56
A
A
2
Title
CRT/Video switch
Size
Document Number
Date:
Rev
1.0
LA-4151P
1
Sheet
20
of
57
2
1
SW for eDOCK side
JBIO1
C1159
<12>
0.1U_0402_10V7K~D
1 DPB_AUX_C
DPB_AUX#_C
2
1
C273 0.1U_0402_10V7K~D
<12> DPB_AUX#
2
5
1
7
8
3
6
4
1A
VCC
2A
1B
1OE#
2B
2OE# GND
SDVO_CTRLCLK
SDVO_CTRLDATA
2
5
1
7
2
DPB_DOCK_AUX#
1
@ R1086
DPB_DOCK_AUX
1
@ R1085
0.1U_0402_16V4Z~D
8
3
6
4
1A
VCC
2A
1B
1OE#
2B
2OE# GND
<31> DOCK_LOM_TRD3<31> DOCK_LOM_TRD3+
+3.3V_RUN
C1174 1
+5V_RUN
U100
<22,32> PLTRST3#
<24> PCIE_IRX_WLANTX_N2
<24> PCIE_IRX_WLANTX_P2
<24> PCIE_ITX_WLANRX_N2_C
<24> PCIE_ITX_WLANRX_P2_C
2
100K_0402_5%~D
2
100K_0402_5%~D
<24> PCIE_MCARD1_DET#
<28,34> CARD_SMBCLK
<28,34> CARD_SMBDAT
<34> MSCLK
<34> MSDATA
<38> LED_WLAN_OUT#
<28,33> PCIE_WAKE#
<24> PCIE_IRX_WANTX_N1
<24> PCIE_IRX_WANTX_P1
<24> PCIE_ITX_WANRX_N1_C
<24> PCIE_ITX_WANRX_P1_C
SN74CBTD3306CPWR_TSSOP8~D
C277
1
Y
P
NC
4
3
U8
DPB_DOCK_CA_DET
2
A
G
DPB_DOCK_CA_DET#
B
0.1U_0402_16V4Z~D
2
5
1
+3.3V_RUN
DPB_DOCK_CA_DET <31>
NC7SZ04P5X_NL_SC70-5~D
1
2
R1052
1M_0402_5%~D
<22> PCIE_MCARD2_DET#
<33> WWAN_RADIO_DIS#
<24> PCIE_IRX_GLANTX_P6
<24> PCIE_IRX_GLANTX_N6
<24> USB_MCARD2_DET#
<24> PCIE_ITX_GLANRX_P6_C
<24> PCIE_ITX_GLANRX_N6_C
<35> BKT_GPIO12
<23> LAN_RSTSYNC
<23> LAN_CLK
SW for eDOCK side
C1160
1
+5V_RUN
<12> DPC_DOCK_AUX
<12> DPC_DOCK_AUX#
C272
2
1
0.1U_0402_10V7K~D
DPC_DOCK_AUX_C
DPC_DOCK_AUX#_C
2
C274
1
0.1U_0402_10V7K~D
0.1U_0402_16V4Z~D
2
<23>
LAN_TX0
<23>
LAN_TX1
<23>
LAN_TX2
<23>
LAN_RX0
<23>
LAN_RX1
<23>
LAN_RX2
<23> ICH_AZ_CODEC_BITCLK
<23> ICH_AZ_CODEC_SDIN0
<23> ICH_AZ_CODEC_SDOUT
<23> ICH_AZ_CODEC_SYNC
<23> ICH_AZ_CODEC_RST#
U101
2
5
1
7
1A
VCC
2A
1B
1OE#
2B
2OE# GND
8
3
6
4
DPC_DOCK_AUX_SW <31>
DPC_DOCK_AUX#_SW <31>
DPC_DOCK_CA_DET
+5V_RUN C1175 1
U102
2
5
1
7
<10> DDPC_CTRLCLK
<10> DDPC_CTRLDATA
1A
VCC
2A
1B
1OE#
2B
2OE# GND
2
DPC_DOCK_AUX#_SW1
@ R1088
DPC_DOCK_AUX_SW 1
@ R1087
2
100K_0402_5%~D
2
100K_0402_5%~D
Y
PCIE_MCARD2_DET#
WWAN_RADIO_DIS#
PCIE_IRX_GLANTX_P6
PCIE_IRX_GLANTX_N6
USB_MCARD2_DET#
PCIE_ITX_GLANRX_P6_C
PCIE_ITX_GLANRX_N6_C
BKT_GPIO12
LAN_RSTSYNC
LAN_CLK
LAN_TX0
LAN_TX1
LAN_TX2
LAN_RX0
LAN_RX1
LAN_RX2
ICH_AZ_CODEC_BITCLK
ICH_AZ_CODEC_SDIN0
ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_RST#
+5V_ALW
P
5
1
PCIE_MCARD1_DET#
CARD_SMBCLK
CARD_SMBDAT
MSCLK
MSDATA
LED_WLAN_OUT#
PCIE_WAKE#
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
+3.3V_RUN_WWAN
2
A
DPC_DOCK_CA_DET
DPC_DOCK_CA_DET <31>
+LOM_VCT
G
4
NC
U7
DPC_DOCK_CA_DET#
DOCK_LOM_TRD3DOCK_LOM_TRD3+
LAN_DISABLE#_R
PLTRST3#
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
+3.3V_LAN
0.1U_0402_16V4Z~D
2
1
+3.3V_RUN
+5V_RUN_AMP
+3.3V_WLAN
C276
AUD_NB_MUTE
+3.3V_RUN_BKT_PWR
+3.3V_RUN
+3.3V_RUN
0.1U_0402_16V4Z~D
8
3
6
4
AUD_NB_MUTE
<31> DOCK_LOM_TRD2<31> DOCK_LOM_TRD2+
DPB_DOCK_AUX <31>
DPB_DOCK_AUX# <31>
DPB_DOCK_CA_DET
<10> SDVO_CTRLCLK
<10> SDVO_CTRLDATA
<33>
<31>
<31>
<31>
<31>
U99
C271
2
DPB_AUX
0.1U_0402_16V4Z~D
2
1
+5V_RUN
3
R1053
1
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
1
3
5
7
9
GND
13
15
17
19
21
23
25
27
29
31
33
GND
37
39
41
43
45
47
49
51
53
55
57
GND
61
63
65
67
69
71
73
75
77
79
GND
83
85
87
89
91
93
95
97
99
101
103
GND
107
109
111
113
115
117
119
121
123
125
127
GND
131
133
135
137
139
2
4
6
8
10
GND
14
16
18
20
22
24
26
28
30
32
34
GND
38
40
42
44
46
48
50
52
54
56
58
GND
62
64
66
68
70
72
74
76
78
80
GND
84
86
88
90
92
94
96
98
100
102
104
GND
108
110
112
114
116
118
120
122
124
126
128
GND
132
134
136
138
140
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
USBP0+
USBP0DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_SPD100LED_ORG#
TPA0+
TPA0TPB0+
TPB0WLAN_RADIO_DIS#
BT_ACTIVE
COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
USB_MCARD1_DET#
ICH_CL_CLK1
ICH_CL_DATA1
USBP0+
<24>
USBP0<24>
DOCK_LOM_ACTLED_YEL# <31>
DOCK_LOM_SPD10LED_GRN# <31>
DOCK_LOM_SPD100LED_ORG# <31>
TPA0+
<27>
TPA0<27>
TPB0+
<27>
TPB0<27>
WLAN_RADIO_DIS# <33>
BT_ACTIVE
<30,38>
COEX1_BT_ACTIVE <30>
COEX2_WLAN_ACTIVE <30>
USB_MCARD1_DET# <24>
ICH_CL_CLK1 <24>
ICH_CL_DATA1 <24>
ICH_CL_RST1#
HOST_DEBUG_RX
HOST_DEBUG_TX
MINI2CLK_REQ#
CLK_PCIE_MINI2#
CLK_PCIE_MINI2
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1CLK_REQ#
USBP4+
USBP4-
ICH_CL_RST1# <24>
HOST_DEBUG_RX <34>
HOST_DEBUG_TX <34>
MINI2CLK_REQ# <6>
CLK_PCIE_MINI2# <6>
CLK_PCIE_MINI2 <6>
CLK_PCIE_MINI1# <6>
CLK_PCIE_MINI1 <6>
MINI1CLK_REQ# <6>
USBP4+
<24>
USBP4<24>
LED_WWAN_OUT#
USB_OC0_1#
USB_POWERSHARE_PWR_EN#
USB_SW_USBD+
USB_SW_USBDCELL_CHARGER_DET_R#
CKG_SMBCLK
CKG_SMBDAT
AUD_PC_BEEP
DOCKED
B
LED_WWAN_OUT# <38>
USB_OC0_1# <24>
USB_POWERSHARE_PWR_EN# <33>
USB_SW_USBD+ <40>
USB_SW_USBD- <40>
CKG_SMBCLK <6,34,46>
CKG_SMBDAT <6,34,46>
DOCKED
DMIC0
DMIC_CLK
DOCK_MIC_DET
DOCK_HP_DET
AUD_HP_NB_SENSE
RUN_ON
DAI_DO#
DAI_DI
DAI_LRCK#
DAI_BCLK#
EN_I2S_NB_CODEC
<33>
DMIC0
<19>
DMIC_CLK
<19>
DOCK_MIC_DET <33>
DOCK_HP_DET <33>
AUD_HP_NB_SENSE <33>
RUN_ON
<19,33,36,37,39>
DAI_DO#
<31>
DAI_DI
<31>
DAI_LRCK# <31>
DAI_BCLK# <31>
EN_I2S_NB_CODEC <33>
DAI_12MHZ#
INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2
WIRELESS_ON#/OFF
BKT_GPIO13
BKT_I2S_DO
BKT_I2S_LRC
BKT_I2S_SCLK
BKT_MCLK
DAI_12MHZ# <31>
INT_SPK_L1 <29>
INT_SPK_L2 <29>
INT_SPK_R1 <29>
INT_SPK_R2 <29>
WIRELESS_ON#/OFF <33>
BKT_GPIO13 <35>
BKT_I2S_DO <39>
BKT_I2S_LRC <39>
BKT_I2S_SCLK <39>
BKT_MCLK
<39>
SNIFFER_PWR_SW#
SNIFFER_YELLOW
SNIFFER_BLUE
SNIFFER_PWR_SW# <34>
SNIFFER_YELLOW <38>
SNIFFER_BLUE <38>
+1.5V_RUN
1M_0402_5%~D
FOX_QT00140A-1120-9F
+3.3V_RUN
+3.3V_RUN
<34>
BEEP
1
C389
1
C394
R798
20K_0402_5%~D
R327 1
2
0.1U_0402_16V4Z~D
R828 1
2
0.1U_0402_16V4Z~D
2 499K_0402_1%~D
AUD_PC_BEEP
2 499K_0402_1%~D
1
+3.3V_ALW
3
2
1
2
2
4
1
2
2
R795
20K_0402_5%~D
PAD-OPEN 2x2m~D
6@
PJP53
1
2
2
100K_0402_5%~D
+3.3V_ALW_ICH
2
100K_0402_5%~D
2
100K_0402_5%~D
2PCIE_MCARD1_DET#
0_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
USB_MCARD2_DET# 1
@ R740
2 PCIE_MCARD2_DET#
0_0402_5%~D
+5V_RUN_AMP
1
2
1
2
1
2
1
1
C1135
<34> EN_CELL_CHARGER_DET#
<33> CELL_CHARGER_DET#
2
@ R996
1
0_0402_5%~D
2
1U_0402_6.3V6K~D
CELL_CHARGER_DET_R#
+3.3V_ALW2
D80
2
1
2
R1083
1
100K_0402_5%~D
RB751S40T1_SOD523-2~D
<24> LAN_DISABLE#
<33> LAN_DISABLE#_R
LAN_DISABLE# 2
R1028
1
0_0402_5%~D
LAN_DISABLE#_R
1
+5V_RUN
2
C459
0.1U_0402_16V4Z~D
<36> ENAB_3VLAN
+3.3V_RUN
USB_MCARD1_DET# 1
R438
PCIE_MCARD1_DET# 1
@ R439
1
R1090
USB_MCARD1_DET#
1
@ R741
USB_MCARD2_DET# 2
R447
PCIE_MCARD2_DET# 2
R449
A
C458
0.1U_0402_16V4Z~D
1
+3.3V_LAN
C457
4.7U_0603_6.3V4Z~D
1
Q44
STS11NF30L_SO8~D
8
1
7
2
6
3
5
C456
4.7U_0603_6.3V4Z~D
1
R824
7.5K_0402_5%~D
2
C455
10U_0805_10V4Z~D
R191
100K_0402_5%~D
S
2
C454
0.1U_0402_16V4Z~D
Q10
BSS138_SOT23~D
<31> DPB_DOCK_HPD
A
@
R328
10K_0402_5%~D
<12>
D
2
G
C453
4.7U_0603_6.3V4Z~D
1
DPB_HPD#
DPB_DOCK_HPD
+3.3V_RUN
TRACE>15 mil
1
SPKR
2
<24>
2
1
3
R796
100K_0402_5%~D
S
+5V_RUN_BKT_PWR
2
Q114
BSS138_SOT23~D
<31> DPC_DOCK_HPD_R
D
2
G
R825
7.5K_0402_5%~D
5@
1
PJP54
2
PAD-OPEN 2x2m~D
+3.3V_RUN_WWAN_PWR
1
1
DPC_DOCK_HPD# <12>
DPC_DOCK_HPD_R
1
PJP56
2
PAD-OPEN 2x2m~D
2
+3.3V_RUN_WWAN
Title
Display port
Size
Document Number
Date:
Rev
1.0
LA-4151P
1
Sheet
21
of
57
5
4
3
2
1
+3.3V_RUN
<27> PCI_AD[0..31]
U79B
1
R755
1
R212
1
R817
1
R926
LVDS_CBL_DET#
2
100K_0402_5%~D
CAM_CBL_DET#
2
100K_0402_5%~D
PNL_BKLT_CBL_DET#
2
100K_0402_5%~D
FAN1_DET#
2
100K_0402_5%~D
<27> PCI_PIRQC#
<27> PCI_PIRQD#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
F1
F5
F2
C7
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D10
A5
E6
C9
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
C3
B1
T3
A7
D4
C5
H5
A6
A2
B8
PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
A21
B5
T1
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
PCI_REQ1#
<27>
PCI_GNT1#
<27>
PCIE_MCARD2_DET# <21>
ICH_GPIO53
<23>
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
D
+3.3V_ALW_ICH
C294
0.1U_0402_16V4Z~D
<27>
<27>
<27>
<27>
14
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCIE_MCARD2_DET#
ICH_GPIO53
PCI_REQ3#
PCI_GNT3#
PCI_PCIRST#
PCI_IRDY# <27>
PCI_PAR <27>
1
IN1
2
IN2
OUT
PCI_SERR# <27>
PCI_STOP# <27>
PCI_TRDY# <27>
PCI_FRAME# <27>
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCI_RST#
<27,30>
14
+3.3V_ALW_ICH
PCI_PLTRST#
4
IN1
5
IN2
P
CLK_PCI_ICH <6>
ICH_PME#
<33>
LVDS_CBL_DET#
PNL_BKLT_CBL_DET#
CAM_CBL_DET#
FAN1_DET#
G3
G1
F3
H4
PCI_RST#
3
U11A
74VHC08MTCX_NL_TSSOP14~D
7
PCI_DEVSEL# <27>
PCI_PERR# <27>
P
G4
E1
A9
E12
B11
C10
D6
C6
G
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
OUT
PLTRST1#
6
PLTRST1#
<10,28>
G
PCI
U11B
LVDS_CBL_DET# <19>
+3.3V_ALW_ICH
CAM_CBL_DET# <19>
FAN1_DET#
<18>
ICH9-M SFF ES_FCBGA569~D
10
IN1
9
IN2
OUT
C
PLTRST2#
8
PLTRST2#
<33,34>
U11C
7
C
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
7
+3.3V_RUN
A11
B12
A10
C12
A8
A12
E10
C11
B9
D8
A4
E8
A3
D9
C8
C2
D7
B3
D11
B6
D5
D3
F4
E3
E4
B2
C4
C1
D1
E2
J4
H2
14
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
P
PCI_DEVSEL#
2
8.2K_0402_5%~D
PCI_STOP#
2
8.2K_0402_5%~D
PCI_TRDY#
2
8.2K_0402_5%~D
PCI_FRAME#
2
8.2K_0402_5%~D
PCI_PLOCK#
2
8.2K_0402_5%~D
PCI _IRDY#
2
8.2K_0402_5%~D
PCI_SERR#
2
8.2K_0402_5%~D
PCI_PERR#
2
8.2K_0402_5%~D
PCI_REQ3#
2
8.2K_0402_5%~D
PCI_PIRQA#
2
8.2K_0402_5%~D
PCI_PIRQB#
2
8.2K_0402_5%~D
PCI_PIRQC#
2
8.2K_0402_5%~D
PCI_PIRQD#
2
8.2K_0402_5%~D
PCI_REQ0#
2
8.2K_0402_5%~D
PCI_REQ1#
2
8.2K_0402_5%~D
G
D
1
R194
1
R195
1
R196
1
R197
1
R198
1
R199
1
R200
1
R201
1
R925
1
R202
1
R203
1
R204
1
R205
1
R207
1
R208
14
+3.3V_ALW_ICH
IN1
12
IN2
P
13
7
PCI_GNT0#
PLTRST3#
<21,32>
U11D
ICH_SPI_CS1#
1
1
<24> ICH_SPI_CS1#
1
PCI_GNT3#
11 PLTRST3#
G
OUT
@ R214
1K_0402_5%~D
2
R213
1K_0402_5%~D
2
@ R215
1K_0402_5%~D
B
2
B
Place closely pin U79.B5
2
CLK_PCI_ICH
A16 away override strap.
@ R216
10_0402_5%~D
Low = A16 swap override enabled.
High = Default.
PCI_GNT0#
*
SPI_CS1#
Boot BIOS Location
0
1
SPI
1
0
PCI
1
1
LPC
CLK_ICH_TERM 1
PCI_GNT3#/(MDC_RST_DIS#)
Boot BIOS Strap
1
2
@ C295
8.2P_0402_50V8J~D
A
A
Title
ICH9-M(1/4)
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
22
of
57
3
2
1
+RTC_CELL
+RTC_CELL
1
4
1
5
2
R218
332K_0402_1%~D
D
1
Package
9.6X4.06 mm
ICH9M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
2
2
<21>
ME_CLR1
1
C298
@SHORT PADS~D
2
1U_0603_10V4Z~D
LAN_CLK
<21> LAN_RSTSYNC
CMOS_CLR1 @SHORT PADS~D
1
2
C299
1U_0603_10V4Z~D
<21>
<21>
<21>
LAN_RX0
LAN_RX1
LAN_RX2
<21>
<21>
<21>
LAN_TX0
LAN_TX1
LAN_TX2
1
@ C302
27P_0402_50V8J~D
1
R243
1
R244
1
R245
1
R246
<10> ICH_AZ_MCH_SDOUT
<10> ICH_AZ_MCH_SYNC
<10> ICH_AZ_MCH_RST#
<10> ICH_AZ_MCH_BITCLK
@ C309
27P_0402_50V8J~D
1
2 ICH_AZ_SDOUT
33_0402_5%~D
2 I CH_AZ_SYNC
33_0402_5%~D
2 ICH_AZ_RST#
33_0402_5%~D
2 ICH_AZ_BITCLK
33_0402_5%~D
2
R241 1
1
R235
1
R239
<21> ICH_AZ_CODEC_RST#
<21> ICH_AZ_CODEC_SDIN0
LAN_CLK
G22
GLAN_CLK
LAN_RSTSYNC
D14
A14
D12
B14
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TX0
LAN_TX1
LAN_TX2
D13
C13
A13
LAN_TXD0
LAN_TXD1
LAN_TXD2
GLAN_DOCK#
D15
GPIO56
H22
H21
GLAN_COMPI
GLAN_COMPO
AE7
AB7
<10> ICH_AZ_MCH_SDIN2
1
R234
<33>
ME_FWP
<41> RTC_BAT_DET#
ICH_AZ_SDOUT
2
33_0402_5%~D
ME_FWP
RTC_BAT_DET#
SATA_ACT#_R
<38> SATA_ACT#_R
<26> PSATA_IRX_DTX_N0_C
<26> PSATA_IRX_DTX_P0_C
<26> PSATA_ITX_DRX_N0
<26> PSATA_ITX_DRX_P0
2
C307 2
C308
<26> SATA_ODD_IRX_DTX_N1_C
<26> SATA_ODD_IRX_DTX_P1_C
<26> SATA_ODD_ITX_DRX_N1
<26> SATA_ODD_ITX_DRX_P1
2
C310 2
C311
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
LDRQ0#
LDRQ1#/GPIO23
H1
J1
LPC_LDRQ0#
LPC_LDRQ1#
A20GATE
A20M#
N3
AB23
SIO_A20GATE
H_A20M#
DPRSTP#
DPSLP#
AE23
AE24
LAN_RSTSYNC
LAN_RX0
LAN_RX1
LAN_RX2
1
2
R232
24.9_0402_1%~D
33_0402_5%~D
ICH_AZ_BITCLK
2
I CH_AZ_SYNC
2
33_0402_5%~D
ICH_AZ_RST#
2
33_0402_5%~D
ICH_AZ_CODEC_SDIN0
FWH4/LFRAME#
LPC_LFRAME#
HDA_BIT_CLK
HDA_SYNC
AA7
HDA_RST#
AB6
AE6
AC6
AA5
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AC7
HDA_SDOUT
AD8
AB8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AC9
SATALED#
PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C
AE14
AD14
AC15
AD15
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA_ODD_ITX_DRX_N1_C
SATA_ODD_ITX_DRX_P1_C
AD13
AC13
AA14
AB14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
1
@ R248
1K_0402_5%~D
0
0
FERR#
AD25
AE22
IGNNE#
AD23
H_IGNNE#
INIT#
INTR
RCIN#
AE21
AD24
L1
H_INIT#
H_INTR
SIO_RCIN#
NMI
SMI#
AD21
AC21
H_NMI
H_SMI#
STPCLK#
AC25
H_STPCLK#
THRMTRIP#
AC23
THRMTRIP_ICH#
TP11
AC22
ICH_TP12
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AD12
AE12
AB12
AA12
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AC11
AD11
AB10
AA10
SATA_CLKN
SATA_CLKP
AC16
AB16
ESATA_IRX_DTX_N4_C
ESATA_IRX_DTX_P4_C
ESATA_ITX_DRX_N4_C
ESATA_ITX_DRX_P4_C C303
C304
SATA_SBRX_DTX_N3_C
SATA_SBRX_DTX_P3_C
SATA_ITX_DRX_N3_C
SATA_ITX_DRX_P3_C
C305
C306
CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS#
SATARBIAS
AD10
AE10
0
Normal Operation (Default)
1
1
Set PCIE port config bit 1
1
1
@ R249
1K_0402_5%~D
A
<7>
<7>
<34>
H_NMI
H_SMI#
<7>
<7>
H_STPCLK#
<7>
1
10K_0402_5%~D
1
10K_0402_5%~D
100K_0402_5%~D
2
2
R233
1
56_0402_5%~D
+1.05V_VCCP
H_FERR#
C
<8,10,45>
<8>
+1.05V_VCCP
R237
56_0402_5%~D
1
2
C301
0.1U_0402_16V4Z~D
T41PAD~D
2
R247
2
2
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
2
2
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
ESATA_IRX_DTX_N4_C <29>
ESATA_IRX_DTX_P4_C <29>
ESATA_ITX_DRX_N4 <29>
ESATA_ITX_DRX_P4 <29>
SATA_SBRX_DTX_N3_C
SATA_SBRX_DTX_P3_C
SATA_SBTX_C_DRX_N3
SATA_SBTX_C_DRX_P3
<31>
<31>
<31>
<31>
B
CLK_PCIE_SATA# <6>
CLK_PCIE_SATA <6>
1
24.9_0402_1%~D
ICH9MSFF Straps
HDA_SYNC
HDA SDOUT
0
0
1
1
Ports Routing
Port 1(X1),Port 2(X1),Port 3(X1), Port 4(X1) default
I CH_AZ_SYNC
ICH_GPIO53
@ R929
1K_0402_5%~D
2
Enter XOR Chain
1
1
2
0
<7>
H_INIT#
H_INTR
SIO_RCIN#
RTC_BAT_DET#
2
R230
2
R231
R757
1
PCIe Port Configuration 1 (Ports 1-4)
@ R928
1K_0402_5%~D
ICH_RSVD_TP3 <24>
H_IGNNE#
SIO_A20GATE
H_DPRSTP#
H_DPSLP#
Within 500 mils
ICH_AZ_SDOUT
RSVD
LPC_LDRQ0# <33>
LPC_LDRQ1# <33>
CPUPWRGD
Description
2
HDA SDOUT
2
ICH_RSVD_TP3
1
XOR Chain Entrance Strap
+3.3V_RUN
LPC_LFRAME# <30,32,33,34>
SIO_A20GATE <34>
H_A20M#
<7>
+3.3V_RUN
SIO_RCIN#
H_DPRSTP#
H_DPSLP#
R229
2
1H_FERR# H_FERR#
<7>
56_0402_5%~D
H_PW RGOOD
H_PWRGOOD <8>
+3.3V_RUN
<30,32,33,34>
1
INTVRMEN
LAN100_SLP
ICH_AZ_MCH_SDIN2
<21> ICH_AZ_CODEC_SDOUT
2
E25
D25
+1.5V_RUN_PCIE_ICH
<21> ICH_AZ_CODEC_BITCLK
<21> ICH_AZ_CODEC_SYNC
B
ICH_INTVRMEN
LAN100_SLP
J2
2
1
RTCRST#
SRTCRST#
INTRUDER#
LPC_LAD[0..3] <30,32,33,34>
<30,32,33,34>
<30,32,33,34>
+1.05V_VCCP
<30,32,33,34>
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
1
1
@
G24
C24
C23
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
2
2
ICH_RTCRST#
SRTCRST#
INTRUDER#
H3
J3
K5
L3
@ R228
56_0402_1%~D
2
@
2
2 20K_0402_5%~D
2 20K_0402_5%~D
1M_0402_5%~D
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
@ R227
56_0402_1%~D
1
1
R224 1
R225 1
R226
RTCX1
RTCX2
1
+RTC_CELL
F25
G25
RTC
LPC
Keep ME RTC Registers
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
U79A
ICH_RTCX2
LAN / GLAN
CPU
Open
R223
0_0402_5%~D
1
1
2
12P_0402_50V8J~D
2
C297
IHDA
Clear ME RTC Registers
ICH_LAN100_SLP
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
SATA
Shunt
1
1
Y1
32.768K_12.5P_1TJS125DJ4A420P~D
ME_CLR1 TPM setting
C
ICH_INTVRMEN
R222
10M_0402_5%~D
2
Keep CMOS
ICH_RTCX1
1
3
Open
2
C296
12P_0402_50V8J~D
4
Clear CMOS
2
CMOS setting
Shunt
1
CMOS_CLR1
ICH9M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)
2
1 GLAN_DOCK#
10K_0402_5%~D
2
R221
D
@ R220
0_0402_5%~D
1
@ R219
0_0402_5%~D
+3.3V_ALW_ICH
LAN100_SLP
2
ICH_INTVRMEN
2
2
R217
332K_0402_1%~D
Port 1(X4)
ICH_GPIO53 <22>
PCIe Port Configuration 2 (Ports 1-4)
ICH_GPIO53
Ports Routing
1
A
Port 5(X1), Port 6(X1) default
Title
ICH9-M(2/4)
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
23
of
57
5
4
+3.3V_RUN
3
2
1
+3.3V_ALW_ICH
+3.3V_RUN
+3.3V_RUN
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
K4
AB20
C19
AB17
AC17
AD17
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
PERN1
PERP1
PETN1
PETP1
MiniWLAN (Mini Card 2)--->
<21>
<21>
<21>
<21>
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
C320 1
C321 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
P25
P24
P21
P22
PERN2
PERP2
PETN2
PETP2
N23
N24
M21
M22
PERN3
PERP3
PETN3
PETP3
M25
M24
L24
L23
PERN4
PERP4
PETN4
PETP4
K24
K25
K21
K22
PERN5
PERP5
PETN5
PETP5
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6
PCIE_ITX_GLANRX_P6
H24
H25
J24
J23
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
ICH_EC_SPI_CLK
ICH_SPI_CS0#_R
ICH_SPI_CS1#_R
E24
E23
F23
ICH_EC_SPI_DO
ICH_EC_SPI_DIN
F22
G23
Express card--->
<28>
<28>
<28>
<28>
<21>
<21>
<21>
<21>
10/100/1G LAN --->
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4_C
PCIE_ITX_EXPRX_P4_C
C1008 1
C1009 1
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6_C
PCIE_ITX_GLANRX_P6_C
1
<22> ICH_SPI_CS1#
Flash ROM
4@ C328
1
2
1
VCC
8
/HOLD
7
2
DO
3
/WP
CLK
6
4
GND
DIO
5
0.1U_0402_16V4Z~D
R299
3.3K_0402_5%~D
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
R294
33_0402_5%~D
ICH_SPI_CS0#
1
2
ICH_SPI_CS1#
1
2
R295
33_0402_5%~D
<21> USB_OC0_1#
<29> ESATA_USB_OC#
SPI_HOLD#
2
2
SA00001OZ0L
R301
SPI_CLK_R1 1
33_0402_5%~D
2 ICH_EC_SPI_CLK
SPI_DO_R1 1
R302
2 ICH_EC_SPI_DO
33_0402_5%~D
+3.3V_LAN
A
2
33_0402_5%~D
1 @ R306 2 SPI_DIN_R2
SPI_AMT_WE#
2
0_0402_5%~D
SPI_WP#_SEL
1
For iAMT
@ U13
1 CS#
2 SO
3 WP#
4 GND
VCC
HOLD#
SCLK
SI
8
7
6
5
@ C329 0.1U_0402_16V4Z~D
1
2
@
R305
3.3K_0402_5%~D
SPI_AMT_HOLD#
33_0402_5%~D
SPI_CLK_R2 1 @ R308 2 ICH_EC_SPI_CLK
SPI_DO_R2 1
2 ICH_EC_SPI_DO
R309 @
33_0402_5%~D
2
1
W25X32VSSIG_SO8~D
@
R304
3.3K_0402_5%~D
W25X16-VSSIG_SO8~D
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4
PCIE_ITX_EXPRX_P4
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
C326 1
C327 1
200 MIL SO8
ICH_EC_SPI_DIN1
2 SPI_DIN_R1
R300
1
233_0402_5%~D SPI_WE#
R1108
0_0402_5%~D
SPI_WP#_SEL
SPI_WP#_SEL <33>
SLP_M#
B23
SIO_SLP_M#
CL_CLK0
CL_CLK1
C22
A18
CL_CLK0
ICH_CL_CLK1
CL_DATA0
CL_DATA1
E22
B18
CL_DATA0
ICH_CL_DATA1
CL_VREF0
CL_VREF1
F21
A17
+CL_VREF0_ICH
+CL_VREF1_ICH
CL_RST0#
CL_RST1#
C17
B17
CL_RST0#
ICH_CL_RST1#
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
A22
E16
A15
D21
PCIE_MCARD1_DET#
ME_SUS_PWR_ACK
AC_PRESENT
ME_WOL_EN
2
ICH_LAN_RST#
CLK_PWRGD <6>
ICH_CL_PWROK <10,34>
SIO_SLP_M# <34>
CL_CLK0 <10>
ICH_CL_CLK1 <21>
USB_OC0_1#
USB_OC2#
ESATA_USB_OC#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
USB_OC10#
USB_OC11#
2
1
R303
22.6_0402_1%~D
USBRBIAS
Within 500 mils
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
W23
W24
V21
V22
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
Y24
Y25
Y21
Y22
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AB24
AB25
AA23
AA24
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
T21
T22
CLK_PCIE_ICH#
CLK_PCIE_ICH
USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#
P4
N4
N1
P5
P1
P2
M3
M2
P3
R1
R4
R2
USB
AE5
AD5
AE2
AD1
AD3
AD4
AC2
AC3
AC5
AB4
AB2
AB1
AA3
AA2
Y1
Y2
W2
W3
V1
V2
Y5
Y4
U3
U2
V4
V5
4
1
SATA
GPIO
V25
V24
U24
U23
DMI_ZCOMP
DMI_IRCOMP
2
C312
4.7P_0402_50V8C~D
C
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
AB21
AB22
1
CL_RST0#
<10>
ICH_CL_RST1# <21>
2@
PCIE_MCARD1_DET# <21>
ME_SUS_PWR_ACK <34>
AC_PRESENT <34>
ME_WOL_EN <34>
1
2
@ R284
10K_0402_5%~D
DMI_CLKN
DMI_CLKP
R279
10_0402_5%~D
CL_DATA0 <10>
ICH_CL_DATA1 <21>
SPI_WE#
SPI_DIN_R1
+3.3V_ALW_ICH
ICH_SPI_CS0#
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
<10>
<10>
<10>
<10>
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
<21>
<21>
<40>
<40>
USBP3- <29>
USBP3+ <29>
USBP4- <21>
USBP4+ <21>
USBP5- <40>
USBP5+ <40>
USBP6- <30>
USBP6+ <30>
USBP7- <28>
USBP7+ <28>
USBP8- <31>
USBP8+ <31>
USBP9- <31>
USBP9+ <31>
USBP10- <32>
USBP10+ <32>
USBP11- <19>
USBP11+ <19>
1
3
5
7
9
11
14
16
18
G2 G1
G4 G3
G6 G5
13
15
17
+CL_VREF1_ICH
2
+1.5V_RUN_PCIE_ICH
24.9_0402_1%~D
USBP0USBP0+
USBP1USBP1+
1
3
5
7
9
11
SPI_DO_R1
SPI_CLK_R1
SPI_HOLD#
+3.3V_LAN
+3.3V_WLAN
Within 500 mils
USBP0USBP0+
USBP1USBP1+
2
4
6
8
10
12
The same MDC connector
for TAA module
TYCO_1-179373-2
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
DMI_IRCOMP 1
R292
JP6
2
4
6
8
10
12
TYCO_5-1775013-4~D
1
----->Right Side Top
2
----->BLT mode
----->Left Side Top
----->WLAN
----->WWAN
----->BT
ICH_SMBDATA 6
----->Express Card
----->DOCK
----->DOCK +3.3V_M
----->BIO
ICH_SMBCLK 3
-----Camera
+3.3V_M
1
+3.3V_M
+CL_VREF0_ICH
1
2
B
MEM_SDATA
MEM_SDATA
<16,17>
MEM_SCLK
<16,17>
Q27A
2N7002DW-T/R7_SOT363-6~D
MEM_SCLK
4
Q27B
2N7002DW-T/R7_SOT363-6~D
ICH_EC_SPI_DIN1
R307
2 ICH_SPI_DIN_R
0_0402_5%~D
Follow Daisy Chain and Star
Topology. Place close to U10
pinE23 within 500mils
Title
ICH9-M(3/4)
Size
3
2
Document Number
Rev
1.0
LA-4151P
Date:
5
Place closely pin U79.AB5
ICH_CL_PWROK
1
CLK_PWRGD
T4
Clocks
T25
T24
R24
R23
4@ U12
1 /CS
U1
CLPWROK
ICH_RSMRST# <34>
R297
2.2K_0402_5%~D
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
ICH_SPI_CS0#
CK_PWRGD
ICH_LAN_RST# <34>
R296
2.2K_0402_5%~D
MiniWWAN (Mini Card 1)--->
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
R298
3.3K_0402_5%~D
ICH_RSMRST#
U79D
C317 1
C319 1
+3.3V_LAN
ICH_LAN_RST#
D19
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
10K_1206_8P4R_5%~D
USB_OC9#
1
2
R288
10K_0402_5%~D
USB_OC10#
1
2
R291
10K_0402_5%~D
USB_OC8#
1
2
R293
10K_0402_5%~D
D22
RSMRST#
@
1
SIO_EXT_SCI#
TPM_ID
USB_OC0_1#
USB_OC2#
ESATA_USB_OC#
USB_OC4#
4
3
2
1
LAN_RST#
CLK_ICH_14M
SIO_PWRBTN# <34>
2
TP12
<21>
<21>
<21>
<21>
10K_1206_8P4R_5%~D
RP2
USB_OC5#
5
4
USB_OC6#
6
3
USB_OC7#
7
2
USB_OC11#
8
1
ICH_SPI_CS1#
ICH_SPI_DIN_R
1
@ R1109
SMB
VRMPWRGD
A19
Place closely pin U79.K1
+3.3V_ALW_ICH
2
2 DMI_TERM_SEL
1K_0402_5%~D
SIO_PWRBTN#
<10,45>
1
+3.3V_ALW_ICH
8.2K_0402_5%~D
R287
3.24K_0402_1%~D
B
1
@ R789
U4
2
R275
1
+3.3V_ALW_ICH
RP1
5
6
7
8
1
@ R811
2 ITP_DBRESET#
100K_0402_5%~D
B24
ICH_TP11
PCI-Express
2
@ R283
10_0402_5%~D
Option to " Disable "
clkrun. Pulling it
down
will keep the clks
running.
IMVP_PWRGD
SPKR
MCH_ICH_SYNC#
ICH_RSVD_TP3
ICH_TP8
ICH_TP9
ICH_TP10
PWRBTN#
SPI
1
CLKRUN#
<21>
SPKR
<10> MCH_ICH_SYNC#
<23> ICH_RSVD_TP3
PAD~D T50
PAD~D T51
PAD~D T52
TPM
ICH_BATLOW#
2
No TPM or TCM
C16
R290
453_0402_1%~D
1
BATLOW#
C325
0.1U_0402_16V4Z~D
0
1
WAKE#
SERIRQ
THRM#
1
1
1
2
R282
8.2K_0402_5%~D
C21
L4
AD20
D
ICH_PWRGD <10,37>
DPRSLPVR
2
RSVD
DPRSLPVR
R286
3.24K_0402_1%~D
1
+3.3V_RUN
M1
DPRSLPVR/GPIO16
1
0
TCM
CLKRUN#/GPIO32
2
C
@ C313
47P_0402_50V8J~D
High = No Reboot
M5
T130 PAD~D
2
100K_0402_5%~D
2
100K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
100K_0402_5%~D
R289
453_0402_1%~D
0
SPKR
ICH_PWRGD
1
0
Function
ICH_GPIO26
D23
C318
4.7P_0402_50V8C~D
2
GPIO6
E14
PWROK
2
2
GPIO60
S4_STATE#/GPIO26
SIO_SLP_S3# <33>
SIO_SLP_S4# <10,34>
SIO_SLP_S5# <34>
ICH_CL_PWROK 1
R250
DPRSLPVR
1
@ R253
ICH_PWRGD
1
R257
ICH_RSMRST# 1
R260
ME_WOL_EN
1
R263
5
Low = Default
STP_PCI#/GPIO15
STP_CPU#/GPIO25
Direct Media Interface
No Reboot Strap
SMBALERT#/GPIO11
B15
A20
AE16
AE18
AD18
SIO_EXT_SMI#
B25
<34> SIO_EXT_SMI#
LAN_DISABLE#
C14
<21> LAN_DISABLE#
CONTACTLESS_DET#
D20
<32> CONTACTLESS_DET#
SNIFFER_DET#
AE17
K3
ICH_GPIO20
AC8
PAD~D T132
AC19
D17
E20
SATA_CLKREQ#
M4
1
<6> SATA_CLKREQ#
ODD_DET#
AB18
<26> ODD_DET#
WPAN_RADIO_DIS_MINI# AC18
PAD~D T48
HDD_DET#
AB19
<26> HDD_DET#
2
DMI_TERM_SEL
AC20
A16
<34> SIO_EXT_SCI#
<33> SIO_EXT_WAKE#
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
1
R276
10K_0402_5%~D
Stuff = Enable
D18
B20
D16
CLK_ICH_14M <6>
CLK_ICH_48M <6>
T44 PAD~D
HDD_DET#
C324
0.1U_0402_16V4Z~D
PAD~D T45
A23
H_STP_PCI#
H_STP_CPU#
ICH_PCIE_WAKE#
IRQ_SERIRQ
RSV_THRM#
SLP_S3#
SLP_S4#
SLP_S5#
PMSYNC#/GPIO0
SMB_ALERT#
CLKRUN#
ICH_SUSCLK
R285
10_0402_5%~D
<30>
1
<33,37,45,47> IMVP_PWRGD
No stuff = Disable
L2
R3
CLK14
CLK48
BT_DET#
2
100K_0402_5%~D
1
100K_0402_5%~D
2
100K_0402_5%~D
2
iTPM function
R270
PM_SYNC#
SUSCLK
SPEAKER_DET# <29>
1
R836
2
R760
1
R759
ODD_DET#
2
<33> ICH_PCIE_WAKE#
<27,30,32,33,34> IRQ_SERIRQ
SUS_STAT#/LPCPD#
SYS_RESET#
CLK_ICH_14M
CLK_ICH_48M
BT_DET#
1
<27,30,33,34> CLKRUN#
RI#
T5
C25
K1
AB5
CLK_ICH_48M
2
<6> H_STP_PCI#
<6> H_STP_CPU#
C20
SUS_STAT#/LPCPD#
ITP_DBRESET#
BT_DET#
SPEAKER_DET#
1
<10> PM_SYNC#
I CH_RI#
2
8.2K_0402_5%~D
AE19
AA18
AE20
AA20
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SYS GPIO
Power MGT
PAD~D T163
<7> ITP_DBRESET#
1
R256
MISC
GPIO
Controller Link
2
1
TPM_ID
<34> AMT_SMBCLK
<34> AMT_SMBDAT
U79C
C18 SMBCLK
C15 SMBDATA
B21 LINKALERT#/GPIO60/CLGPIO4
E18 SMLINK0
A24 SMLINK1
ICH_SMBCLK
ICH_SMBDATA
ICH_GPIO60
AMT_SMBCLK
AMT_SMBDAT
R271
10K_0402_5%~D
2 CONTACTLESS_DET#
100K_0402_5%~D
1
R822
+3.3V_RUN
2
2 ICH_EC_SPI_DO
1K_0402_5%~D
2 ICH_SMBCLK
2.2K_0402_5%~D
2 ICH_SMBDATA
2.2K_0402_5%~D
2 ICH_CL_RST1#
10K_0402_5%~D
2 AMT_SMBCLK
10K_0402_5%~D
2 AMT_SMBDAT
10K_0402_5%~D
2 I CH_RI#
10K_0402_5%~D
1 ICH_PCIE_WAKE#
10K_0402_5%~D
1 ME_SUS_PWR_ACK
10K_0402_5%~D
2 SIO_EXT_SMI#
10K_0402_5%~D
2 ICH_GPIO60
10K_0402_5%~D
2 SMB_ALERT#
10K_0402_5%~D
LAN_DISABLE#
2
10K_0402_5%~D
2 ICH_GPIO60
10K_0402_5%~D
1
1
@ R270
+3.3V_ALW_ICH
1
R252
1
R255
1
@ R259
1
R262
1
R265
1
R267
2
R268
2
R269
1
R274
1
8@ R787
1
R192
1
@ R1065
1
1@ R1111
7@ R988
100K_0402_5%~D
2 IMVP_PWRGD
2.2K_0402_5%~D
2 MCH_ICH_SYNC#
10K_0402_5%~D
2 RSV_THRM#
8.2K_0402_5%~D
1 IRQ_SERIRQ
10K_0402_5%~D
2 SPKR
1K_0402_5%~D
2 SPEAKER_DET#
100K_0402_5%~D
2 SNIFFER_DET#
100K_0402_5%~D
2 SIO_EXT_SCI#
10K_0402_5%~D
3@ R987
100K_0402_5%~D
D
1
@ R251
1
@ R254
1
R258
2
R261
1
@ R264
1
R834
1
@ R754
1
R272
+3.3V_LAN
Sheet
1
24
of
57
A
5
4
3
2
1
+RTC_CELL
1
2
V5REF_SUS
1
2
2
2
1
2
1
2
ICH_V5REF_SUS
VCCDMIPLL
P19
+VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
T17
U17
+VCC_DMI_ICH
V_CPU_IO[1]
V_CPU_IO[2]
V16
U16
VCC3_3[01]
V18
VCC3_3[02]
AE9
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
AA9
V14
W14
+1.5V_RUN_SATAPLL
C349 1
2
2
0.1U_0402_16V4Z~D
G8
H7
H8
1
PCI
+1.5V_RUN
1
2
4
VCCSUS1_5[1]
H16
VCCSUS1_5_ICH_1
VCCSUS1_5[2]
V7
VCCSUS1_5_ICH_2
2
TP_VCCSUS1.05_INT_ICH1
TP_VCCSUS1.05_INT_ICH2
1
2
+3.3V_RUN
1
2
+1.5V_ALW_HDA
T53 PAD~D
T122 PAD~D
2
T91
1
C357
0.1U_0402_16V4Z~D
+3.3V_RUN
W10
VCC1_5_A[07]
U15
V15
VCC1_5_A[08]
VCC1_5_A[09]
W18
VCC1_5_A[10]
G9
H9
VCC1_5_A[11]
VCC1_5_A[12]
V11
U11
VCC1_5_A[13]
VCC1_5_A[14]
U8
VCCUSBPLL
T9
U9
VCC1_5_A[15]
VCC1_5_A[16]
G11
H11
VCCLAN1_05[1]
VCCLAN1_05[2]
G12
H13
VCCLAN3_3[1]
VCCLAN3_3[2]
J17
VCCGLANPLL
H19
J18
VCCGLAN1_5[1]
VCCGLAN1_5[2]
K16
VCCPSUS
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCCPUSB
U12
V12
W12
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
G14
G15
H14
+3.3V_ALW_ICH
2
C360
0.1U_0402_16V4Z~D
+3.3V_ALW_ICH
VCCSUS3_3[04]
W8
VCCSUS3_3[05]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
J7
J8
K7
K8
L7
L8
M7
M8
N7
N8
P7
P8
VCCCL1_05
G18
VCCCL1_5
H17
VCCCL3_3[1]
VCCCL3_3[2]
J14
K14
1
2
VCCCL1_05_ICH 1
C366
VCCCL1_5
1
2
1
2
2
0.1U_0402_16V4Z~D
+3.3V_LAN
1
2
1
2
C369
0.1U_0402_16V4Z~D
2
T7
H15
C368
1U_0603_10V4Z~D
5
1
C373
4.7U_0603_6.3V6M~D
2
C372
2.2U_0603_6.3V6K~D
1
C371
10U_0805_4VAM~D
L17
1UH_20%_0805~D
VCCSUS1_05[1]
VCCSUS1_05[2]
2
B4
B7
B10
B13
B16
B19
B22
D2
D24
E5
E7
E9
E11
E13
E15
E17
E19
E21
F24
G2
G5
G10
G13
G16
G19
G21
H10
H12
H18
H23
J5
J9
J10
J11
J12
J13
J15
J21
J22
J25
K2
K9
K10
K11
K12
K13
K15
K17
K23
L5
L9
L10
L16
L17
L21
L22
L25
M9
M10
M12
M13
M14
M16
M17
M23
N2
N5
N9
N10
N12
N13
N14
N16
N17
N21
N22
N25
P9
P10
P12
P13
P14
P16
P17
P23
R5
R7
R8
R9
R10
R16
R17
R19
R21
R22
R25
T2
T8
T10
T11
T12
T13
T14
T15
T16
T23
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
U5
U10
W11
U14
W16
U21
U22
U25
V3
V8
V19
V23
W1
W4
W5
W7
W9
W15
W19
W21
W22
W25
Y3
Y23
AA1
AA4
AA6
AA8
AA11
AA13
AA15
AA16
AA17
AA19
AA21
AA22
AA25
AB3
AB9
AB11
AB13
AB15
AC24
AC1
AC4
AC10
AC12
AC14
AD2
AD6
AD9
AD16
AD19
AD22
AE3
AE4
AE11
AE13
AE15
V17
AE8
V9
J16
D
C
B
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
A1
A25
AE1
AE25
A
GLAN POWER
+1.5V_RUN
2
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
2
1
C363
0.1U_0402_16V4Z~D
+VCCGLANPLL
1
U13
V13
W13
2
C362
0.022U_0402_16V7K~D
+1.5V_RUN
V10
C361
0.022U_0402_16V7K~D
VCCLAN1.05_INT_ICH
1
2
C370
0.1U_0402_16V4Z~D
VCCSUSHDA
USB CORE
A
C1111
1U_0603_10V4Z~D
2
C367
0.1U_0402_16V4Z~D
1
C364
0.1U_0402_16V4Z~D
2
+3.3V_LAN
C365
0.1U_0402_16V4Z~D
1
2
2
VCCSATAPLL
ATX
2
C359
1U_0603_10V4Z~D
1
1
C352
0.1U_0402_16V4Z~D
1
2
+1.05V_VCCP
1
B
1
AD7
W17
ARX
2
C358
1U_0603_10V4Z~D
1
VCCHDA
1
1
C355
0.1U_0402_16V4Z~D
VCC3_3[06]
VCC3_3[07]
VCC3_3[08]
+3.3V_RUN
C354
0.1U_0402_16V4Z~D
2
+3.3V_RUN
C353
0.1U_0402_16V4Z~D
2
1
C351
1U_0603_10V4Z~D
C350
10U_0805_4VAM~D
1
2
+3.3V_RUN
1
VCCP_CORE
L16
10UH_LB2012T100MR_20%_0805~D
1
2
1
C348
0.1U_0402_16V4Z~D
VCCA3GP
+1.5V_RUN
5ohm@100MHz
1
2
+1.05V_VCCP
L15
C347
0.1U_0402_16V4Z~D
C
2
2
+1.5V_RUN
0.1U_0402_16V4Z~D
C346
C342
1U_0603_10V6K~D
1
L14
1
2
2
1
R312
1_0603_1%~D
C345
0.1U_0402_16V4Z~D
2
1
2
10_0805_5%~D
C344
4.7U_0603_6.3V6M~D
1
1
MMBD4148-7-F_SOT23-3~D
C343
4.7U_0603_6.3V6M~D
1
D16
RB751S40T1_SOD523-2~D
2
R313
100_0402_5%~D
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
1
+1.05V_1.5V_PSEQ
3
C341
10U_0805_4VAM~D
2
1
J19
K18
K19
L18
L19
M18
M19
N18
N19
P18
R18
T18
T19
U18
U19
L11
L12
L13
L14
L15
M11
M15
N11
N15
P11
P15
R11
R12
R13
R14
R15
C340
0.01U_0402_16V7K~D
1
V5REF
U7
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
C334
0.1U_0402_16V4Z~D
2
G7
ICH_V5REF_SUS
C339
2.2U_0603_6.3V6K~D
2
+3.3V_ALW_ICH
1
VCCRTC
I CH_V5REF_RUN
C338
22U_0805_6.3V6M~D
1
1
C333
0.1U_0402_16V4Z~D
G17
C337
22U_0805_6.3V6M~D
C336
220U_D2_4VY_R15M~D
C335
1U_0603_10V6K~D
R310
+1.05V_VCCP
U79F
+1.5V_RUN_PCIE_ICH
L13
+1.5V_RUN_PCIE_ICH
1
2
BLM21PG600SN1D_0805~D
+
+5V_ALW
2
+1.5V_RUN
2
+1.5V_RUN
I CH_V5REF_RUN
1
2
2
U79E
+1.05V_VCCP
D14
@
CORE
2
1
2
D15
RB751S40T1_SOD523-2~D
1
C332
0.1U_0402_16V4Z~D
D
R311
100_0402_5%~D
1
C331
0.1U_0402_16V4Z~D
+5V_RUN +3.3V_RUN
C330
1U_0603_10V4Z~D
1
VCCGLAN3_3
3
2
Title
ICH9-M(4/4)
Size
Document Number
Date:
Re v
1.0
LA-4151P
Sheet
1
25
of
57
4
3
2
1
For ODD
+5VMOD Source
5
2
<33> MODC_EN
1
1
Main SATA +5V Default
R319
100K_0402_5%~D
2
For HDD
Q31A
2N7002DW-T/R7_SOT363-6
TYCO_2-1759838-5_NR~D
Pleace near ODD CONN
1
2
S
+5V_MOD
+5V_RUN
PJP2
1
1
2
1
2
3
14
15
3
R318
100K_0402_5%~D
GND1
GND2
D Q29
SI3456BDV-T1-E3_TSOP6~D
G
2 MOD_EN
2
@ PAD-OPEN 4x4m
2
1
R316
100K_0402_5%~D
R317
100K_0402_5%~D
C379
10U_0805_10V4Z~D
DP
+5V
+5V
MD
GND
GND
+3.3V_ALW2
C378
0.1U_0603_50V4Z~D
8
9
10
11
12
13
D
+5V_ALW
Q31B
2N7002DW-T/R7_SOT363-6
close SATA connector
+15V_ALW
4
<23> SATA_ODD_IRX_DTX_P1_C
GND
RX+
RXGND
TXTX+
GND
2
2
1 SATA_ODD_IRX_DTX_N1
0.01U_0402_16V7K~D
1 SATA_ODD_IRX_DTX_P1
0.01U_0402_16V7K~D
ODD_DET#
<24> ODD_DET#
+5V_MOD
2
C374
2
C375
<23> SATA_ODD_IRX_DTX_N1_C
1
2
3
4
5
6
7
6
1
C377
0.1U_0402_16V4Z~D
2
<23> SATA_ODD_ITX_DRX_P1
<23> SATA_ODD_ITX_DRX_N1
C376
1000P_0402_50V7K~D
1
SATA_ODD_ITX_DRX_P1
SATA_ODD_ITX_DRX_N1
1
JSATA1
+5V_MOD
1
2
5
6
D
4
5
Open
JSATA2
HDD PWR
+5V_ALW
1
1
2
<33> HDDC_EN
Pleace near HDD CONN
S
+5V_HDD
2
1
2
2
@ PAD-OPEN 4x4m
1
1
+5V_RUN
PJP3
1
Open
+5V_HDD Source
+3.3V_ALW
1
2
5
6
2
R323
100K_0402_5%~D
Q34A
2N7002DW-T/R7_SOT363-6
Main SATA +5V Default
3
R322
100K_0402_5%~D
5
TYCO_1775770-1_RV
D Q32
G
HDD_EN_5V
2
2
R321
100K_0402_5%~D
23
24
C383
10U_0805_10V4Z~D
2
GND1
GND2
3
1
R320
100K_0402_5%~D
C382
0.1U_0603_50V4Z~D
2
+3.3V_ALW2
6
1
C
+15V_ALW
Q34B
2N7002DW-T/R7_SOT363-6
2
@ C388
0.1U_0402_10V7K~D
1
HDD_DET#
+5V_HDD
@ C387
0.1U_0402_16V4Z~D
2
@ C386
10U_0805_10V4Z~D
1
C385
0.1U_0402_16V4Z~D
2
C384
1000P_0402_50V7K~D
1
+3.3V_HDD
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
1
<24> HDD_DET#
+5V_HDD
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
close SATA connector
+3.3V_HDD
1
2
5
6
PSATA_IRX_DTX_N0
1
1 0.01U_0402_16V7K~D PSATA_IRX_DTX_P0
0.01U_0402_16V7K~D
C
4
2
C380 2
C381
GND
RX+
RXGND
TXTX+
GND
1
<23> PSATA_IRX_DTX_N0_C
<23> PSATA_IRX_DTX_P0_C
1
2
3
4
5
6
7
4
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
<23> PSATA_ITX_DRX_P0
<23> PSATA_ITX_DRX_N0
D Q117
G
3
B
S
4
+3.3V_HDD
1
R477
100K_0402_5%~D
2
PJP47
C79
10U_0805_10V4Z~D
1
+3.3V_RUN
1
2
B
2
@ PAD-OPEN 4x4m
Open
+3.3V_HDD Source
A
A
Title
5
4
3
2
ODD/HDD CONNECTOR
Size
Document Number
Date:
R ev
1.0
LA-4151P
Sheet
1
26
of
57
5
4
3
2
1
SD,MMC muti-function pin define
+3.3V_R5C833
U56
<6> CLK_PCI_PCM
<22,30> PCI_RST#
MSEN
XDEN
XI
XO
94
95
R5C833XI
R5C833XO
R885 1
<24,30,33,34> CLKRUN#
<33>
115
116
INTA#
INTB#
2 0_0402_5%~D
R886
1
2
SYS_PME#
@ 0_0402_5%~D
0_0402_5%~D
2
69
66
R812
2
2
1
R813
1
10K_0402_5%~D
B
100K_0402_5%~D
+3.3V_R5C833
99
102
103
107
111
97
UDIO0/SRIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
HWSPND#
TEST
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RSV
Layout Note: Place close to R5C833 Chip
72
60
56
65
59
57
T94
4
PAD~D
R1110 1
1
SDCLK_MSCLK_R
0_0402_5%~D
2
2
Layout Note:
Place close to R5C833
2
2
1
2
2
1
2
1
2
OUT
GND
OC#
EN
1
2
3
1
TPS2051BDBVR_SOT23-5~D
2
1
2
C1032
15P_0402_50V8J~D
1
2
C1056
IRQ_SERIRQ
UDIO4
UDIO5
4
13
22
28
54
62
63
68
118
122
<24,30,32,33,34>
+3.3V_R5C833
R889
10K_0402_5%~D
1
2
1
2
R984
100K_0402_5%~D
2
1
SDCCMD
MMCCMD
MDIO09
SDCCLK
MMCCLK
MDIO10
SDCDAT0
MMCDAT0
MDIO11
SDCDAT1
MMCDAT1
MDIO12
SDCDAT2
MMCDAT2
MDIO13
SDCDAT3
MMCDAT3
MDIO14
MMCDAT4
MDIO15
MMCDAT5
MDIO16
MMCDAT6
MDIO17
MMCDAT7
MDIO18
MDIO19
C
UDIO3
UDIO4
MSEN
XDEN
Function
Pull-up
Pull-up
Pull-up
Pull-up
Enable
SD,XD,MS,MMC Card
R5C833XI
1
2
C1058
15P_0402_50V8J~D
1
2
R5C833XO
R809
220_0402_5%~D
JSD1
Solve MS Duo Adaptor short problem
S
Q132
3 2N7002W-7-F_SOT323-3~D
1
XDEN
R976 10K_0402_5%~D
1
2
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
13
11
7
5
DAT4/MMC10
DAT5/MMC11
DAT6/MMC12
DAT7/MMC13
16
17
CD_WP_SW/GND
CD_WP_SW/GND
19
20
2
1
CD_SW/SD
WP_SW/SD
CD_SW_TAISOL/SD
WP/SW_TAISOL/SD
SDCD#_MMCDC#
SDWP#
SDCD#_MMCDC#
SDWP#
S
D
Q133
3 2N7002W-7-F_SOT323-3~D SDDATA2
1
18
2
G
R975 10K_0402_5%~D
1
2
DAT3/SD1
CMD/SD2
VSS1/SD3
VCC/SD4
CLK/SD5
GND/VSSS2/SD6
DAT0/SD7
DAT1/SD8
DAT2/SD9
SDDATA1
2
G
SDDATA2_MSDATA2
MSEN
SDDATA0_MSDATA0
SDDATA1
SDDATA2
14
12
10
9
8
6
4
3
15
+3.3V_RUN_CARD
SDCLK_MSCLK_R
SDDATA1_MSDATA1
TPB0+
SDEXTCK
MDIO08
SDDATA3_MSDATA3
SDCMD_MSBS
MSEN Pull-Up : MS Enabled
MSEN Pull-Down: MS Disabled
TPA0-
MDIO07
Y2
24.576MHZ_12PF_1YG24576CE1C~D
D
1
2
1
2
2
0.33U_0603_10V7K~D
C1045
0.01U_0402_16V7K~D
C1044
56.2_0402_1%~D
R815
56.2_0402_1%~D
R814
TPA0+
2
+15V_ALW
R923
1
only for MMC/SD
1
3
1
2
2
SDCD#_MMCDC#
D
S Q134
2N7002W-7-F_SOT323-3~D
2
G
A
5.1K_0402_1%~D
1
1
2
56.2_0402_1%~D
C1052
1
R891
R985
56.2_0402_1%~D 270P_0402_50V7K~D
R890
2
Title
CardBus Controller(R5C833)
Size
4
3
2
Document Number
Rev
1.0
LA-4151P
Date:
5
GND_SW
2
10K_0402_5%~D
XDEN Pull-Up : xD Enabled
XDEN Pull-Down: xD Disabled
B
T-SOL_156-4000000901_NR
TPB0-
A
D
MMCLED#
Function set pin define
R5C833-TQFP128P_TQFP128_14X14~D
1
2
+3.3V_RUN_CARD
TPBIAS0
1
1
MMCPWR
Layout Note: Place close to
R5C833 and Shield GND
@
0.01U_0402_16V7K~D 1
C1055
<22> PCI_PIRQD#
<22> PCI_PIRQC#
R808 1
<33> CB_HWSPND#
FIL0
REXT
VREF
96
101
100
SDLED#
R413
150K_0402_5%~D
58
55
MDIO06
C506
1U_0603_10V4Z~D
1
2
PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#
SDPWR1
C505
0.1U_0402_16V4Z~D
121
119
71
117
70
SDPWR0
MDIO05
2
REQ#
GNT#
CLK_PCI_PCM
PCI_RST#
BUS_GRST#
CARD_EN
SDCMD_MSBS
SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
SDWP#
MDIO04
1
124
123
2
1
R1029
+3.3V_RUN
0_0805_5%~D U28
5 IN
1
2
2
1
2
1
MSEN
XDEN
2
PCI_REQ1#
PCI_GNT1#
<22> PCI_REQ1#
<22> PCI_GNT1#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
<21>
<21>
1
10K_0402_1%~D
33
23
25
24
29
26
8
30
31
TPB0+
TPB0-
2
R887
0.01U_0402_16V7K~D
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI _IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_IDSEL
PCI_PERR#
PCI_SERR#
<22> PCI_PAR
<22> PCI_FRAME#
<22> PCI_TRDY#
<22> PCI_IRDY#
<22> PCI_STOP#
<22> PCI_DEVSEL#
PCI_AD17
1
2
100_0402_5%~D
R895
<22> PCI_PERR#
<22> PCI_SERR#
<21>
<21>
SDWP#
CARD_EN
TP_SD/MMC/MS
MDIO03
0.47U_0402_10V4Z~D
2
TPA0+
TPA0-
1
C509
0.1U_0402_16V4Z~D
1
C/BE3#
C/BE2#
C/BE1#
C/BE0#
1
MMCCD#
MDIO02
C1025
0.47U_0402_10V4Z~D
SDCD#_MMCDC#
2
MMC Card
SDCD#
0_0805_5%~D
+3.3V_RUN_PHY
1
SD Card
MDIO00
MDIO01
+VCC_ROUT
L65
+3.3V_R5C833
Media I/F
2
C1024
0.01U_0402_16V7K~D
80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83
+3.3V_RUN
R888
1
C1053
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
2
+3.3V_R5C833
C1054
0.01U_0402_16V7K~D
TPB0+
TPB0-
2
1
10U_0805_6.3V6M~D
TPBP0
TPBN0
105
104
1
1000P_0402_50V7K~D
TPA0+
TPA0-
C1048
0.01U_0402_16V7K~D
109
108
2
C1030
0.1U_0402_16V4Z~D
TPAP0
TPAN0
2
1
C1047
0.01U_0402_16V7K~D
TPBIAS0
1
C1029
0.01U_0402_16V7K~D
113
C1046
0.01U_0402_16V7K~D
TPBIAS0
2
C1028
10U_0805_6.3V6M~D
98
106
110
112
2
1
C1059
0.01U_0402_16V7K~D
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
2
2
1
C1027
7
21
35
45
2
1
2
C1010
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
C1057
10P_0402_50V8J~D
<22>
<22>
<22>
<22>
1
+3.3V_RUN_PHY
2
1
C1041
0.01U_0402_16V7K~D
2
R803
10_0402_5%~D
C
1
67
86
2
+3.3V_R5C833
1
10U_0805_6.3V6M~D
C1026
CLK_PCI_PCM
1U_0603_10V6K~D
@ 0_0402_5%~D
VCC_3V
VCC_MD3V
+VCC_ROUT
1
C1043
0.01U_0402_16V7K~D
BUS_GRST#
2
61
16
34
64
114
120
1
C1042
0.1U_0402_16V4Z~D
1
<33> CBUS_GRST#
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
+3.3V_R5C833
10U_0805_6.3V6M~D
R802
VCC_RIN
10
20
27
32
41
128
C1051
0.01U_0402_16V7K~D
R801
47K_0402_1%~D
R5C833
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
C1049
D
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C1050
0.01U_0402_16V7K~D
+3.3V_R5C833
125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
C1040
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
1
<22> PCI_AD[0..31]
Sheet
1
27
of
57
5
4
3
2
1
+1.5V_CARD
+1.5V_RUN
2
2
1.5Vin
1.5Vin
2
4
3.3Vin
3.3Vin
17
PLTRST1#
<10,22> PLTRST1#
1
R657
1
R683
1
R684
1
R790
<33> EXPRCRD_STDBY#
+3.3V_SUS
2
100K_0402_5%~D
2
0_0402_5%~D
2
100K_0402_5%~D
2
100K_0402_5%~D
AUX_IN
6
1.5Vout
1.5Vout
11
13
3.3Vout
3.3Vout
3
5
AUX_OUT
15
OC#
19
SYSRST#
20
SHDN#
PERST#
EXPRCRD_STBY_R#
1
STBY#
NC
EXPRCRD_PWREN#
10
CPPE#
GND
CPUSB#
9
1
2
+3.3V_CARDAUX
8
1
16
2
7
CPUSB#
18
<33> EXPRCRD_PWREN#
2
1
2
1
2
C1006
0.1U_0402_16V4Z~D
+3.3V_SUS
2
U52
12
14
D
+3.3V_CARD
C1003
10U_0805_6.3V6M~D
1
1
C1002
0.1U_0402_16V4Z~D
C135
0.1U_0402_16V4Z~D
2
C134
0.1U_0402_16V4Z~D
1
1
C1001
0.1U_0402_16V4Z~D
C997
0.1U_0402_16V4Z~D
1
C1000
0.1U_0402_16V4Z~D
+3.3V_SUS +3.3V_RUN
C999
0.1U_0402_16V4Z~D
D
RCLKEN
CARD_RESET#
R5538_QFN20~D
C
C
Express Card
+1.5V_CARD: Max. 650mA, Average 500mA
+3.3V_CARD: Max. 1300mA, Average 1000mA
+1.5V_CARD
1
R791
2
0_0402_5%~D
1
@ R792
4 4
2
0_0402_5%~D
3 3
@
<24> USBP7-
1
<24> USBP7+
1
2
1
2
USBP7_DDET_PCCRD_EXPSCRD#
1
2
3
CPUSB#
4
5
6
EXP_SMBCLK
7
EXP_SMBDATA
8
9
10
PCIE_WAKE#
11
12
CARD_RESET#
13
14
15
16
EXPRCRD_PWREN#
17
CLK_PCIE_EXP#
18
CLK_PCIE_EXP
19
20
PCIE_IRX_EXPTX_N4
21
PCIE_IRX_EXPTX_P4
22
23
PCIE_ITX_EXPRX_N4_C 24
PCIE_ITX_EXPRX_P4_C 25
26
27
28
USBP7_D+
2
L64
DLW21SN900SQ2_0805~D
B
<21,33> PCIE_WAKE#
1
2
1
2
2
2
+3.3V_CARD
<6> EXPCLK_REQ#
1
2
EXP_SMBDATA
C1005
0.1U_0402_16V4Z~D
R127
2.2K_0402_5%~D
1
R126
2.2K_0402_5%~D
6
<21,34> CARD_SMBDAT
1
C1004
0.1U_0402_16V4Z~D
+3.3V_CARDAUX
+3.3V_SUS
<6> CLK_PCIE_EXP#
<6> CLK_PCIE_EXP
<24> PCIE_IRX_EXPTX_N4
<24> PCIE_IRX_EXPTX_P4
<24> PCIE_ITX_EXPRX_N4_C
<24> PCIE_ITX_EXPRX_P4_C
Q112A
2N7002DW-T/R7_SOT363-6
5
+3.3V_SUS
<21,34> CARD_SMBCLK
3
C1007
0.1U_0402_16V4Z~D
<33> DET_PCCRD_EXPSCRD#
JEXP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
GND
B
TYCO_2-2041070-6
Q112B
2N7002DW-T/R7_SOT363-6
EXP_SMBCLK
4
A
A
Title
CardBus/SD card Socket
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
28
of
57
5
4
3
2
USB PORT#
IO connector II
+5V_RUN
D
JBIO2
+3.3V_RUN
DAT_DDC2_CRT
CLK_DDC2_CRT
<20> DAT_DDC2_CRT
<20> CLK_DDC2_CRT
<24>
<24>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
USBP3USBP3+
USBP3USBP3+
+5V_ALW
31
32
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
GND
GND
GND
34
35
36
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
GND
GND
GND
RED_CRT
GREEN_CRT
BLUE_CRT
RED_CRT
<20>
GREEN_CRT <20>
BLUE_CRT <20>
HSYNC_CRT
VSYNC_CRT
HSYNC_CRT <20>
VSYNC_CRT <20>
ESATA_USB_OC#
ESATA_USB_PWR_EN#
ESATA_USB_OC# <24>
ESATA_USB_PWR_EN# <33>
ESATA_IRX_DTX_N4_C
ESATA_IRX_DTX_P4_C
ESATA_IRX_DTX_N4_C <23>
ESATA_IRX_DTX_P4_C <23>
ESATA_ITX_DRX_P4
ESATA_ITX_DRX_N4
ESATA_ITX_DRX_P4 <23>
ESATA_ITX_DRX_N4 <23>
TYCO_3-1775014-0~D
+3.3V_TP_PWR +5V_TP_PWR
1
2
3
4
5
6
7
8
+3.3V_TP_PWR
+5V_FP
D82
FP_USB_DFP_USB_D+
FPRESET#
1
1
2
+5V_TP_PWR
@ R873
0_0402_5%~D
3
FP_RESET# <32>
2
BKT_GPIO17 <35>
BAT54CW_SOT323~D
TYCO_2041070-6
1
2
C770
0.1U_0402_16V4Z~D
1
2
3
4
5
6
GND
GND
1
2
C1035
0.1U_0402_16V4Z~D
JBIO3
C
1
@
DESTINATION
0
JUSB1 (Ext Right Side Top)
1
BLT mode
2
NC
3
JESATA1 (Ext Left Side Bottom)
4
WLAN
5
WWAN
6
BT
7
Card Bus/Express card
8
DOCKING
9
DOCKING
10
USH->BIO
11
Camera
D
C
Place close to
JBIO1.1
U51
FP_USB_D<40> FP_SW_USBD+
1
R422
2
0_0402_5%~D
FP_USB_D+
<40> FP_SW_USBD-
1
R423
2
0_0402_5%~D
FP_USB_D-
1
GND IO2
3
2
IO1
4
VIN
FP_USB_D+
+3.3V_TP_PWR
PRTR5V0U2X_SOT143-4~D
B
B
JSPK1
LID_CL#
15 mils trace
+3.3V_ALW
<21> INT_SPK_L1
<21> INT_SPK_L2
<21> INT_SPK_R1
<21> INT_SPK_R2
<24> SPEAKER_DET#
INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2
2
1
2
10
11
@ C424
100P_0402_50V8J~D
2
1
@ C423
100P_0402_50V8J~D
1
@ C426
100P_0402_50V8J~D
2
@ C425
100P_0402_50V8J~D
1
C685
0.1U_0402_16V4Z~D
1
GND
GND
Speaker Connector
LID_CL#
2
1
2
3
4
5
6
7
8
9
MOLEX_53780-0919
A
<33,38> LID_CL#
1
2
3
4
5
6
7
8
9
A
Title
FingerFrint
Size
Date:
5
4
3
2
Document Number
Rev
1.0
LA-4151P
Sheet
1
29
of
57
5
4
3
2
1
China TPM
+3.3V_RUN
LOW:Power Down Mode
High:Working Mode
U24
<6> CLK_PCI_TPM_CHA
<23,32,33,34> LPC_LFRAME#
<22,27> PCI_RST#
<24,27,32,33,34> IRQ_SERIRQ
<24,27,33,34> CLKRUN#
PAD~D
T167
28
26
23
20
17
LPCPD#
LAD0
LAD1
LAD2
LAD3
21
22
16
27
15
7
9
8
TPM_PIN7
TPM_PIN9
TESTI
VDD_0
VDD_1
VDD_2
10
19
24
GND_11
GND_18
GND_25
GND_4
11
18
25
4
NC_3
NC_5
NC_12
NC_13
NC_14
3
5
12
13
14
GPIO1
GPIO2
GPIO_EXPRESS_00
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
TESTBI/BADD
TESTI
2
1
TPM_PIN3
TPM_PIN5
TPM_PIN12
TPM_PIN13
TPM_PIN14
1
1
2
9@
<6> CLK_TCM_14M
C1202
0.1U_0402_10V7K~D
9@
1
RUNMODE
PIN9
X
EE/EF
BA1
PIN3
0
BA0
PIN9
0
1
Base Address
TESTEN
PIN8
0
1
+3.3V_RUN
@
R1116
@
R1117
0
1
0
2E/2F
1
0
Normal mode
1
1
4E/4F
1
1
D
A0 USH B0 USH A0 w/CHINAB0 w/CHINA
Ref Des
Pull-up on LPC_EN_R
USH pin R6 LPCEN
R841
POP
@
POP
@
Pull-down on LPC_EN_R
USH pin R6 LPCEN
R483
@
POP
@
POP
@
3@ R464
@
POP
@
Series from EC to LPD#
EC to USH Pin P7 LPCPD_N
R466
@
@
@
@
Pull-up on LPD#
USH pin P7 LPCPD_N
R474
POP
POP
POP
POP
Pull-up on EC
SIO pin 105 OUT65
R788
@
@
@
@
Pull-down on China TPM
To China TPM U24 pin 28
1@ R892
@
@
POP
POP
POP
Series from EC to LPC_EN_R EC to USH Pin R6 LPCEN
1@ R893
Broadcom USH
U32 USH
U32
China TPM
U24 China TPM
1@ U24
@
@
POP
POP
POP
POP
POP
@
@
POP
POP
LPCBus Series Resistors
R705,R723,R724,R732,R733
3@
POP
POP
@
@
TPM_ID(Strap Low)
ICH9M GPIO6 Pin AH21
1@ R988
@
@
POP
POP
TPM_ID (Strap High)
ICH9M GPIO6 Pin AH21
3@ R987
POP
POP
@
@
1@ is for TCM
3@ is for Broadcom TPM only
9@ is for ZTE TCM
10@ is for Jetway TCM
C
TPM_PIN12
TPM_PIN5
2
TPM_PIN9
1(default)
BSEL
PIN12
0
FLASH
SRAM
C_TPM_LPC_EN
1
@
R1119
1K_0402_5%~D
2
C1203
0.1U_0402_10V7K~D
10@
1@ R892
4.7K_0402_5%~D
1
9@
R1118
1K_0402_5%~D
1
10K_0402_5%~D
2
10K_0402_5%~D
7E/7F
JTAG mode
Normal mode
PART/PIN
Series from EC to China PD# SIO to China Pin 28 LPCPD#
2
2
1
+3.3V_RUN
1
1@
Jetway
SSX35BCB_TSSOP28~D
STATUS
2
2
2 0_0402_5%~D
1
ZTE
2
1
1@
@ R383
10K_0402_5%~D
C
1
2
10@ R1115 1
2
1K_0402_5%~D
TPM_PIN3
1@
C487
10U_0603_6.3V6M~D
0_0402_5%~D
C_TPM_LPC_EN
2
1
<32,33> SP_TPM_LPC_EN
<23,32,33,34> LPC_LAD0
<23,32,33,34> LPC_LAD1
<23,32,33,34> LPC_LAD2
<23,32,33,34> LPC_LAD3
9@
R884
1
2
6
C486
0.1U_0402_16V4Z~D
1@ R893
PAD~D T164
PAD~D T165
TPM_PIN6
C485
0.1U_0402_16V4Z~D
T166
DESCRIPTION
C484
0.1U_0402_16V4Z~D
PAD~D
Lola USH and China TPM BOM Option
1@
2
Blue tooth
B
D
S
G
3
@
1
2
BT_RADIO_DIS#
USBP6+
USBP6BT_ACTIVE
<33> BT_RADIO_DIS#
<24>
USBP6+
<24>
USBP6<21,38> BT_ACTIVE
<24>
BT_DET#
BT_DET#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
13
14
TYCO_1-2041070-2
2
C1087
1
2
@ 100P_0402_50V8J~D
2
10K_0402_5%~D
1
1
1
2
1
2
3
<21> COEX1_BT_ACTIVE
<21> COEX2_WLAN_ACTIVE
R920
33P_0402_50V8J~D
2
4
1
6
JBT
COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
C1086
1
0.1U_0402_16V4Z~D
2
4
Q47
C551
4700P_0402_25V7K~D
1
C1085
1
R435
470K_0402_5%~D
R437
100K_0402_5%~D
@
B
+3.3V_RUN
+3.3V_WLAN
6
5
2
1
Q53B
2N7002DW-T/R7_SOT363-6~D
2
<34> AUX_EN_WOWL
R436
200K_0402_5%~D
5
Q53A
2N7002DW-T/R7_SOT363-6~D
R432
100K_0402_5%~D
2
+3.3V_ALW
R431
100K_0402_5%~D
1
+15V_ALW
2
D
A
A
5
4
3
2
Title
Blue Tooth
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
30
of
57
5
4
3
D
4
5
DPB_LANE_N0_C
7
DPB_LANE_P1_C
6
DPB_LANE_N1_C
8
RCLAMP0524P.TCT~D
<12> DPB_LANE_P2_C
<12> DPB_LANE_N2_C
@ D25
<12> DPB_LANE_P3_C
<12> DPB_LANE_N3_C
DPB_LANE_P2_C
1
10 DPB_LANE_P2_C
DPB_LANE_N2_C
2
9
DPB_LANE_N3_C
<12> DPB_LANE_P0_C
<12> DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
<12> DPB_LANE_P1_C
<12> DPB_LANE_N1_C
3
DPB_LANE_P3_C
DPB_LANE_P0_C
DPB_LANE_N0_C
4
7
5
6
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
<21> DPB_DOCK_AUX
<21> DPB_DOCK_AUX#
<21> DPB_DOCK_HPD
+NBDOCK_DC_IN_SS
<20> BLUE_DOCK
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_DOCK_HPD
BLUE_DOCK
3
8
<20> RED_DOCK
RED_DOCK
RCLAMP0524P.TCT~D
<20> GREEN_DOCK
GREEN_DOCK
@ D27
DPB_DOCK_AUX
1
10 DPB_DOCK_AUX
DPB_DOCK_AUX#
2
9
DPB_DOCK_AUX#
7
DPB_DOCK_HPD
DPB_DOCK_HPD
DPB_DOCK_CA_DET
C
4
5
6
<20> HSYNC_DOCK
<20> VSYNC_DOCK
<34> CLK_MSE
<34> DAT_MSE
DPB_DOCK_CA_DET
<21> DAI_BCLK#
<21> DAI_LRCK#
3
<21>
<21>
8
RCLAMP0524P.TCT~D
DAI_DI
DAI_DO#
<21> DAI_12MHZ#
Place close to JDOCK1 connector
<33>
<33>
D_LAD0
D_LAD1
<33>
<33>
D_LAD2
D_LAD3
<33> D_LFRAME#
<33> D_CLKRUN#
<33> D_SERIRQ
<33> D_DLDRQ1#
<6> CLK_PCI_DOCK
<34> DOCK_SMB_CLK
<34> DOCK_SMB_DAT
<34,41> DOCK_SMB_ALERT#
<41> DOCK_PSID
<34> DOCK_PWR_BTN#
SLICE_BAT_PRES#
<33,41,48> SLICE_BAT_PRES#
B
SM24.TCT_SOT23-3~D
2
1
0.1U_0603_50V4Z~D
1
D73
C1034
2
3
+DOCK_PWR_BAR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
146
147
148
GND1
PWR1
PWR1
PWR1
153
154
155
156
157
158
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
PWR2
PWR2
PWR2
GND2
149
150
151
152
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
159
160
161
162
163
164
DOCK_AC_OFF
@D22
DOCK_AC_OFF <33,48>
DOCK_LOM_SPD100LED_ORG# <21>
DPC_DOCK_CA_DET <21>
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
DPC_DOCK_AUX_SW
DPC_DOCK_AUX#_SW
DPC_DOCK_HPD_R
DPC_LANE_P0_C <12>
DPC_LANE_N0_C <12>
DPC_LANE_P1_C <12>
DPC_LANE_N1_C <12>
DPC_LANE_P0_C
1
10 DPC_LANE_P0_C
DPC_LANE_N0_C
2
9
DPC_LANE_N0_C
DPC_LANE_P1_C
4
7
DPC_LANE_P1_C
DPC_LANE_N1_C
5
6
DPC_LANE_N1_C
DPC_LANE_P2_C <12>
DPC_LANE_N2_C <12>
8
RCLAMP0524P.TCT~D
DPC_LANE_P3_C <12>
DPC_LANE_N3_C <12>
@D24
DPC_DOCK_AUX_SW <21>
DPC_DOCK_AUX#_SW <21>
DPC_DOCK_HPD_R <21>
ACAV_DOCK_SRC# <48>
DAT_DDC2_DOCK <20>
CLK_DDC2_DOCK <20>
SATA_SBRX_DTX_P3
2
SATA_SBRX_DTX_N3 C586 2
C587
D
3
DPC_LANE_P2_C
1
10 DPC_LANE_P2_C
DPC_LANE_N2_C
2
9
DPC_LANE_N2_C
DPC_LANE_P3_C
4
7
DPC_LANE_P3_C
DPC_LANE_N3_C
5
6
DPC_LANE_N3_C
3
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
SATA_SBRX_DTX_P3_C <23>
SATA_SBRX_DTX_N3_C <23>
8
RCLAMP0524P.TCT~D
SATA_SBTX_C_DRX_P3 <23>
SATA_SBTX_C_DRX_N3 <23>
@D26
USBP8+ <24>
USBP8- <24>
DPC_DOCK_AUX_SW
USBP9+ <24>
USBP9- <24>
CLK_KBD <34>
DAT_KBD <34>
10 DPC_DOCK_AUX_SW
1
DPC_DOCK_AUX#_SW 2
9
DPC_DOCK_AUX#_SW
DPC_DOCK_HPD_R
4
7
DPC_DOCK_HPD_R
DPC_DOCK_CA_DET
5
6
DPC_DOCK_CA_DET
C
3
8
RCLAMP0524P.TCT~D
Place close to JDOCK1 connector
BREATH_LED# <34,38>
DOCK_LOM_ACTLED_YEL# <21>
DOCK_LOM_TRD0+ <21>
DOCK_LOM_TRD0- <21>
+RTC_CELL
DOCK_LOM_TRD1+ <21>
DOCK_LOM_TRD1- <21>
TR0/1CT
TR2/3CT
DOCK_DET#
2
@ R124
+LOM_VCT
DOCK_LOM_TRD2+ <21>
DOCK_LOM_TRD2- <21>
1
100K_0402_5%~D
+3.3V_ALW
2
R1075
DOCK_LOM_TRD3+ <21>
DOCK_LOM_TRD3- <21>
1
100K_0402_5%~D
DOCK_DCIN_IS+ <46>
DOCK_DCIN_IS- <46>
D77
RB751S40T1_SOD523-2~D
1
2 DOCK_DET#
DOCK_POR_RST# <34>
DOCK_DET#_R
CLK_PCI_DOCK
DOCK_DET#
<33>
1
DPB_LANE_N1_C
9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
B
@ R462
10_0402_5%~D
+DOCK_PWR_BAR
@ R1076
910K_0402_5%~D
1
2
2
DPB_LANE_P1_C
2
DOCK_DET_1
<21> DOCK_LOM_SPD10LED_GRN#
<21> DPB_DOCK_CA_DET
1
DPB_LANE_N0_C
JDOCK1
10 DPB_LANE_P0_C
1
1
C1033
0.1U_0603_50V4Z~D
1
2
@ D23
DPB_LANE_P0_C
2
2
@C590
4.7P_0402_50V8C~D
JAE_WD2F144WD3
A
A
Title
5
4
3
2
DOCKING CONN
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
31
of
57
2
D
C
RESET#
S#
Q
VSS
VCC
W#
8
7
6
5
1
SPI_RXD
BCM5880_GPIO15
M45PE16-VMP6TP_SO8~D
2
1
L72
RFREADER_RXP
1
R498
2 RFREADER_RXP_F1
3K_0402_1%~D
C643
2RFREADER_TXP1 1
1U_0603_10V6K~D1
2
@
2
RFTAG_VRXN
2
2
1
2
1
2
RFTAG_VRXP
1
2
1
2
BAS40-04_SOT23-3~D
3
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Hardware enable for USH TPM:Populate D70 & R841,
No Stuff R483.
Hardware disable for USH TPM:No Stuff D70 &
R841, Populate R483
1
+3.3V_RUN
1
A
RFREADER_TXN1_P1
1
R496
1
R497
150NH_LLQ1608-FR15G_2%~D
2
1
2
1
2
1
2
2
1
1
2
1
1
1
2
3
4
2
UART LPC
SPI
U34
SPI_TXD
SPI_CLK
SPI_RST
SPI_CS
1
2
D29
JCS1
2 RFTAG_VRXN_F
1
2 ANT_RFTAG_VRXN_R
4.12K_0402_1%~D C640
1U_1206_100V4Z~D
2 RFTAG_VRXP_F
1
2 ANT_RFTAG_VRXP_R
4.12K_0402_1%~D C642
1U_1206_100V4Z~D
RFREADER_TXP1_P1
1
@
1
2
PCI_TPM_TERM 2
10
9
8
7
6
5
4
3
2
1
2
2
1
C1018
10U_0603_6.3V6M~D
10
9
8
7
6
5
4
3
2
1
2
2
2
150NH_LLQ1608-FR15G_2%~D
2
1
C1173
68P_0402_50V8J~D
SC_RST
+SC_VCC
GND
GND
1@
L71
2RFREADER_TXN1 1
1U_0603_10V6K~D1
C647
150P_0402_50V8J~D
+3.3V_SC
SC_DET
SC_C8
SC_C4
SC_IO
SC_CLK
12
11
1
C639
@
C589
4.7P_0402_50V8C~D
R973 300_0402_5%~D
2
+3.3V_RUN 1
R1067
1
JSC1
RXN_F
2
3K_0402_1%~D
CLK_PCI_TPM
+3.3V_RUN
1
2
1
R494
1
+3.3V_RUN
BLM18BB100SN1D_0603~D
2
1 +RFID_AVDD3P3
L38
D28
RFREADER_RXN
100K_0402_5%~D
When using the 73S8009C,no-stuff R768,R769,R490
When using the 73S8009CN,stuff R768,R769,R490
2
2
1
C1017
4.7U_0603_6.3V6M~D
1
1
1
1
C875
0.1U_0402_16V4Z~D
2
2
2
2
C638
0.1U_0402_16V4Z~D
1
SC_DET
SC_IO
SC_C4
SC_C8
SC_CLK
SC_RST
100K_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
C644
1U_0603_10V4Z~D
1
C646
0.47U_0402_10V4Z~D
C1031
10U_0805_10V4Z~D
2
2
1
2
2
2
2
R744
10_0402_5%~D
73S8009CN-32IMR/F_QFN32_5X5~D
1
2
1
1
1
1
2
1
@
C632
0.1U_0402_16V4Z~D
2
1
10UH_LQH32CN100K53L_10%~D
1
1
2
1
+3.3V_RUN
C630
3.3U_0603_10V4Z~D
17
28
31
2
L69
TER_USBH_N1
TER_USBH_P1
SC_DET_PR
SC_IO_R
R773
SC_C4_R
R491
SC_C8_R
R493
SC_CLK_R R492
R772
2
+1.2V_RUN_AVDD
2
1 +RFID_AVDD1P2
L37
1
@
C631
1U_0402_6.3V6K~D
+2.5V_RUN_AVDD
2
1 +RFID_AVDD2P5
L36
48MHz
C1172
68P_0402_50V8J~D
GND
GND
GND
+LIN
RDIF
24MHZ 27.12MHz
C629
0.1U_0402_16V4Z~D
23
25
14
22
21
20
16
18
CLK
RVD
C641
150P_0402_50V8J~D
DM
DP
PRES
I/O
AUX1
AUX2
CLK
RST
JTAG
AD[16:15]
+1.2V_RUN_AVDD
+2.5V_RUN_AVDD
1
@
2
1
REF CLK
1
B
C602
0.1U_0402_16V4Z~D
RVD
C627
1U_0603_10V4Z~D
+SC_VCC
ON/OFF
CLKIN
RDY
OFF_ACK
OFF_REQ
CS
SC_USB#
CMDVCC5#
CMDVCC3#
RSTIN
OFF#
TEST1
TEST2
I/OUC
AUX1UC
AUX2UC
C1015
27P_0402_50V8J~D
A
2
1K_0402_5%~D
2
2
C619
0.1U_0402_16V4Z~D
USB
C621
4.7U_0603_6.3V6K~D
2
1
1
1
C601
0.1U_0402_16V4Z~D
11
SPI
Routing impedance is 90ohm
+SC_VCC
C633
27P_0402_50V8J~D
24
7
8
9
11
12
2 SC_USB#
13
2 47K_0402_1%~D 4
2 47K_0402_1%~D 5
1 47K_0402_1%~D 6
10K_0402_5%~D 32
10
30
BCM5880_IO
1
AUX1UC
2
AUX2UC
3
1
R771
PAD~D T139
PAD~D T63
PAD~D T64
GPIO16_TER_TRIS
1
5880_GPIO26 @ R490 1
5880_GPIO25
R766 1
BCM5880_SCRST R767 2
BCM5880_SCDET R770
19
26
29
15
27
2
2
C618
0.1U_0402_16V4Z~D
10
SMC
2
VCC
VPC
VDD
VP
LIN
1
C617
0.1U_0402_16V4Z~D
01
AD[18:17]
U33
GPIO1_TER_ON/OFF
BCM5880_SCCLK
2
1
BCM5880KFBG_FBGA225~D
C616
0.1U_0402_16V4Z~D
SSMC
Boot SRC
Pull-downs for 5880
Rev A0, and pull-ups
for Rev B0
C628
1U_0402_6.3V6K~D
1
2
C615
0.1U_0402_16V4Z~D
1
Function
C626
0.1U_0402_16V4Z~D
@ R843
00
2 BBCLK
1K_0402_5%~D
2 LPC_EN_R
4.7K_0402_5%~D
2 JTAG_RST#_USH
1K_0402_5%~D
2 SMC_ADD15
4.7K_0402_5%~D
2 SBOOT
4.7K_0402_5%~D SMC_ADD18
SMC_ADD17
USBH_OC0#
USBH_OC1#
1
R473
1
7@ R483
1
R737
1
R479
1
@ R950
C637
0.1U_0402_16V4Z~D
3@ R841
VDDO_33
VDDO_33
VDDO_33
C636
0.1U_0402_16V4Z~D
2
L9
L10
L11
1
1
C1021
4.7U_0603_6.3V6M~D
R488
3.3M_0402_5%~D
1 PLTRST3#_R
10K_0402_5%~D
2 LPC_EN_R
3K_0402_5%~D
2 IRQ_SERIRQ_R
47K_0402_1%~D
2
VESD
C635
0.1U_0402_16V4Z~D
1
@ R1089
VDD_BB
VDD_BB
L8
+3.3V_RUN
2
C607
0.1U_0402_16V4Z~D
POR_EXTR
C625
1U_0402_6.3V6K~D
2 +8009_VDDMON
47K_0402_1%~D
1
V3P3_TAMPER_N
H12
J13
1
C606
0.1U_0402_16V4Z~D
R476
5.1M_0402_5%~D
+3.3V_RUN
2
V3P3_PWRGOOD
+3.3V_RUN
2 LPD#
4.7K_0402_5%~D
2 OVSTB
4.7K_0402_5%~D
2 SBOOT
4.7K_0402_5%~D
2 TAMPER_N
4.7K_0402_5%~D
2 RST_N
4.7K_0402_5%~D
2 SMC_ADD16
4.7K_0402_5%~D
1 SC_USB#
10K_0402_5%~D
2FP_RESET#
4.7K_0402_5%~D
1
R474
1
R484
1
R485
1
R736
1
R810
1
R478
2
R850
1
R1066
C624
1U_0402_6.3V6K~D
GPIO2_TER_VDDMON 1
R20 @
1
V3P3_BBLCLK
C614
0.1U_0402_16V4Z~D
1
2
H14
C14
G11
G6
G7
G8
H10
H11
H6
H7
H8
H9
J10
J12
J6
J7
J8
J9
K10
K12
L12
M13
F8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C605
0.1U_0402_16V4Z~D
2
C706
10U_0805_10V4Z~D
2
27.12MHZ_12PF_1N227120CC0B~D
C609
15P_0402_50V8J~D
VDDO_33SC
VDDO_33SC
VDDO_SC
Place
close
to
pinA14
+3.3V_RUN
+3.3V_RUN
1
2
R339
4.7K_0402_5%~D
L13
M14
K13
1
H15
0_0402_5%~D
TAMPER_N H13
@ C594
680P_0402_50V7K
LPC_LFRAME#_R
1
2
R705 1
2 0_0402_5%~D LPC_LAD0_R
R723 1
2 0_0402_5%~D LPC_LAD1_R
R724 1
2 0_0402_5%~D LPC_LAD2_R
R732 1
2 0_0402_5%~D LPC_LAD3_R
R733
0_0402_5%~D
C620
0.1U_0402_16V4Z~D
C608
12P_0402_50V8J~D
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
1
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
JTCE
VDDO_33CORE
VDDO_33CORE
VDDO_33CORE
C613
0.1U_0402_16V4Z~D
XO
P10
R11
N10
R12
P11
M9
2
R471
VDDO_LPC
VDDO_LPC
K5
L5
L6
C612
0.1U_0402_16V4Z~D
4
RST_N
RSTOUT_N
BBCLK
K8
L7
AVSS_LDO12
AVSS_ldo25
AVSS_ldo25
AVSS_AUX
AVSS_REF
AVSS_PLL
R847
4.7K_0402_5%~D
3
GND
C8
D7
A5
E9
G10
F10
A10
A9
B8
E8
VDDO_SMC
VDDO_SMC
VDDO_SMC
R846
4.7K_0402_5%~D
OUT
GND
CLKOUT
CLKOUT_EN
@ R482
4.7K_0402_5%~D
IN
2
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
C1014
0.1U_0402_16V4Z~D
1
1
BBCLK
1
2 BBCLK_R
A1
@ R555 1
2 22_0402_5%~D B2
@ R848
4.7K_0402_1%~D
PLTRST3# 1
RST_N
2
N8
@ R1077 0_0402_5%~D SPI_RST
R8
JTAG_CLK_USH
JTAG_TDI_USH
@ R9401 0_0402_5%~D
2
JTAG_TDO_USH
JTAG_TMS_USH
@ R9411 0_0402_5%~D
2
JTAG_RST#_USH
@ R942
0_0402_5%~D
JTCE_USH
1
2
1
2
@ R949
0_0402_5%~D1
2 SWV
HF_RFIDTAG_AVSS
HF_RFIDTAG_AVSS
HF_RFIDTAG_DVSS
HF_RX_ADC_AVSS1
HF_RX_ADC_AVSS2
HF_RX_AVSS
HF_RX_AVSS
HF_TX_AVSS
HF_TX_AVSS
HF_TX_AVSS
AUXCLK_XTALIN
AUXCLK_XTALOUT
VDDO_VAR
VDDO_VAR
R845
4.7K_0402_5%~D
1
<23,30,33,34>
<23,30,33,34>
<23,30,33,34>
<23,30,33,34>
<23,30,33,34>
C1013
0.1U_0402_16V4Z~D
2
REF_XIN
0_0402_5%~D
AUX_XIN
2
D15
AUX_XOUT E14
RFREADER_RXN
RFREADER_RXP
RFREADER_TXN1
RFREADER_TXP1
R820
4.7K_0402_5%~D
XI
1
2
R487
0_0402_5%~D
K2
J1
K1
J3
M1
K3
P12
J2
L1
REFCLK_XTALIN
REFCLK_XTALOUT
E6
F6
G5
H5
J5
R844
4.7K_0402_5%~D
1
SMC_ADV_N
SMC_BLS_N_0
SMC_BLS_N_1
SMC_CRE
SMC_CS_N_0
SMC_CS_N_1
SMC_IO_3V
SMC_OE_N
SMC_WE_N
REF_XIN
F15
REF_XOUT F14
+RFID_AVDD3P3
1
2
C595
+RF_VREF
0.01U_0402_25V7K~D
RFTAG_VRXN
RFTAG_VRXP
R819
4.7K_0402_5%~D
2
10M_0402_5%~D
Y5
2
GPIO_25/SC_SEL5V
GPIO_26/SC_SEL18V
SC_CINRUSH
SC_CLK
SC_VCC
SC_RST
SC_IO
SC_FCB
SC_FCB_ENB
SC_DET
SC_PWR
SC_PWR
1R1057
<29>
B6
A6
C7
B7
E7
B10
C10
A11
A12
C11
B11
C9
B9
+3.3V_RUN
@ R475
4.7K_0402_5%~D
1
R486
2
C1023
1U_0402_6.3V6K~D
2 REF_XOUT
0_0402_5%~D
1
R481
C1022
1U_0402_6.3V6K~D
P8
R7
N15
BCM5880_SCCLK_R L14
2
10_0402_5%~D BCM5880_SCVCC
L15
BCM5880_SCRST
K15
BCM5880_IO
K14
AUX1UC
J14
AUX2UC
J15
BCM5880_SCDET
M10
M15
+SC_PWR
N14
BCM5880_SCCLK 1
T142
R472
PAD~D
5880_GPIO25
5880_GPIO26
T68
T69
OVSTB/ZEROB
SCANACCMODE
SECURE_BOOT
SWV/ERROR,OSC1,OSC2,SPL
TESTMODE/TST_SEC_BOOT
IDDQ_EN/CM3_MODE
2
USBH_DN1
USBH_UP1
USBH_OC_1
@ C600
680P_0402_50V7K
1
2
SPI
BootStrap
N13
P13
R15
PAD~D
PAD~D
FP_RESET#
OVSTB
N9
SCANMOD M8
SBOOT
P9
SWV
M12
TSTMOD
R9
IDQ_EN
R10
HF_RFIDTAG_AVSS
HF_RFIDTAG_VREF
HF_RFIDTAG_VRX_N
HF_RFIDTAG_VRX_P
HF_RFIDTAG_VTX
HF_RX_TEST0
HF_RX_TEST1
HF_RX_TEST2
HF_RX_TEST3
HF_RX_N
HF_RX_P
HF_TX_N
HF_TX_P
+RFID_AVDD1P2
C1019
4.7U_0603_6.3V6M~D
USBH_N1
2
2 22_0402_5%~D USBH_P1
22_0402_5%~D USBH_OC1#
@
T66
PLL_VDD_1P2I
PLL_AVDD_1P2O
PLL_VSS
PLL_VDD_1P2I
PLL_VSS
NC
A7
F7
C6
E10
F9
G9
D8
A8
D9
C599
0.1U_0402_16V4Z~D
1
R768 1
R769
FP_RESET#
PAD~D
B14
B15
D12
D13
E12
A15
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_DVDD1P2
HF_RX_ADC_AVDD1P2
HF_RX_AVDD1P2
HF_RX_AVDD2P5
HF_TX_AVDD1P2
HF_TX_AVDD2P5
HF_TX_AVDD3P3
C1020
10U_0603_6.3V6M~D
USBH_DN0
USBH_UP0
USBH_OC_0
SMC_ADD15
SMC_ADD16
SMC_ADD17
SMC_ADD18
2
POR_AVSS
POR_EXTR
POR_INT12
POR_MONITOR
@ 1
2
C591
680P_0402_50V7K
R4
1
2
M5
R463
1
2 2.2K_0402_5%~D
D10
R465
4.7K_0402_5%~D
A14
G12
+2.5V_RUN_AVDD
B13
A13
1
+3.3V_RUN
B12
E11
+1.2V_RUN_AVDD
E13
2
F13
+1.2V_RUN_PLL
D14
1
P15 +OTP_PWR 2
+3.3V_RUN
R467
0_0603_5%~D
2
1
F11
+SC_PWR
R829
0_0603_5%~D
C12
D11
C15
+1.2V_VDDC_5880
E15
CORE_CINRUSH
CORE_PWRDN
ALDO_PWRDN
AVDD33_LDO25
AVDD_2P5I
AVDD_2P5O
AVDD25_ldo12
AVDD25_ldo12
AVDD_1P2O
AVDD_1P2I_AUX
AVDD_1P2I_REF
AVDD25_PLL
OTP_PWR
C598
0.1U_0402_16V4Z~D
N11
N12
M11
2
1
F12
POR_EXTR G13
G15
G14
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
C877
0.1U_0402_16V4Z~D
TER_USBH_N1
TER_USBH_P1
USBD_DN
USBD_UP
GPIO_27/USBD_ATATCH
FP_USBDFP_USBD+
USBH_OC0#
FP_USBDFP_USBD+
SMC_DATA_0
SMC_DATA_1
SMC_DATA_2
SMC_DATA_3
SMC_DATA_4
SMC_DATA_5
SMC_DATA_6
SMC_DATA_7
SMC_DATA_8
SMC_DATA_9
SMC_DATA_10
SMC_DATA_11
SMC_DATA_12
SMC_DATA_13
SMC_DATA_14
SMC_DATA_15
R2
P3
R1
P2
R3
M4
N2
N3
P1
M3
M2
L4
N1
L3
L2
K4
1
BCM5880
C13
E5
F5
J11
K11
K6
K7
K9
N4
P4
+RFID_AVDD2P5
C873
0.1U_0402_16V4Z~D
<40>
<40>
R13
R14
P14
GPIO_14
GPIO_15
GPIO_16
+1.2V_RUN_PLL
BCM5880
C597
0.1U_0402_16V4Z~D
USBP10-_R
2
2 22_0402_5%~D USBP10+_R
2 22_0402_5%~D
1.5K_0402_5%~D
1
R468 1
R469 1
R470
USBP10USBP10+
GPIO_6/SSP_CLK
GPIO_7/SSP_FSS
GPIO_8/SSP_RXD
GPIO_9/SSP_TXD
H1
J4
H2
H3
G1
H4
F2
G4
G2
G3
E2
F4
F1
F3
D2
E3
D1
E1
C2
D3
C1
E4
B1
C3
C596
0.1U_0402_16V4Z~D
<24>
<24>
C4
A2
D4
GPIO_0/UART_RX
GPIO_1/UART_TX
GPIO_2/UART_CTS
GPIO_3/UART_RTS
SMC_ADD_0
SMC_ADD_1
SMC_ADD_2
SMC_ADD_3
SMC_ADD_4
SMC_ADD_5
SMC_ADD_6
SMC_ADD_7
SMC_ADD_8
SMC_ADD_9
SMC_ADD_10
SMC_ADD_11
SMC_ADD_12
SMC_ADD_13
SMC_ADD_14
SMC_ADD_15/REFCLK_FREQ_0
SMC_ADD_16/REFCLK_FREQ_1
SMC_ADD_17/BOOT_SRC_0
SMC_ADD_18/BOOT_SR_1
SMC_ADD_19
SMC_ADD_20
SMC_ADD_21
SMC_ADD_22
SMC_ADD_23
@
GPIO1_TER_ON/OFF
BCM5880_GPIO15
GPIO16_TER_TRIS
BCM5880
LCLK
LPCEN
GPIO_17/LRESET_N
GPIO_18/LFRAME_N
GPIO_19/LSERIRQ
GPIO_20/LAD[0]
GPIO_21/LAD[1]
GPIO_22/LAD[2]
GPIO_23/LAD[3]
GPIO_24/LPCPD_N
U32C
U32B
C593
1U_0603_10V4Z~D
R4641
R1072
1
0_0402_5%~D
1
<24,27,30,33,34> IRQ_SERIRQ
R842
+1.2V_VDDC_5880
USH:B0-->SA00001SJ1L
C592
1U_0603_10V4Z~D
CLK_PCI_TPM
M7
2 0_0402_5%~D LPC_EN_R
R6
PLTRST3#_R
2
N5
LPC_LFRAME#_R
P5
IRQ_SERIRQ_R
2
M6
LPC_LAD0_R
0_0402_5%~D
R5
LPC_LAD1_R
N6
LPC_LAD2_R
N7
LPC_LAD3_R
P6
LPD#
1
2
P7
@ R466
0_0402_5%~D
UART_RX/GPIO0
B5
UART_RX/GPIO1
B4
GPIO2_TER_VDDMON D6
SC_DET 2
SC_DET_R
1
A4
R849
1.5K_0402_5%~D
UART_RX/GPIO1
SPI_CLK
C5
SPI_CS
1
2UART_RX/GPIO0
B3
SPI_RXD
@ R948
0_0402_5%~D
D5
SPI_TXD
A3
@
<21,22> PLTRST3#
B
1
U32A
Smard Card
3@ D76
RB751S40T1_SOD523-2~D
1
2
<6> CLK_PCI_TPM
<24> CONTACTLESS_DET#
CONTACTLESS_DET#
1
2
3
4
5
6
7
8
1
2
3
4
5
6
GND
GND
TYCO_2041070-6
3
+3.3V_RUN
BAS40-04_SOT23-3~D
Title
BCM5880_GPIO15
1
@ R341
SC_DET
2
@ R1068
TYCO_1-1775784-0
2
2
4.7K_0402_5%~D
1
100K_0402_5%~D
1
USH I/F
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
32
of
57
5
4
3
+3.3V_RUN
2
1
+3.3V_ALW
2
+3.3V_ALW
R882
100K_0402_5%~D
SLICE_BAT_PRES#
2
4.7K_0402_5%~D
DCIN_CBL_DET#
2
100K_0402_5%~D
CELL_CHARGER_DET#
2
100K_0402_5%~D
PWR_BTN_BD_DET#
2
100K_0402_5%~D
1
1
1
R501
1
R503
1
R862
1
R991
1
R1099
PCIE_WAKE#
2
10K_0402_5%~D
2
DET_PCCRD_EXPSCRD#
1
C648
0.1U_0402_16V4Z~D
1
2
C652
0.1U_0402_16V4Z~D
2
1
C649
0.1U_0402_10V7K~D
2
1
C650
0.1U_0402_16V4Z~D
C651
0.1U_0402_16V4Z~D
2
+3.3V_ALW
D
GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N
SLICE_BAT_PRES#
PWR_BTN_BD_DET#
32
33
GPIOH[6]
GPIOH[7]
LAN_DISABLE#_R
CAP_LED#
SYS_LED_MASK#
CBUS_GRST#
R526 1
2 0_0402_5%~D
ICH_PME#
ICH_PCIE_WAKE#
WLAN_RADIO_DIS#
88
89
90
91
92
93
94
95
GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]
<26> HDDC_EN
<26> MODC_EN
<38> PWR_BTN_BD_DET#
<21> LAN_DISABLE#_R
<38> CAP_LED#
<38> SYS_LED_MASK#
<27> CBUS_GRST#
<24> SIO_EXT_WAKE#
<22> ICH_PME#
<24> ICH_PCIE_WAKE#
<21> WLAN_RADIO_DIS#
B
WWAN_RADIO_DIS#
<21> WWAN_RADIO_DIS#
D74
RB751S40T1_SOD523-2~D
<34,38> INSTANT_ON_SW#
INSTANT_ON_SW# 1
2
1
@ R1070
106
107
INSTANT_ON_SW_D#
2
0_0402_5%~D
CHIPSET_ID0
BID2
BID1
BID0
5
2
1
2
1
2
1
2
1
2
1
CHIPSET_ID1
1
R534
1
R535
1
@R536
1
R537
1
@R538
GPIOI[4](XTAL1/CLKIN)
GPIOI[3](XTAL2)
123
122
SIO_SLP_S3#
3.3V_RUN_ON
54
52
49
47
42
41
56
37
46
44
39
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLKI (14.318 MHz)
64
CLK_SIO_14M
VSS
96
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
55
53
50
48
43
38
45
40
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
7
RUNPWROK
OUT65
105
SP_TPM_LPC_EN
GPIOJ[4](VSS)
VSS
GPIOK[7](VSS)
VSS
VSS
VSS
VSS
VSS
GPIOJ[1](VSS)
11
17
23
36
51
72
87
121
128
GPIO_PSID_SELECT
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
LPC
DLPC
PWRGD
GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]
113
114
IRTX
IRRX
115
116
117
118
GPIOF[3]/IRMODE/IRRX3B
GPIOF[2]/IRTX2
GPIOF[1]/IRRX2
GPIOF[0]/IRMODE/IRRX3A
1
2
ACAV_IN_NB
1
IN1
2
IN2
@ R1078
1
O
SIO_SLP_S3# <24>
3.3V_RUN_ON <36,39>
4DOCK_AC_OFF_R 2
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
4
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X00
X01
X02
X03
X04
X05
X06
X07
1
DOCK_AC_OFF <31,48>
U96
D78 RB751S40T1_SOD523-2~D
R1079
33K_0402_1%~D
SPI_WP#_SEL
C657
4.7U_0603_6.3V4Z~D
LPC_LAD[0..3] <23,30,32,34>
LPC_LFRAME# <23,30,32,34>
PLTRST2# <22,34>
CLK_PCI_5028 <6>
CLKRUN# <24,27,30,34>
LPC_LDRQ0# <23>
LPC_LDRQ1# <23>
IRQ_SERIRQ <24,27,30,32,34>
CLK_SIO_14M <6>
+3.3V_RUN
D_LAD0 <31>
D_LAD1 <31>
D_LAD2 <31>
D_LAD3 <31>
D_LFRAME# <31>
D_CLKRUN# <31>
D_DLDRQ1# <31>
D_SERIRQ <31>
CLK_SIO_14M
R648
10K_0402_5%~D
ME_FWP
CLK_PCI_5028
@R506
10_0402_5%~D
@ R527
10_0402_5%~D
B
1
@ R649
@C654
10K_0402_5%~D 4.7P_0402_50V8C~D
RUNPWROK
2
1
@ C656
4.7P_0402_50V8C~D
2
<34,37,45>
SP_TPM_LPC_EN <30,32>
GPIO_PSID_SELECT <41>
+3.3V_ALW
SPI_WP#_SEL <24>
TP_DET#
<35>
LID_CL_SIO#
BID2 BID1 BID0 REV
0
0
0
0
1
1
1
1
C
2 0_0402_5%~D
R524
1M_0402_5%~D
ECE5028-NU_VTQFP128_14X14~D
R533
10K_0402_5%~D
CHIPSET_ID0
@ R532
10K_0402_5%~D
BID2
R531
10K_0402_5%~D
BID1
@ R530
10K_0402_5%~D
@ R529
10K_0402_5%~D
BID0
DOCK_AC_OFF_EC
TP_DET#
+3.3V_ALW
A
126
SYSOPT1/GPIOH[2]
SYSOPT0/GPIOH[3]
109
110
111
112
VGA_IDENTIFY
CHIPSET_ID1
R528
10K_0402_5%~D
2
1
GPIOI[7](ATEST)
C1161 0.1U_0402_16V4Z~D
1
2
ACAV_IN_NB <34,46>
1
63
28
29
30
31
IMVP_VR_ON <45>
IMVP_PWRGD <24,37,45,47>
0.75V_DDR_VTT_ON <44>
2
HD DC_EN
MODC_EN
INSTANT_ON_SW_D#
CLK
2.5V_RUN_PWRGD <18,37>
RUN_ON
<19,21,36,37,39>
1.5V_RUN_ON <36>
+3.3V_ALW
2
1
R514
1K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
2
100K_0402_5%~D
2
100K_0402_5%~D
RUN_ON
1.5V_RUN_ON
1
GPIOD[1]
GPIOD[2]
TEST
35
2
R515
2
R516
1.05V_RUN_ON
2
R518
3.3V_RUN_ON
2
R519
0.75V_DDR_VTT_ON 2
R520
PBATT_OFF
2
R521
VGA_IDENTIFY
1
R522
1.8V_RUN_ON
1
R951
D_DLDRQ1#
2
61
62
LID_CL_SIO#
1.05V_RUN_ON
<36> 1.05V_RUN_ON
GPIO
TEST_PIN
R509 1
20_0402_5%~D
IMVP_PWRGD
0.75V_DDR_VTT_ON
8mil
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
2
1
R502
1
R504
1
R1013
<21> EN_I2S_NB_CODEC
<27> CB_HWSPND#
<48> EN_DOCK_PWR_BAR
<46> ADAPT_OC
<46> ADAPT_TRIP_SET
<19> LCD_TST
<41> PSID_DISABLE#
<12> PANEL_BKEN_MCH
<21>
DOCKED
USB_SIDE_EN#
2
<31> DOCK_DET#
10K_0402_5%~D
<21> AUD_NB_MUTE
ESATA_USB_PWR_EN#
2
<21> CELL_CHARGER_DET#
10K_0402_5%~D
<19> LCD_VCC_TEST_EN
2
<19> CCD_OFF
100K_0402_5%~D
<21> AUD_HP_NB_SENSE
<29> ESATA_USB_PWR_EN#
+CAP_LDO
2
2
R510
2
R511
2
R512
D_SERIRQ
1
+3.3V_ALW2
USB_SIDE_EN#
EN_I2S_NB_CODEC
CB_HWSPND#
EN_DOCK_PWR_BAR
ADAPT_OC
ADAPT_TRIP_SET
LCD_TST
PSID_DISABLE#
PANEL_BKEN_MCH
DOCKED
DOCK_DET#
AUD_NB_MUTE
CELL_CHARGER_DET#
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
125
124
120
86
127
2.5V_RUN_PWRGD
RUN_ON
1.5V_RUN_ON
SNIFFER_BLUE# <38>
SNIFFER_YELLOW# <38>
DOCK_HP_DET <21>
CRT_SWITCH <20>
ME_FWP
<23>
NB_AC_OFF <41,46,48>
D_CLKRUN#
1
GPIOB[0]/INIT#
GPIOB[1]/SLCTIN#
GPIOC[2]/SCLT
GPIOC[3]/PE
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIOC[6]/ERROR#
GPIOC[7]/ALF#
GPIOD[0]/STROBE#
GPIOC[1]/PD7
GPIOC[0]/PD6
GPIOB[7]/PD5
GPIOB[6]/PD4
GPIOB[5]/PD3
GPIOB[4]/PD2
GPIOB[3]/PD1
GPIOB[2]/PD0
C
GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)
GPIOI[2](VDD18)
CAP_LDO
GPIOJ[0](RBIAS)
SNIFFER_BLUE#
SNIFFER_YELLOW#
DOCK_HP_DET
CRT_SWITCH
ME_FWP
NB_AC_OFF
1
1.8V_RUN_ON <44>
2
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
DET_PCCRD_EXPSCRD#
<28> DET_PCCRD_EXPSCRD#
USB
9
10
13
12
15
16
19
18
21
22
DOCK_MIC_DET <21>
MCH_TSATN_EC <10>
2
GPIOE[0]/RXD
GPIOE[1]/TXD
GPIOE[2]/RTS#
GPIOE[3]/DSR#
GPIOE[4]/CTS#
GPIOE[5]/DTR#
GPIOE[6]/RI#
GPIOE[7]/DCD#
GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)
119
1.8V_RUN_ON
1
1
2
3
4
5
84
83
6
GPIOI[1](VCC1)
DOCK_MIC_DET
MCH_TSATN_EC
1
GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
BC_INT#
BC_DAT
BC_CLK
ECE5028-NU
(ECE5018)
8
14
20
5
24
25
26
27
58
59
60
WIRELESS_ON#/OFF
BT_RADIO_DIS#
EXPRCRD_PWREN#
EXPRCRD_STDBY#
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
<21> WIRELESS_ON#/OFF
<30> BT_RADIO_DIS#
<28> EXPRCRD_PWREN#
<28> EXPRCRD_STDBY#
<34> BC_INT#_ECE5028
<34> BC_DAT_ECE5028
<34> BC_CLK_ECE5028
+3.3V_ALW
VCC1(VDDA33)
GPIOJ[7](VDDA33)
GPIOK[4](VDDA33)
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
+3.3V_RUN
P
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
G
97
98
99
100
101
102
103
104
3
PBAT_PRES#
SCRL_LED#
NUM_LED#
DCIN_CBL_DET#
PBATT_OFF
SYS_PME#
PCIE_WAKE#
<41> PBAT_PRES#
<38> SCRL_LED#
<38> NUM_LED#
<41> DCIN_CBL_DET#
<48> PBATT_OFF
<27>
SYS_PME#
<21,28> PCIE_WAKE#
<21> USB_POWERSHARE_PWR_EN#
SNIFFER_BLUE#
2
@ R507
SNIFFER_YELLOW# 2
@ R508
TP_DET#
2
R756
INSTANT_ON_SW_D# 2
R1080
2
U35
WIRELESS_ON#/OFF
2
100K_0402_5%~D
SP_TPM_LPC_EN
2
10K_0402_5%~D
LCD_TST
2
100K_0402_5%~D
PANEL_BKEN_MCH
1
100K_0402_5%~D
SYS_LED_MASK#
1
10K_0402_5%~D
C653
0.1U_0402_16V4Z~D
1
@ R874
1
@ R788
1
R816
2
R505
2
R1069
VCC1
VCC1
VCC1
VCC1
+3.3V_RUN
34
57
85
108
D
R525
10_0402_5%~D
2
1
LID_CL#
LID_CL#
<29,38>
1
CHIPSET_ID0
CHIPSET_ID1
0
1
Note
2
C655
0.047U_0402_16V4Z~D
A
SFF
3
2
Title
ECE5028
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
33
of
57
5
4
3
2
1
1
+RTC_CELL
R539
100K_0402_5%~D
2
2
L39
1
2
1
2
2
R578
10K_0402_5%~D
= Amber LED
= Blue LED
VSS_RO
thermal GND
129
VR_CAP[1]
22
1
DOCK_SMB_DAT
2
1
DAT_MSE
2
AC_PRESENT
C
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
2
10K_0402_5%~D
1
R579
10K_0402_5%~D
JTAG_RST#
C1109
0.1U_0402_16V4Z~D
1
2
R585
100_0402_1%~D
@
1
1
2
DOCK_SMB_DAT <31>
DOCK_SMB_CLK <31>
LCD_SMBDAT <19>
LCD_SMBCLK <19>
CKG_SMBDAT <6,21,46>
CKG_SMBCLK <6,21,46>
AMT_SMBDAT <24>
AMT_SMBCLK <24>
ACAV_IN_NB <33,46>
+3.3V_ALW
2
RC _ID
@
CARD_SMBDAT <21,28>
CARD_SMBCLK <21,28>
BKT_SMBDAT <39>
BKT_SMBCLK <39>
+RTC_CELL
JTAG1
@SHORT PADS~D
1
U57
IN1
1
IN2
2
SNIFFER_PWR_SW#
P
SNIFFER/INSTANT_SW#
ALWON
ALWON
<42>
EN_CELL_CHARGER_DET#
EN_CELL_CHARGER_DET# <21>
POWER_SW_IN#
ACAV_IN
ACAV_IN
<18,46>
DOCK_PWR_SW#
4
@
O
1
R1071
2
B
C1011 0.1U_0402_16V4Z~D
INSTANT_ON_SW#
G
118
119
120
126
127
128
1
CLK_MSE
R1050
33K_0402_1%~D
3.3V_M_PWRGD <18,37>
AUX_EN_WOWL <30>
SIO_SLP_S4# <10,24>
M_ON
<36>
ICH_RSMRST# <24>
AC_PRESENT <24>
SIO_PWRBTN# <24>
2
R569
2
R570
2
R571
2
R572
1
R573
DAT_KBD
+3.3V_ALW
3
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
+5V_RUN
CLK_KBD
2
CARD_SMBDAT
CARD_SMBCLK
BKT_SMBDAT
BKT_SMBCLK
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
1
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
CKG_SMBDAT
CKG_SMBCLK
AMT_SMBDAT
AMT_SMBCLK
ACAV_IN_NB
2
R565
2
R567
@ R586
10K_0402_5%~D
5
5
6
7
8
12
13
93
94
95
96
97
98
99
100
DOCK_SMB_CLK
1
3.3V_M_PWRGD
AUX_EN_WOWL
SIO_SLP_S4#
M_ON
ICH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
SIO_SLP_M#
<24>
DOCK_SMB_ALERT# <31,41>
ME_WOL_EN <24>
ME_SUS_PWR_ACK <24>
1.5V_SUS_PWRGD <10,43>
ICH_CL_PWROK <10,24>
3.3V_LAN_PWRGD <37>
1.05V_M_PWRGD <43>
ALW_PWRGD_3V_5V <42>
SUSPWROK
<37>
SIO_SLP_S5# <24>
BEEP
<21>
AUX_ON
<36>
+RTC_CELL
1
100K_0402_5%~D
2
100K_0402_5%~D
1
200K_0402_5%~D
1
RB751S40T1_SOD523-2~D
1
100K_0402_5%~D
+3.3V_ALW
1
SIO_SLP_M#
DOCK_SMB_ALERT#
ME_WOL_EN
ME_SUS_PWR_ACK
1.5V_SUS_PWRGD
ICH_CL_PWROK
3.3V_LAN_PWRGD
1.05V_M_PWRGD
ALW_PWRGD_3V_5V
SUSPWROK
SIO_SLP_S5#
BEEP
AUX_ON
DOCK_PWR_BTN# <31>
2
21
44
65
83
116
104
4
52
1
2
2
@ C673
4.7P_0402_50V8C~D
8mil +VR_CAP
CLK_PCI_5035
1
1
C674
27P_0402_50V8J~D
2
2
C675
22P_0402_50V8J~D
3
1
A
121
AGND
1+5035_AGND 125
15mil
Place closely pin 58
@ R588
10_0402_5%~D
Y4
32.768K_12.5P_1TJS125DJ4A420P~D
MEC5035_XTAL2
4
1
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
MASTER CLOCK
XTAL1
XTAL2
GPIO160/32KHZ_OUT
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[7]
VSS[8]
2
1
1
1
2
2
32 KHz
Clock
Same as Laguna
2
3
14
15
16
17
18
28
29
30
31
32
33
34
73
84
89
90
91
108
109
2
1K_0402_5%~D
2
R560
SNIFFER_PWR_SW# 1
R562
EN_CELL_CHARGER_DET#
2
R877
2
D79
SNIFFER/INSTANT_SW# 2
R968
+3.3V_ALW
DELL PWR SW INF
<18> EC_32KHZ_OUT
MEC5035_XTAL1
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
GPIO011/nSMI
GPIO061/LPCPD#
LDRQ#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/nEC_SCI
ACES_85204-06001~D
HOST_DEBUG_TX <21>
HOST_DEBUG_RX <21>
RESET_OUT# <37>
MSDATA
<21>
MSCLK
<21>
SIO_A20GATE <23>
PS_ID
<41>
BAT1_LED#
<38> Bat2
BAT2_LED#
<38> Bat1
1
R554
1
2
@ C669
1U_0402_6.3V6K~D
2 C670
1U_0603_10V4Z~D
INSTANT_ON_SW#
2
HOST INTERFACE
122
124
117
HOST_DEBUG_TX
HOST_DEBUG_RX
RESET_OUT#
MSDATA
MSCLK
SIO_A20GATE
PS_ID
BAT1_LED#
BAT2_LED#
FWP#
1
R550
100K_0402_5%~D
DOCK_PWR_SW#
DDR_ON
<10,36,44>
RUNPWROK <33,37,45>
ICH_LAN_RST# <24>
20mA drive pins
SMBUS INTERFACE
C671
4.7U_0603_6.3V4Z~D +5035_VSS 101
15mil
MEC5035_XTAL1
1
0_0402_5%~D
BC-LINK
26
51
74
88
113
20
53
1
2
1
2
2
1
1
1
2
2
VBAT
MEC5035_XTAL2
2
R587
GPIO001
GPIO002
GPIO014/GPTP-IN7
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO020
GPIO26/GPTP-IN1
GPIO27/GPTP-OUT1
GPIO30/GPTP-IN2
GPIO31/GPTP-OUT2
GPIO032/GPTP-IN3
GPIO040/GPTP-OUT3
GPIO041
GPIO107
GPIO120
GPIO124/GPTP-OUT5
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
FAN PWM & TACH
11
54
55
56
57
58
59
60
61
62
63
64
66
RC _ID
DDR_ON
RUNPWROK
ICH_LAN_RST#
POWER_SW#_MB <38>
D
FWP#
0.1U_0402_16V4Z~D
2
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC5035
IRQ_SERIRQ
PLTRST2#
CLK_PCI_5035
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
2
2
1K_0402_5%~D
C659
1U_0603_10V4Z~D
+RTC_CELL
<18> DOCK_PWR_SW#
19
27
49
50
67
68
69
70
71
72
81
82
92
110
114
115
123
GENERAL PURPOSE I/O
GPIO022/BCM_B_CLK/V_CLK
GPIO023/BCM_B_DAT/V_DATA
GPIO024/BCM_B_INT#/V_FRAME
GPIO042/BCM_C_INT#
GPIO043/BCM_C_DAT
GPIO044/BCM_C_CLK
GPIO045/LSBCM_D_INT#
GPIO046/LSBCM_D_DAT
GPIO047/LSBCM_D_CLK
GPIO121/BCM_A_INT#
GPIO122/BCM_A_DAT
GPIO123/BCM_A_CLK
2
1
C1151
4700P_0402_25V7K~D
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
GPIO021/RC_ID
GPIO025/UART_CLK
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO102/ECGP_SOUT
GPIO103/ECGP_SIN
GPIO104/UART_TX
GPIO105/UART_RX
GPIO106/nRESET_OUT
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
JTAG INTERFACE
23
24
25
35
36
37
38
39
40
85
86
87
2
1
C668
0.1U_0402_16V4Z~D
R583
10K_0402_5%~D
1
2
3
4
5
6
R584
10K_0402_5%~D
R582
10K_0402_5%~D
R581
10K_0402_5%~D
G1
G2
1
2
3
4
5
6
R580
49.9_0402_1%~D
@JP2
7
8
<24,27,30,32,33> IRQ_SERIRQ
<22,33> PLTRST2#
<6> CLK_PCI_5035
<23,30,32,33> LPC_LFRAME#
<23,30,32,33> LPC_LAD0
<23,30,32,33> LPC_LAD1
<23,30,32,33> LPC_LAD2
<23,30,32,33> LPC_LAD3
<24,27,30,33> CLKRUN#
<24> SIO_EXT_SCI#
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#
GPIO050/FAN_TACH1
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PWM0
GPIO054/PWM1
GPIO055/PWM2
GPIO056/PWM3
2
1
C667
0.1U_0402_16V4Z~D
+3.3V_ALW
<24> SIO_EXT_SMI#
<23> SIO_RCIN#
102
103
105
106
107
41
42
43
45
46
47
48
2
1
C666
0.1U_0402_16V4Z~D
2
0_0402_5%~D
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
BC_CLK_EMC4002
BC_DAT_EMC4002
BC_INT#_EMC4002
BC_INT#_ECE1088
BC_DAT_ECE1088
BC_CLK_ECE1088
BC_INT#_ECE1077
BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
2
1
C665
0.1U_0402_16V4Z~D
HOST_DEBUG_RX
GPIO007/I2C1D_DATA/PS2_CLK0B
GPIO010/I2C1D_CLK/PS2_DAT0B
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B
GPIO155/I2C1C_CLK/PS2_DAT1B
BREATH_LED#
ICH_ALW
KYBRD_BKLT_PWM
1
C664
0.1U_0402_16V4Z~D
<18> BC_CLK_EMC4002
<18> BC_DAT_EMC4002
<18> BC_INT#_EMC4002
<35> BC_DAT_ECE1088
<35> BC_CLK_ECE1088
<35> BC_DAT_ECE1077
<35> BC_CLK_ECE1077
<33> BC_DAT_ECE5028
<33> BC_CLK_ECE5028
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
9
10
75
76
77
78
79
80
111
112
DOCK_POR_RST#
SUS_ON
2
C663
10U_0805_10V4Z~D
<31,38> BREATH_LED#
<36> ICH_ALW
<35> KYBRD_BKLT_PWM
Molex_53261
B
<35> CLK_TP_SIO
<35> DAT_TP_SIO
<31> CLK_KBD
<31> DAT_KBD
<31> CLK_MSE
<31> DAT_MSE
<41> PBAT_SMBDAT
<41> PBAT_SMBCLK
1
MISC INTERFACE
PS/2 INTERFACE
<31> DOCK_POR_RST#
<36,37> SUS_ON
R576
10K_0402_5%~D
R575
10K_0402_5%~D
R574
100K_0402_5%~D
MSDATA
MSCLK
1
R577
1
2
U36
C1167
1
+3.3V_ALW
@ JDEG1
5 5
4 4
3 3
2 2
1 1
2
C660
0.1U_0402_16V4Z~D
C662
0.1U_0402_16V4Z~D
C
2
+RTC_CELL_VBAT
1
C661
0.1U_0402_16V4Z~D
1 DOCK_POR_RST#
1M_0402_5%~D
M_ON
1
1M_0402_5%~D
AUX_ON
2
2.7K_0402_5%~D
DDR_ON
2
100K_0402_5%~D
SUS_ON
2
100K_0402_5%~D
ICH_ALW
2
100K_0402_5%~D
2
R1082
2
R561
1
R563
1
R564
1
R566
1
R568
1
2
R544
0_0402_5%~D
1
R541
1
+3.3V_ALW
+RTC_CELL
2
@ C658
1U_0402_6.3V6K~D
POWER_SW_IN#
<18> POWER_SW_IN#
CKG_SMBDAT
2
2.2K_0402_5%~D
CKG_SMBCLK
2
2.2K_0402_5%~D
BC_DAT_ECE5028
2
100K_0402_5%~D
BC_DAT_EMC4002
1
100K_0402_5%~D
BC_DAT_ECE1077
1
100K_0402_5%~D
DOCK_SMB_ALERT#
1
10K_0402_5%~D
LCD_SMBCLK
2
8.2K_0402_5%~D
LCD_SMBDAT
2
8.2K_0402_5%~D
PBAT_SMBDAT
2
2.2K_0402_5%~D
PBAT_SMBCLK
2
2.2K_0402_5%~D
BC_DAT_ECE1088
1
100K_0402_5%~D
1 LPC_LDRQ#_MEC5035
100K_0402_5%~D
CARD_SMBDAT
2
2.2K_0402_5%~D
CARD_SMBCLK
2
2.2K_0402_5%~D
1 HOST_DEBUG_TX
10K_0402_5%~D
BKT_SMBDAT
2
2.2K_0402_5%~D
BKT_SMBCLK
2
2.2K_0402_5%~D
1
R540
1
R542
1
R543
2
R545
2
R546
2
R547
1
R548
1
R549
1
R551
1
R552
2
5@ R557
2
@ R837
1
R838
1
R839
2
R974
1
5@ R1026
1
5@ R1027
D
1
2
+3.3V_ALW
INSTANT_ON_SW# <33,38>
SNIFFER_PWR_SW# <21>
1=JTAG interface Reset disabled
0=Reset JTAG interface
2
0_0402_5%~D
MEC5035_XVTQFP128_14X14~D
1
2
L40
A
5
4
3
2
Title
EMC5035
Size
Document Number
Date:
R ev
1.0
LA-4151P
Sheet
1
34
of
57
5
4
3
2
1
+3.3V_ALW
D
5@
5@
2
5@
2
@R747
2
R650 2
R826
For LVDS signals switch
BKT_GPIO2
For BKT power switch
BKT_GPIO3
For TP power swich&USB signal switch
BKT_GPIO4
For AMP/TP power source&USB signal switch
Part Number
GC20323MX00
Description
BATT CR2032 3V
220MAH MAXELL
5@ U38
7
21
BC_DAT_ECE1088
BC_CLK_ECE1088
BC_INT#_ECE1088
<34> BC_DAT_ECE1088
<34> BC_CLK_ECE1088
+3.3V_ALW
1
C677
0.1U_0402_16V4Z~D
2
C676
0.1U_0402_16V4Z~D
1
5@
@ RTC BATT
BKT_GPIO1
22
23
24
ECE1088GPIO00
VCC
VCC
GPIO01
GPIO02
GPIO03
GPIO07
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO20
GPIO24
GPIO25
GPIO26
GPIO27
GPIO30
GPIO31
GPIO32
GPIO36
GPIO37
BC_DAT/SMB_DATA
BC_CLK/SMB_CLK
BC_INT#/SMB_INT#
1
10K_0402_5%~D
1
25
1 10K_0402_5%~D 28
10K_0402_5%~D 27
SMB_ADDR
TEST
RESERVE
29
THER_PAD
BKT_GPIO1
BKT_GPIO2
BKT_GPIO3
BKT_GPIO4
BKT_GPIO5
BKT_GPIO6
BKT_GPIO7
BKT_GPIO8
BKT_GPIO9
17
18
19
20
26
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
BKT_GPIO11
BKT_GPIO12
BKT_GPIO13
BKT_GPIO14
BKT_GPIO15
BKT_GPIO16
BKT_GPIO17
BKT_GPIO18
BKT_GPIO19
BKT_GPIO1
BKT_GPIO2
BKT_GPIO3
BKT_GPIO4
BKT_GPIO5
BKT_GPIO6
BKT_GPIO7
BKT_GPIO8
BKT_GPIO9
<40>
<39>
<40>
<39,40>
<39>
<39>
<39>
<39>
<39>
BKT_GPIO11
BKT_GPIO12
BKT_GPIO13
BKT_GPIO14
BKT_GPIO15
BKT_GPIO16
BKT_GPIO17
BKT_GPIO18
BKT_GPIO19
<40>
<21>
<21>
<19>
<39>
<39>
<29>
<19>
<39>
+3.3V_ALW
ECE1088-FZG_QFN28_5X5~D
@ FAN
Part Number
DC28A000800
Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
D
@ Speak
BKT_GPIO5
For LID_Closed
Part Number
PK230003Q0L
BKT_GPIO6
For PAD_Out
BKT_GPIO7
For BKT Reset
BKT_GPIO8
For USB_SEL_BLK
BKT_GPIO9
For Radio_OFF
Description
SPK PACK ZJX 2.0W 4 OHM FG
SM CARD BODY
Part Number
Description
SP070007V0L S SOCKET TYCO 1770551-1
10P H5.9 SMART
PCMCIA BODY
Part Number
DC000001Q0L
BKT_GPIO11
Biometric mux switch
BKT_GPIO12
For WLAN antenna mux control
Description
PCMCIA TYCO
1759096-1
@ PWR cable
BKT_GPIO17 2
@
R1104
1
10K_0402_5%~D
Part Number
NBX00009O0L
C
Normal mode
0
BKT_GPIO12
JTP1
BKT_GPIO15
+5V_TP_PWR
1
2
2
Place close to
JTP1.12
+3.3V_ALW
BKT_GPIO16
BKT_GPIO17
For Biometic reset signal
BKT_GPIO18
For LVDS Power switch
BKT_GPIO19
For TP Power
Place close to
JTP1.13
NBX0000BA0L
Part Number
+5V_ALW
TP_DATA
1
1
@
2
@
2
2
NBX00009L0L
Part Number
NBX0000BF0L
DAT_TP_SIO
DAT_TP_SIO <34>
4
FPC 03S LF-4151P REV0
M/B-LED/B
Description
FFC 16P G P0.5
PAD=0.3 117MM
MB-TP 03S
CLK_TP_SIO <34>
NBX00009M0L
1
2
B
Description
FFC 12P F P0.5
PAD=0.3
76MM MB-BT/B 03S
Description
FFC 12P A P1
PAD=0.6 L=83MM
03I
@ Finger print cable
Part Number
CLK_TP_SIO
Description
FFC 6P F P0.5
PAD=0.3 257.2MM
MB-FP 03S
Title
Touch PAD/Int KB/LID
Size
3
Document Number
Rev
1.0
LA-4151P
Date:
5
Description
@ SW cable
C683
10P_0402_50V8J~D
2
C682
10P_0402_50V8J~D
Place close to JTP1 connector
1
L41
1
2
1
2
L42
1
C681
10P_0402_50V8J~D
2
C680
10P_0402_50V8J~D
D54
SD05.TCT_SOD323-2~D
+3.3V_RUN_BKT_PWR
1
2
D53
SD05.TCT_SOD323-2~D
+3.3V_RUN
TP_CLK
TP_DATA
H-CONN SET 03S MB-LCD
@ Bluetooth cable
TP_CLK
6@ PJP59 PAD-OPEN 4x4m +3.3V_TP_PWR
1
2
Description
@ TOUCH PAD cable
Part Number
2
2
Place close to
JTP1.5,6
1
2
Part Number
DA300003O0L
1
A
For SMBALERT
R595
4.7K_0402_5%~D
6@ PJP57 PAD-OPEN 4x4m +5V_TP_PWR
1
2
1
C
@ LED cable
R594
4.7K_0402_5%~D
2
For WWAN Power
+3.3V_TP_PWR
C771
0.1U_0402_16V4Z~D
1
+5V_RUN_BKT_PWR
1
Place close to
JTP1.11
TYCO_1-2041070-6
+5V_RUN
Part Number
+5V_ALW
C679
0.1U_0402_16V4Z~D
B
For Inverter Power
1
KYBRD_BKLT_PWM
TP_DET#
BKT_GPIO14
2
<34> KYBRD_BKLT_PWM
<33> TP_DET#
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FFC 4P G P.5
PAD=.3 79MM
MB-PWR_SW/B 03S
@ LCD-LED cable
1
+5V_TP_PWR
+5V_ALW
+3.3V_TP_PWR
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RSB_DET#
DC02000KC0L
C1112
0.1U_0402_16V4Z~D
TP_CLK
TP_DATA
GND
GND
C678
0.1U_0402_16V4Z~D
<34> BC_DAT_ECE1077
<34> BC_CLK_ECE1077
+3.3V_ALW
18
17
BKT mode
1
BKT_GPIO13
Description
2
Sheet
1
35
of
57
A
4
3
1
4
6
5
2N7002DW-T/R7_SOT363-6~D
1
2
6
1
R1003 4.7K_0402_5%~D
<10,34,44> DDR_ON
1
@ R1101
4
2
0_0402_5%~D
1
R607
20K_0402_5%~D
1
2
C691
10U_0805_10V4Z~D
4
Q70B
2N7002DW-T/R7_SOT363-6~D
4
1
2
R614
20K_0402_5%~D
1
+1.05V_VCCP
1
2
2
4
C695
10U_0805_10V4Z~D
1
5
C697
470P_0402_50V7K~D
Q70A
2N7002DW-T/R7_SOT363-6~D
<33> 1.05V_RUN_ON
B
2
+1.5V_RUN Source
3
4
2
C1200
1U_0603_10V6K~D
RUN_ON_1.5V#
5
4
Q129B
2N7002DW-T/R7_SOT363-6~D
1
2
1
1
2
R912
20K_0402_5%~D
1
2
@ D65
RB751V_SOD323-2~D
1
2
R913
0_0402_5%~D
+1.5V_RUN
2
1
R911
100K_0402_5%~D
C1080
10U_0805_10V4Z~D
Q128
+1.5V_MEM SI4336DY-T1-E3_SO8~D
8
1
7
2
6
3
5
+15V_ALW
1
EN_1.5VALW
2N7002DW-T/R7_SOT363-6~D
1
2
3
4
R1035 4.7K_0402_5%~D
Q67
SI4336DY-T1-E3_SO8~D
1
2
3
1
2
@ D31
RB751V_SOD323-2~D
1
2
R618
0_0402_5%~D
2
RUN_ON_1.05V#
2
100K_0402_5%~D
EN_1.5VALW
C
C693
470P_0402_50V7K~D
2
R617
100K_0402_5%~D
6
+5V_ALW
8
7
6
5
R613
100K_0402_5%~D
R910
100K_0402_5%~D
1
4
2
3
4
1
2
3
+1.05V_M
2
GND
NC
2
C1081
470P_0402_50V7K~D
Q129A
2N7002DW-T/R7_SOT363-6~D
<43>
<33> 1.5V_RUN_ON
1.5 Volt +/-5%
Design Current:11mA
Peak current: 11mA
2
A
1
1
@ R1102
2
5
2
0_0402_5%~D
+15V_ALW
+1.5V_ALW_HDA
2
1
Q150A
M_ON 1
@ R1100
#SHDN
C1201
1U_0603_10V6K~D
2
2
1
+3.3V_ALW
Q150B
5
1
2
6
R1004 4.7K_0402_5%~D
Q136A
U103
MAX8511EXK15+T_SC70-5~D
1 IN
OUT 5
2
4
2N7002DW-7-F_SOT363-6~D
+3.3V_ALW
@ R621
470K_0402_5%~D
3
EN_1.05VALW <43>
2N7002DW-7-F_SOT363-6~D
1
2
3
R1034 4.7K_0402_5%~D
Q136B
4
1
2
2
100K_0402_5%~D
EN_1.05VALW
2
C698
4700P_0402_25V7K~D
2
+5V_ALW
5
@
1
1
1
+1.05V_VCCP Source
+3.3V_ALW2
2
3
2
6
1
1
@ R1103
A
Q64B
2N7002DW-T/R7_SOT363-6~D
ENAB_3VLAN <21>
R629
200K_0402_5%~D
+3.3V_ALW
Q74A
2N7002DW-T/R7_SOT363-6~D
2
5
+3.3V_RUN
2
+3.3V_ALW2
Q74B
2N7002DW-T/R7_SOT363-6~D
AUX_ON_R
1
2
@ D30
RB751V_SOD323-2~D
1
2
R609
0_0402_5%~D
6
1
2
S
Q61
SI4336DY-T1-E3_SO8~D
1
2
3
1
<33,39> 3.3V_RUN_ON
2
R620
100K_0402_5%~D
AUX_ON
R606
100K_0402_5%~D
1
1
2
1
2
1
1
D
8
7
6
5
Q64A
2N7002DW-T/R7_SOT363-6~D
1
R619
100K_0402_5%~D
+3.3V_ALW
1
3
1
S
S
ALW_ON_3.3V# 2
G
3
2
1
D
SUS_ON_3.3V# 2
G
+15V_ALW
3
3
1
1
4
6
1
B
D
2
G
@ Q82
2N7002W-7-F_SOT323-3~D
@ R628
1K_0402_5%~D
C696
4700P_0402_25V7K~D
2
+3.3V_ALW2
+15V_ALW
R608
100K_0402_5%~D
+3.3V_ALW_ICH
@ Q81
2N7002W-7-F_SOT323-3~D
@ R627
1K_0402_5%~D
2
S
+3.3V_SUS
1
Q68A
2N7002DW-T/R7_SOT363-6~D
S
D
2
G
3
2
1
D
2
1
S
G
3
2
3
2
1
1
1
1
1
2
4
R612
20K_0402_5%~D
M_ENABLE
D
RUN_ON_5V# 2
G
Q68B
2N7002DW-T/R7_SOT363-6~D
M_ON_3.3V# 5
+3.3V_M
C694
10U_0805_10V4Z~D
R610
100K_0402_5%~D
R611
100K_0402_5%~D
6
5
2
1
@ Q78
2N7002W-7-F_SOT323-3~D
@ R624
1K_0402_5%~D
+15V_ALW
+3.3V_ALW2
Q66
D
+3.3V_RUN Source
+3.3V_ALW2
+0.75V_DDR_VTT
@ Q77
@ R623
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
@ Q76
2N7002W-7-F_SOT323-3~D
@ R622
1K_0402_5%~D
+3.3VM Source
<34>
2
RUN_ON_3V#
+3.3V_ALW
1
4
+1.5V_RUN
S
5
R600
20K_0402_5%~D
2
1
1
2
2
1
1
2
+5V_RUN
3
1
C692
4700P_0402_25V7K~D
RUN_ON_1.05V# 2
G
Q56B
2N7002DW-T/R7_SOT363-6~D
2
2
<34,37> SUS_ON
M_ON
S
D
2
Q56A
2N7002DW-T/R7_SOT363-6~D
<19,21,33,37,39> RUN_ON
+5V_RUN
1
RUN_ENABLE
3
2
D
RUN_ON_3V# 2
G
3
1
4
6
1
2
2
3
5
Q62A
2N7002DW-T/R7_SOT363-6~D
1
2
S
G
3
1
2
Q62B
2N7002DW-T/R7_SOT363-6~D
SUS_ON_3.3V#
1
R605
20K_0402_5%~D
C690
10U_0805_10V4Z~D
2
4
Q79
2N7002W-7-F_SOT323-3~D
6
5
2
1
SUS_ENABLE
R604
100K_0402_5%~D
+3.3V_SUS
D
1
R603
100K_0402_5%~D
+3.3V_ALW2
RUN_ON_5V#
@ Q80
2N7002W-7-F_SOT323-3~D
@ R626
1K_0402_5%~D
Q60
S
+1.05V_VCCP
R625
39_0402_5%~D
+3.3V_SUS Source
+3.3V_ALW
<34>
1
1
+3.3V_RUN
+15V_ALW
C
3
2
1
2
2
ICH_ALW
S
C688
4700P_0402_25V7K~D
1
<34>
20K_0402_5%~D
2
G
R599
100K_0402_5%~D
Q55
STS11NF30L_SO8~D
1
2
3
6
2
Q57A
2N7002DW-T/R7_SOT363-6~D
2
G
D
8
7
6
5
1
4
6
5
M_ON_3.3V#
D
+5V_ALW
R597
100K_0402_5%~D
1
ALW_ON_3.3V#
1
R601
2
3
2
Q57B
2N7002DW-T/R7_SOT363-6~D
1
+15V_ALW
C689
2200P_0402_50V7K~D
C687
10U_0805_10V4Z~D
G
3
ALW_ENABLE
3
2
R602
100K_0402_5%~D
D
1
S
1
1
R598
100K_0402_5%~D
4
+3.3V_ALW2
C686
10U_0805_10V4Z~D
6
5
2
1
+5VRUN Source
@ Q72
2N7002W-7-F_SOT323-3~D
@ R616
1K_0402_5%~D
+3.3V_ALW2
+3.3V_M
@ Q71
2N7002W-7-F_SOT323-3~D
@R615
75_0603_5%~D
Q54
+3.3V_ALW_ICH
D
+3.3V_ALW
1
+1.05V_M
+15V_ALW
1
Discharg Circuit
+3.3V_ALW_ICH Source
DC/DC Interface
2
2
5
3
2
Title
POWER CONTROL
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
36
of
57
3
2
+3.3V_SUS
+3.3V_ALW
1
C
Q84
MMST3904-7-F_SOT323-3~D
A
8
Y
7
6
A
U39A
74LVC3G14DC_VSSOP8~D
+3.3V_ALW
2
Y
U39B
14
1
1
1
2
R636
0_0402_5%~D
<19,21,33,36,39> RUN_ON
2
IN1
OUT
C700
0.1U_0402_16V4Z~D
2
U40A
3
IN2
+3.3V_ALW
E
1
R639
4.7K_0402_5%~D
1
2
2
B
C705
2200P_0402_50V7K~D
C
P
+3.3V_ALW
Q86
MMST3904-7-F_SOT323-3~D
14
2
2
1
E
3
IN1
IN2
P
10
3.3V_5V_SUS_PWRGD 9
OUT
8
SUSPWROK <34>
U40C
7
<34,36> SUS_ON
G
1
2
R638
200K_0402_5%~D
C704
0.1U_0402_16V4Z~D
2
1
2
R637
1 10K_0402_5%~D
IN2
Q85
MMBT3906WT1G_SC70-3~D
B
1
U40B
RUNPWROK
6
RUNPWROK <33,34,45>
C
2
D33
RB751V_SOD323-2~D
5
OUT
7
3
+3.3V_RUN
IN1
G
4
+3.3V_ALW
1
D
14
3
E
P
2
R635
4.7K_0402_5%~D
1
2
2
B
C703
2200P_0402_50V7K~D
1
G
2
1
7
3
2
1
1
1
2
B
R634
200K_0402_5%~D
C702
0.1U_0402_16V4Z~D
2
E
1
D32
RB751V_SOD323-2~D
1
Q83
C
2
R633
10K_0402_5%~D
1
2
P
2
+5V_RUN
D
+3.3V_ALW
8
1
0_0402_5%~D
1
C699
0.1U_0402_16V4Z~D
2
P
2
R879
G
<44> 1.8V_RUN_PWRGD
+5V_ALW
1
4
1
0_0402_5%~D
R632
C701
100K_0402_5%~D 0.1U_0402_16V4Z~D
2
R630
1
@
<18,33> 2.5V_RUN_PWRGD
G
4
4
5
+1.5V_MEM
C
C
3
E
2
2
+3.3V_M
C1083
2200P_0402_50V7K~D
R917
4.7K_0402_5%~D
1
2
2
B
1
1
C
Q131
MMST3904-7-F_SOT323-3~D
R640
100K_0402_5%~D
E
3
+3.3V_ALW
2
1
ICH_PWRGD#
ICH_PWRGD# <18>
12
IN2
+3.3V_ALW
1
IN1
RESET_OUT#
D
S
P
13
11
OUT
ICH_PWRGD
Q87
2N7002W-7-F_SOT323-3~D
2
G
U40D
7
<34> RESET_OUT#
IMVP_PWRGD
G
<24,33,45,47> IMVP_PWRGD
3
14
2
2
1
2
R915
1 10K_0402_5%~D
R916
200K_0402_5%~D
C1082
0.1U_0402_16V4Z~D
B
1
C
2
D66
RB751V_SOD323-2~D
1
Q130
1
+1.5V_RUN
+3.3V_SUS
3
8
P
5
U39C
+3.3V_ALW
+3.3V_ALW
B
8
P
2
1
1
A
Y
G
2
D37
RB751V_SOD323-2~D
4
2
Q89
1
1
2
C709
0.1U_0402_16V4Z~D
1
R646
200K_0402_5%~D
2
R644
10K_0402_5%~D
1
2
2
C710
2200P_0402_50V7K~D
1
R645
200K_0402_5%~D
D36
RB751V_SOD323-2~D
2
1
3
+3.3V_M
1
G
Y
4
1
2
1
1
2
A
B
3
E
2
ICH_PWRGD <10,24>
C
B
1
C
B
E
C707
0.1U_0402_16V4Z~D
+3.3V_ALW
Q88
D35
RB751V_SOD323-2~D
2
1
R643
200K_0402_5%~D
2
R641
10K_0402_5%~D
1
2
2
C708
2200P_0402_50V7K~D
1
R642
200K_0402_5%~D
D34
RB751V_SOD323-2~D
2
1
+3.3V_ALW
3
8
P
1
2
A
1
6
A
Y
G
2
D41
RB751V_SOD323-2~D
4
1
1
C
2
B
Q91
R653
200K_0402_5%~D
2
C713
0.1U_0402_16V4Z~D
1
2
E
1
C715
2200P_0402_50V7K~D
2
C714
0.1U_0402_16V4Z~D
R652
200K_0402_5%~D
1
R651
10K_0402_5%~D
1
2
2
3.3V_M_PWRGD <18,34>
+3.3V_ALW
+3.3V_LAN
D40
RB751V_SOD323-2~D
2
1
7
U41A
2
3.3V_LAN_PWRGD <34>
U41B
A
5
4
3
2
Title
Power Good
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
37
of
57
H13
@H_2P8
H8
@H_2P8
H9
@H_2P8
Fiducial Mark
@
@
@
@
@
Q93
2N7002W-7-F_SOT323-3~D
<33>
H18
@H_2P5
H14
@H_2P5
H15
@H_2P5
1
2
3
<33> NUM_LED#
1
1
R_NUM_LED
2
1K_0402_5%~D
1
R_SCRL_LED
2
1K_0402_5%~D
R596
3
D75
PWR_BTN_BD_DET#
<33> PWR_BTN_BD_DET#
POWER_SW#_MB
<34> POWER_SW#_MB BREATH_BLUE_LED_PWR
INSTANT_ON_SW#
<33,34> INSTANT_ON_SW#
Q122
DDTA114EUA-7-F_SOT323-3~D
Q97
PDTA114EU_SC70-3~D
SDM10U45-7_SOD523-2~D
R655
1
1
D83
2
R_SCRL_LED
R_NUM_LED
R_CAP_LED
WWA N_LED
SDM10U45-7_SOD523-2~D
1
1
2 WLAN_LED
R663
1K_0402_5%~D
Q167 5@
PDTA114EU_SC70-3~D
@ R1036
100K_0402_5%~D
1
2
G
2N7002W-7-F_SOT323-3~D
1
2
BATT_YELLOW_LED_R
BATT_BLUE_LED_R
SATA_LED
WLAN_LED
BT_LED
MASK_BASE_LEDS#
2
Q168 5@
MASK_BASE_LEDS#
+5V_ALW
WLAN_LED_R
+5V_ALW
3
3
3
2
BKT_LED
BKT_LED
D
S
<39>
2N7002W-7-F_SOT323-3~D
+5V_RUN_BKT_PWR
1
2
3
4
5
6
GND
GND
JBIO5
G
MASK_BASE_LEDS#
1
2
3
4
5
6
7
8
TYCO_2041070-6
2 LED_W# 2
1
D
S
LED_WLAN# 1
1
Q98
JBIO4
R_CAP_LED
2
1K_0402_5%~D
2
<33> SCRL_LED#
Keyboard Status LED
1
R556
Q121
1
+5V_RUN
R662
100K_0402_5%~D
@
@
D
Q120
HDD LED solution for Blue LED
+3.3V_WLAN
H16
H17
@H_3P2X4P2N @H_2P2N
@
@
FIDUCIAL MARK~D
@
2
CAP_LED#
3
R659
2
@
@
2 SATA_LED
1K_0402_5%~D
1
D
3
@
1
MASK_BASE_LEDS#
<21> LED_WLAN_OUT#
@
+5V_ALW
1
FIDUCIAL MARK~D
@
1
@
1
@
FD4
1
FIDUCIAL MARK~D
@
1
1
1
1
@
1
G
2
@
2
FD3
1
3
2
D
S
SATA_ACT#
1
FD2
1
FIDUCIAL MARK~D
@
3
@
Q92
3
<23> SATA_ACT#_R
1
1
1
FD1
R654
10K_0402_5%~D
1
H12
@H_2P8
1
1
H11
@H_2P8
1
H7
H10
@H_2P7 @H_2P8
1
H6
@H_2P7
1
H5
@H_2P3
1
2
H4
@H_2P3
1
3
H1
H2
H3
@H_3P4N @H_3P4N @H_2P3
+5V_RUN
1
4
+3.3V_RUN
1
5
1
2
3
4
5
6
7
8
9
10
11
12
Q151
WLAN&BKT LED solution for Blue LED
1
6
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
13
14
TYCO_1-2041070-2
2
C
C
2
+3.3V_ALW
Q152A
MASK_BASE_LEDS# 2N7002DW-7-F_SOT363-6~D
C1162 0.1U_0402_16V4Z~D
1
2
2
2
1
3
1
2
2 BT_LED
1K_0402_5%~D
1
SYS_LED_MASK#
4
3
Q102
SNIFFER_BLUE
2
150_0402_5%~D
SNIFFER_YELLOW <21>
<29,33> LID_CL#
SNIFFER_BLUE <21><33> SYS_LED_MASK#
LID_CL#
1
SYS_LED_MASK# 2
5
4
3
+5V_ALW
Q161B
2N7002DW-7-F_SOT363-6~D
4
3 2
1
Q159
1
+3.3V_ALW
SYS_LED_MASK#
+5V_ALW
1
R1045
BREATH_BLUE_LED
2
1K_0402_5%~D
BREATH_BLUE_LED <19>
Q162B
2N7002DW-7-F_SOT363-6~D
4
3 2
Q160
MASK_BASE_LEDS#
1
R1047
A
BREATH_BLUE_LED_PWR
2
150_0402_5%~D
P
1
R668
0.1U_0402_16V4Z~D
2
U90
IN1
O
4
MASK_BASE_LEDS#
IN2
G
1
R667
3
@
SN IFFER_YELLOW
2
220_0402_5%~D
5
2
1
<33> SNIFFER_BLUE#
+3.3V_ALW
C1165
1
1
2
BATT_YELLOW_LED <19>
3
1
BREATH_LED#_R
2
BATT_BLUE_LED <19>
1K_0402_5%~D
R1043
150_0402_5%~D
1
2
5
+5V_ALW
A
Y
U89
R1042
5
1
3
G
A
6
2
<31,34> BREATH_LED#
NC
5
Q100
0.1U_0402_16V4Z~D
2
2
2
C1164
R1113
1
47K_0402_1%~D
1
X
0
1
1
0
1
1
P
1
@
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
R1046
100K_0402_5%~D
+3.3V_ALW
2
2
<33> SNIFFER_YELLOW#
6
LID_CL#
3
SYS_LED_MASK#
Q162A
Q161A
2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D
2
LED Circuit Control Table
R1044
100K_0402_5%~D
+3.3V_ALW
B
1
1
1
3
BT LED
+3.3V_ALW
Q153
2
1
1
3
2N7002W-7-F_SOT323-3~D
G
Q157B
2N7002DW-7-F_SOT363-6~D
1
+3.3V_ALW
Q156
Q158
3
R1041
100K_0402_5%~D
BAT1_LED
4
U88
5
R661
R1040
150_0402_5%~D
1
2
2
2
1
3
MASK_BASE_LEDS#
Y
D
Q95
2N7002W-7-F_SOT323-3~D
2
4
2
A
S
2
G
R1051
10K_0402_5%~D
U91
74LVC1G14GV_SOT753-5
NC
P
BAT1_LED# 2
<34> BAT1_LED#
2
G
BT_ACTIVE#
2
1
5
3
5
1
1
G
P
NC
BT_ACTIVE_R 3
4
6
Q157A
MASK_BASE_LEDS# 2N7002DW-7-F_SOT363-6~D
+3.3V_ALW
C1163 0.1U_0402_16V4Z~D
+3.3V_ALW
1
2
Q94
Y
D
A
S
2
+3.3V_ALW
Q155
1
1
@ R1039
100K_0402_5%~D
1
2
3
+3.3V_ALW
+5V_RUN
0.1U_0402_16V4Z~D
2
1
G
2 WWA N_LED
1K_0402_5%~D
WWAN LED solution for Blue LED
+3.3V_RUN
3
SYS_LED_MASK#
4
2
G
Q152B
2N7002DW-7-F_SOT363-6~D
1
<21,30> BT_ACTIVE
2N7002W-7-F_SOT323-3~D
5
Q116
2N7002W-7-F_SOT323-3~D
R125
B
Q154
D
Q115
PDTA114EU_SC70-3~D
BATT_YELLOW_LED_R
+5V_ALW
3
4
U87
2
MASK_BASE_LEDS#
C1152
1
1
1
Y
3
NC
P
L ED_WWAN#
1
3
G
A
R1038
100K_0402_5%~D
BAT2_LED
S
3
<21> LED_WWAN_OUT#
<34> BAT2_LED#
3
D
S
2
R206
100K_0402_5%~D
BAT2_LED# 2
BATT_BLUE_LED_R
2
1K_0402_5%~D
1
R1037
1
5
+5V_TP_PWR
+5V_ALW
1
+3.3V_RUN_BKT_PWR
3
2
Title
PAD and Standoff
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
38
of
57
3
2
1
+3.3V_BKT_PWR
<40> BKT_LVDS_RIN0<40> BKT_LVDS_RIN0+
+3.3V_RUN_WWAN_PWR Source
<40> BKT_LVDS_RIN2<40> BKT_LVDS_RIN2+
1
Q139
2N7002W-7-F_SOT323-3~D
BKT_USBHBKT_USBH+
BKT_GPIO5
For WWAN power source
<35> BKT_GPIO9
BKT_GPIO9
C
+3.3V_RUN_BKT_PWR Source
Q140
+3.3V_ALW
S
D
BKT_I2S_LRC <21>
BKT_I2S_DO <21>
BKT_I2S_SCLK <21>
BKT_MCLK
<21>
BKT_USBBIO- <40>
BKT_USBBIO+ <40>
BKT_LED
<38>
BKT_GPIO5
<35>
C
BKT_GPIO6
<35>
102
104
5@ Q143
+3.3V_BKT_PWR
Enable BKT power
D
1
R1020
20K_0402_5%~D
BKT_LVDS_CLK- <40>
BKT_LVDS_CLK+ <40>
MOLEX_55299-1071
6
5
2
1
4
G
C1139
470P_0402_50V7K~D
+3.3V_ALW2
+15V_ALW
5@
R1030
100K_0402_5%~D
5@
R1031
100K_0402_5%~D
For TP power source
1
2
5@
Q142
2N7002W-7-F_SOT323-3~D
1 R1055 2
@ 100K_0402_5%~D
BKT_LVDS_RIN1- <40>
BKT_LVDS_RIN1+ <40>
5@
B
1
2
BAT54CW_SOT323~D
2
GND
GND
+3.3V_ALW
1
<35> BKT_GPIO19
Q141
2N7002W-7-F_SOT323-3~D
2
GND
GND
1
2
D
13.3V_RUN_BKT_PWR_EN 2
G
B
1
BKT_GPIO19
1
3
3
3.3V_RUN_ON
S
1
2
G
D71
<33,36> 3.3V_RUN_ON
D
3
2
R1021
100K_0402_5%~D
1
2
3
G
C1138
10U_0805_10V4Z~D
4
2
1
101
103
S
6
5
2
1
R1019
100K_0402_5%~D
+3.3V_RUN_BKT_PWR
D
+15V_ALW
1
+3.3V_ALW2
1
1 R1054 2
@ 100K_0402_5%~D
BAT54CW_SOT323~D
<40> BKT_USBH<40> BKT_USBH+
C1140
10U_0805_10V4Z~D
S
13.3V_RUN_WWAN_PWR_EN
2
G
<35> BKT_GPIO15
C1137
470P_0402_50V7K~D
BKT_SMBCLK
BKT_SMBDAT
BKT_GPIO16
BKT_GPIO7
BKT_GPIO8
2
4 BKT_LVDS_RIN16 BKT_LVDS_RIN1+
8
10 BKT_LVDS_CLK12 BKT_LVDS_CLK+
14
16
18
20
22
24
26
BKT_I2S_LRC
28
30
BKT_I2S_DO
32
BKT_I2S_SCLK
34
36
BKT_MCLK
38
40
42
44
46
48
50
BKT_USBBIO52
BKT_USBBIO+
54
56
58
60
62
BKT_LED
64
66
68
70
72
BKT_GPIO5
74
76
78
80
82
84
86
88
90
92
94
96
98
BKT_GPIO6
100
2
2
D
2
S
2
<34> BKT_SMBCLK
<34> BKT_SMBDAT
<35> BKT_GPIO16
<35> BKT_GPIO7
<35> BKT_GPIO8
VSS
Odd Rin1Odd Rin1+
VSS
Odd ClkOdd Clk+
VSS
Even Rin1Even Rin1+
VSS
Even ClkEven Clk+
VSS
I2S_LRC
I2S_DIN
I2S_DOUT
I2S_SCLK
VSS
M_Clk
VSS
VDD 3.3v 5%
VDD 3.3v 5%
VDD 3.3v 5%
VSS
VSS
BioMetric
BioMetric
VSS
Reserved
Reserved
VSS
Reserved
Reserved
Reserved
Reserved
VSS
LID Closed
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PAID_Out
S
1
BKT_GPIO15
1
3
3
<33,36> 3.3V_RUN_ON
Q138
2N7002W-7-F_SOT323-3~D
3
D70
3.3V_RUN_ON
1
D
2
G
1
2
C1136
10U_0805_10V4Z~D
G
3
2
1
4
2
R1018
100K_0402_5%~D
+3.3V_RUN_WWAN_PWR
S
6
5
2
1
R1016
100K_0402_5%~D
BKT_LVDS_RIN2BKT_LVDS_RIN2+
D
+3.3V_ALW
1
+15V_ALW
BKT_LVDS_RIN0BKT_LVDS_RIN0+
3
Q137
+3.3V_ALW2
R1017
20K_0402_5%~D
D
+3.3V_BKT_PWR
5@
JBKT1
1 PAID_IN
3 Odd Rin05 Odd Rlin0+
7 VSS
9 Odd Rin211 Odd Rin2+
13 VSS
15 Even Rin017 Even Rlin0+
19 VSS
21 Even Rin223 Even Rin2+
25 VSS
27 SMBCLK
29 SMBDATA
31 SMBALERT
33 RST35 USB_SEL_BLK
37 VSS
39 VSS
41 VDD 3.3v 5%
43 VDD 3.3v 5%
45 VDD 3.3v 5%
47 VSS
49 VSS
51 USB Host Port Data53 USB Host Port Data+
55 VSS
57 Reserved
59 Reserved
61 VSS
63 GPIO
65 SM CLK
67 SK DAT
69 SM Alert
71 VSS
73 Radio_OFF
75 Reserved
77 Reserved
79 Reserved
81 Reserved
83 Reserved
85 Reserved
87 Reserved
89 Reserved
91 Reserved
93 Reserved
95 Reserved
97 Reserved
99 VSS
2
4
R1022
20K_0402_5%~D
5
S
3
1
1
2
G
1
1
2
3
2
BAT54CW_SOT323~D
1
<19,21,33,36,37> RUN_ON
5V_RUN_BKT_PWR_EN
D
3
1
RUN_ON
1
S
2
BKT_GPIO4 3
S
2
G
1 R1056 2
@ 100K_0402_5%~D
5@
R1025
D72
5@
Q147
2N7002W-7-F_SOT323-3~D
5@
Q149
2N7002W-7-F_SOT323-3~D
4
C1142
2200P_0402_50V7K~D
5@
5@
Q146
2N7002W-7-F_SOT323-3~D
S
BKT_GPIO2 2
G
+5V_RUN_BKT_PWR
6
5
2
1
2 5@
D
1
5@ Q145
5@
20K_0402_5%~D
5@
R1024
100K_0402_5%~D
5@
R1023
100K_0402_5%~D
2
G
<35,40> BKT_GPIO4
5@
C1150
470P_0402_50V7K~D
Q144A
2N7002DW-7-F_SOT363-6~D
LDDC_DATA_MCH
1
6
<12> LDDC_DATA_MCH
+3.3V_RUN
LDDC_CLK_MCH
<12> LDDC_CLK_MCH
LDDC_DATA_MCH_LVDS
LDDC_DATA_MCH_LVDS <19>
LVDS connector side
5 2
+5V_ALW
C1141
10U_0805_10V4Z~D
2
1
+15V_ALW
D
+3.3V_ALW2
D
3
<35> BKT_GPIO2
A
2
3
+5V_RUN_BKT_PWR Source
1
D
2
5@
G
Q148
S
2N7002W-7-F_SOT323-3~D
4
3
LDDC_CLK_MCH_LVDS
LDDC_CLK_MCH_LVDS <19>
A
EDID signals drive low
when BlackTop mode
Q144B
2N7002DW-7-F_SOT363-6~D
For AMP/TP power source
Title
BlackTopI
Size
Document Number
Date:
Rev
1.0
LA-4151P
5
4
3
2
Sheet
1
39
of
57
5
4
2
1
Normal mode BKT mode
0
1
BKT_GPIO4
0
1
BKT_GPIO11
0
1
BKT_GPIO3
Normal mode
1
D
BKT mode Diag mode
0
1
5@
U84
+3.3V_RUN_BKT_PWR
<19> SW_LVDS_A2+
<19> SW_LVDS_A2-
5@
U97
C
8
BKT_USBH-
<35> BKT_GPIO3
NC
7
D-
5
USBP1-
D+
3
USBP1+
GND
4
VCC
6
HSD-
BKT_USBH+
2
HSD+
BKT_GPIO3
1
OE#
11
12
COM3+
COM3-
NC1+
NC1-
38
37
LCD_A0+_MCH
LCD_A0-_MCH
NO1+
NO1-
34
33
BKT_LVDS_RIN0+
BKT_LVDS_RIN0-
USBP1+ <24>
BKT_GPIO1
<35> BKT_GPIO1
Com_to
_NC
Com_to
_NO
0
1
ON
OFF
OFF
ON
1
4
10
14
17
19
21
39
41
43
Add SB<-->BKT by USB interface when diagnostic mode
For WWAN
From SB signals
B
<24>
USBP5+
<24>
USBP5-
<39> BKT_USBH+
<39> BKT_USBH-
9
SEL
BKT_GPIO3 Logic"0" on Diag mode
5@
C1148
1
COM4+
COM4-
USBP1- <24>
TS3USB31RSER_QFN8_1P5X1P5~D
5@
U85
15
16
MAX4889
SEL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SEL Logic"1" Work from BKT
1
1D+
VCC
USBP5-
2
1D-
S
9
BKT_GPIO4
BKT_USBH+
3
2D+
D+
8
USB_SW_USBD+
BKT_USBH-
4
2D-
D-
7
USB_SW_USBD-
5
GND
OE#
6
10
+3.3V_RUN_BKT_PWR
BKT_GPIO4 <35,39>
TS3USB221RSER_QFN10_2x1P5~D
S Logic"1" Work from BKT
USB_SW_USBD+ <21> To
6@ RN1
1
2
USBP5USBP5+
NC2+
NC2-
36
35
NO2+
NO2-
32
31
BKT_LVDS_RIN1+
BKT_LVDS_RIN1-
NC3+
NC3-
29
28
LCD_A2+_MCH
LCD_A2-_MCH
NO3+
NO3-
25
24
BKT_LVDS_RIN2+
BKT_LVDS_RIN2-
NC4+
NC4-
27
26
LCD_ACLK+_MCH
LCD_ACLK-_MCH
NO4+
NO4-
23
22
BKT_LVDS_CLK+
BKT_LVDS_CLK-
FP_USBD+
FP_USBD-
<39> BKT_USBBIO+
A
<39> BKT_USBBIO-
1
1D+
VCC
FP_USBD-
2
1D-
S
9
BKT_GPIO11
BKT_USBBIO+
3
2D+
D+
8
FP_SW_USBD+
D-
7
FP_SW_USBD-
OE#
6
2D-
5
GND
10
BKT_LVDS_RIN0+ <39>
BKT_LVDS_RIN0- <39>
C
LCD_A1+_MCH <12>
LCD_A1-_MCH <12>
BKT_LVDS_RIN1+ <39>
BKT_LVDS_RIN1- <39>
LCD_A2+_MCH <12>
LCD_A2-_MCH <12>
BKT_LVDS_RIN2+ <39>
BKT_LVDS_RIN2- <39>
LCD_ACLK+_MCH <12>
LCD_ACLK-_MCH <12>
BKT_LVDS_CLK+ <39>
BKT_LVDS_CLK- <39>
MAX4889ETO+_TQFN42_3P5x9~D
WWAN signals
0_0404_4P2R_5%~D
USB_SW_USBD- <21>
S
OE#
Function
X
H
L
H
L
L
Disconnect
D=1D
D=2D
SW_LVDS_A0SW_LVDS_A0+
Bypass BKT function
6@ RN2
1
2
4LCD_A0-_MCH
3LCD_A0+_MCH
0_0404_4P2R_5%~D
6@ RN5
1
2
6@ RN3
1
2
B
4LCD_A2-_MCH
3LCD_A2+_MCH
0_0404_4P2R_5%~D
6@ RN4
SW_LVDS_ACLK- 1
SW_LVDS_ACLK+ 2
4LCD_A1-_MCH
3LCD_A1+_MCH
4LCD_ACLK-_MCH
3LCD_ACLK+_MCH
0_0404_4P2R_5%~D
+3.3V_RUN_BKT_PWR
BKT_GPIO11 <35>
FP_SW_USBD+ <29>
FP_SW_USBD- <29>
To Fingerprint signals
TS3USB221RSER_QFN10_2x1P5~D
S Logic"1" Work from BKT
LCD_A0+_MCH <12>
LCD_A0-_MCH <12>
0.1U_0402_16V4Z~D
2
FP_USBD+
4
2
Bypass BKT function
5@
C1149
1
5@
U86
BKT_USBBIO-
1
LVDS switch when system
on power mode or BKT mode
4USB_SW_USBD3USB_SW_USBD+
For Biometric
<32>
2
LCD_A1+_MCH
LCD_A1-_MCH
0_0404_4P2R_5%~D
<32>
2
5@
1
0.1U_0402_16V4Z~D
2
USBP5+
From USH signals
1
0.1U_0402_16V4Z~D
SW_LVDS_A2+
SW_LVDS_A2-
COM1+
COM1-
C1145
COM2+
COM2-
SW_LVDS_ACLK+
SW_LVDS_ACLK-
<19> SW_LVDS_ACLK+
<19> SW_LVDS_ACLK-
5@
6
7
2
3
0.1U_0402_16V4Z~D
C1147
<19> SW_LVDS_A1+
<19> SW_LVDS_A1-
5@
SW_LVDS_A1+
SW_LVDS_A1-
SW_LVDS_A0+
SW_LVDS_A0-
<19> SW_LVDS_A0+
<19> SW_LVDS_A0-
+3.3V_RUN_BKT_PWR
5
8
13
18
20
30
40
42
V+
V+
V+
V+
V+
V+
V+
V+
0.1U_0402_16V4Z~D
C1146
BKT_GPIO1
D
3
S
OE#
Function
X
H
L
H
L
L
Disconnect
D=1D
D=2D
FP_USBD+
FP_USBD-
6@ RN6
1
2
4FP_SW_USBD+
3FP_SW_USBDA
0_0404_4P2R_5%~D
Bypass BKT function
Title
BlackTopII
Size
Document Number
Date:
Rev
1.0
LA-4151P
5
4
3
2
Sheet
1
40
of
57
5
4
3
2
1
+COINCELL
1
COIN RTC Battery
PR271
1K_0402_5%~D
JRTC2
+COINCELL
<23> RTC_BAT_DET#
Z4012
2
+3.3V_RTC_LDO
1
2
3
4
5
+3.3V_ALW
1
+3.3V_ALW
PC3
0.1U_0603_25V7K~D
2
1
PR7
100_0402_5%~D
1
2
Z4304
Z4305
Z4306
PR8
100_0402_5%~D
1
2
PR9
100_0402_5%~D
1
2
PBAT_SMBCLK <34>
PBAT_SMBDAT <34>
PR10 @
100_0402_5%~D
1
2
PBAT_ALARM#
PBATT+
PAD-OPEN 4x4m
PBAT_PRES#
<33>
PQ47
PD22
RB751V_SOD323~D
1
2
FDN338P_NL_SOT23-3~D
3
PC4
2200P_0402_50V7K~D
2
1
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
2
1
FOX_BP02093-P5652-7F~D
GND
GND
1
Move to power schematic
PR6
10K_0402_1%~D
2
1
PJP12
PBATT+_C
11
10
PC244
1U_0603_10V4Z~D
1
PD8
DA204U_SOT323~D @ DA204U_SOT323~D
1
@
1
@
1
Primary Battery Connector
PD28
BAT54CW_SOT323~D
1
<BOM Structure>
27.4
2
2
3
2
3
2
3
2
3
PL2
FBMA-L18-453215-900LMA90T_1812~D
1
2
PD6
PD7
DA204U_SOT323~D
@
D
+RTC_CELL
ESD Diodes
PD5
DA204U_SOT323~D
GND
GND
MOLEX_53780-0370~D
3
2
D
1
2
3
1
3
DOCK_SMB_ALERT# <31,34>
2
2
PBATT1
PR20
0_0402_5%~D
1
2
2
3
PR11
2.2K_0402_5%~D
1
2
6
V+
5
+5V_ALW
3
NC
COM
4
PS_ID
GPIO_PSID_SELECT <33>
<34>
PD11
DA204U_SOT323~D
@
1
1
2
3
2
S
2
G
IN
GND
+5V_ALW
+5V_ALW
E
PR17
1
@
2
PSID_DISABLE# <33>
10K_0402_5%~D
+DC_IN_SS
1
2
PC9
10U_1206_25V6M~D
PR19
4.7K_0805_5%~D
2
1
PC8
0.1U_0603_25V7K~D
2
1
4
PC7
0.1U_0603_25V7K~D
2
1
4
1
PR16
2
DC_IN+ Source
PR22
22K_0402_1%~D
2
1
@
@
1
PR285
D
S
1
1
2
G
100K_0402_5%~D
2
NB_AC_OFF <33,46,48>
A
PC11
0.1U_0603_25V7K~D
2
5
3
PQ5
RHU002N06_SOT323
PQ4A
IMD2AT-108_SC74-6~D
<48> NB_AC_OFF_BJT
6
A
PC414
0.1U_0603_25V7K~D
2
1
1
PL21
FBMJ4516HS720NT_1806~D
1
2
3
2
2
1M_0402_5%~D
PQ4B
IMD2AT-108_SC74-6~D
@
PC5
0.022U_0603_50V7K~D
1
2
+D C_IN
PR21
1M_0402_5%~D
2
1
MOLEX_87438-0743
NO
2
8
7
6
5
PC6
0.1U_0603_25V7K~D
2
1
1
2
3
2
1
PR272
0_0402_5%~D
+ DCIN_JACK
PD29
VZ0603M260APT_0603
PC413
0.1U_0603_25V7K~D
2
1
-D CIN_JACK
PC412
0.1U_0603_25V7K~D
2
1
1
2
3
4
5
6
7
1
PQ2
FDS6679AZ_SO8~D
+DC_IN
PL20
1
2
1
2
3
4
5
6
7
NB_PSID_TS5A63157
1
B
@
PJPDC1
PU1
<31> DOCK_PSID
DCIN_CBL_DET# <33>
PC183
.47U_0402_6.3V6-K~D
1
2
B
C
TS5A63157DCKR_SC70-6~D
PQ1
FDV301N_SOT23~D
PQ3
MMST3904-7-F_SOT323~D
2
B
PR18
15K_0402_1%~D
1
2
GND
1
@
3
C
@
PD10
SM24_SOT23
2
3
PD12
DA204U_SOT323~D
1
+5V_ALW
PR13
33_0402_5%~D
1
2
1
3
PR14
100K_0402_1%~D
1
2
1
2
NB_PSID
D
PL3
BLM18BD102SN1D_0603~D
2
1
GND
3
1
2
0_0402_5%~D
+3.3V_ALW
1
PR12
PR15
10K_0402_1%~D
@
PD9
DA204U_SOT323~D
+5V_ALW
PR334
1
2
0_0402_5%~D
PC38
1500P_0402_50V7K~D
2
1
GND
C
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+DCIN
Size
Document Number
Date:
Rev
0.2
LA-4151P
Sheet
1
41
of
57
5
4
3
2
1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP/ +3.3V_RTC_LDO
+DC1_PWR_SRC
PC64
10U_1206_25V6M~D
2
1
2
1
PC15
10U_1206_25V6M~D
2
1
PC14
10U_1206_25V6M~D
PQ7
3.3 Volt +/-5%
Thermal Design Current: 8.4A
Peak current: 12A
OCP_min:12.4A
PL7
HMP1350-2R8 16A
@
+5V_ALW_LGATE
PC30
330U_D3L_6.3VM_R18~D
2.2_1206_5%~D
PC32
0.1U_0402_10V7K~D
2
1
1
2
2
PR290
1
PC222
470P_0402_50V7K
PQ9
FDS6676AS_NL_SO8~D
3
D
G
S
2
C
+3.3V_ALWP
1
PC191
1000P_0603_50V7K~D
PR35
0_0402_5%~D
2
1
2
GNDA_3V5V
+3.3V_ALWP
PR39
0_0402_5%~D
2
1
S
1
FDMS8692_POWERPAK
D
3
PC25
0.1U_0402_10V7K~D
2
1
G
1
PC28
0.1U_0603_25V7K~D
1
2
PR37
4.7_0603_5%~D
+3.3V_ALW_BOOT1
2
2
GNDA_3V5V
+3.3V_ALW_LGATE
2
PC13
0.1U_0805_50V7K
2
1
PC12
2200P_0402_50V7K~D
2
1
1
RE FIN2
@
PR31
200K_0402_1%~D
1
2
+3.3V_OUT2
2 PR33 0_0402_5%~D
1
POK2
EN_3V_5V
+3.3V_ALW_UGATE
+3.3V_ALW_PHASE
BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2
32
31
30
29
28
27
26
25
1
PR38
2
TON
+5V_ALW2P
V IN
+3.3V_ALW2
EN_3V_5V
8
7
6
5
4
3
2
1
LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF
PQ6
PQ8
REFIN2
ILIM2
OUT2
SKIP#
POK2
EN2
UGATE2
PHASE2
17
18
19
20
21
22
23
24
GNDA_3V5V
PR36
1_0603_5%~D
1
2 +5V_ALW_BOOT
PR30
@
1
2
0_0402_5%~D
PR28
@ PR29
0_0603_5%~D
BYP
OUT1
FB1
PU2
ILIM1
POK1 MAX8778_QFN32~D
EN1
UGATE1
PHASE1
0_0402_5%~D
GNDA_3V5V
2
2
S
1
0_0402_5%~D
PC27
0.1U_0603_25V7K~D
2
1
2
G
FDS6676AS_NL_SO8~D
2
PR288
2.2_1206_5%~D
1
SECFB
1
3
D
2
1000P_0603_50V7K~D
5V_3V_REF
PC24
0.1U_0603_25V7K~D
1
2
1
2
PR34
B YP9
PR32 +5V_OUT1
10
+5V_FB1
187K_0402_1%~D
11
12
1
2
GNDA_3V5V
POK1
13
EN_3V_5V
14
+5V_ALW_UGATE
15
+5V_ALW_PHASE
16
1
PC189
2
+
1
1
PC31
0.1U_0402_10V7K~D
2
1
PC29
330U_D3L_6.3VM_R18~D
1
2
@
0_0402_5%~D
1
+5V_ALWP
@
PAD
PL6
HMP1350-2R8 16A
+5V_ALWP
33
S
+5V_ALWP
C
PC26
0.1U_0402_10V7K~D
2
1
G
FDMS8692_POWERPAK
D
3
LDO REFIN
D
PC23
1U_0603_10V6K~D
2
1
PC20
4.7U_0805_6.3V6K
2
1
PC22
0.1U_0603_25V7K~D
2
1
@ PR27
0_0402_5%~D
1
2
GNDA_3V5V
GNDA_3V5V
PR25
10_0603_5%~D
2
1
PR26
0_0402_5%~D
1
2
+3.3V_RTC_LDO
2
+5V_VCC1
2
PAD-OPEN1x1m
PR284
0_0402_5%~D
2
1
5 Volt +/-5%
Thermal Design Current:8.33A
Peck current: 11.97A
OCP_min:13A
PJP15
1
+5V_ALW2
+3.3V_ALW2
PC21
0.1U_0603_25V7K~D
2
1
PC63
10U_1206_25V6M~D
2
1
PC19
10U_1206_25V6M~D
2
1
PC18
10U_1206_25V6M~D
2
1
PC17
0.1U_0805_50V7K
2
1
PC16
2200P_0402_50V7K~D
2
1
D
PR24
0_0805_5%
1
2
PL15
1
2
PR23
0_0805_5%
1
2
+PWR_SRC
1
+
2
GNDA_3V5V
+3.3V_ALWP
PAD-OPEN1x1m
GNDA_3V5V
PD16
BAT54CW_SOT323~D
3
Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R18
Sanyo_6TPE330ML)*1
H_MOSFET FDMC8878
L_MOSFET FDS6676AS(5.9/[email protected], 14.5A)
Inductor 2.8U_SSC-1350F3-2R8-R_16A(TNP)
PR43
0_0402_5%~D
2
1
<18> THERM_STP#
BAT54SW-7-F_SOT323-3~D
PR45
0_0402_5%~D
2
1
B
@
POK2
PD15
2
PR42
2K_0402_5%~D
2
1
3
Component select
Input CAP 10uF_1206_25V *2
<34> ALWON
Output Cap 330uF_D3L_6.3VM_R18(Sanyo_6TPE330ML)*1
H_MOSFET FDMC8878
L_MOSFET FDS6676AS(5.9/[email protected], 14.5A)
Inductor 2.8U_SSC-1350F3-2R8-R_16A(TNP)
POK1
ALW_PWRGD_3V_5V <34>
PJP26
PJP17
+15V_ALW
+5V_ALW
2
1
+15V_ALWP
PAD-OPEN 4x4m
PAD-OPEN1x1m
(100mA,20mils ,Via NO.=1)
PJP19
+3.3V_ALWP
1
2
PR46
200K_0402_1%~D
2
1
+3.3V_ALW
PAD-OPEN 4x4m
PJP29
1
2
2
PAD-OPEN 4x4m
PJP18
1
2
PR49
39K_0402_1%~D
1
+5V_ALWP
2
PC37
0.1U_0603_25V7K~D
2
1
1
VOUT2=3.3V
L=3.3uF
Fsw=300KHz
D=0.173
Input Ripple Current=TDC*(D*(1-D))^0.5=2.98A
Output ripple current=(19-3.3)*0.173/2.8u/300K=3.23A
Output ripple Voltage=3.23*25=58.14mV
+3.3V_ALWP
PR41
100K_0402_1%~D
1
2
PC36
0.1U_0603_25V7K~D
1 1
2
2
2
PR40
100K_0402_1%~D
1
2
PD14
BAT54SW-7-F_SOT323-3~D
1
PC35
0.1U_0603_25V7K~D
2
1
3
PJP16
1
PR44
200K_0402_5%
1
2
B
2
+5V_ALW2
+5V_ALWP
VOUT2=5V
L=3.3uF
Fsw=200KHz
D=0.263
Output Ripple Current=(19-5)*0.263/2.8u/200K=6.57A
Output Ripple Voltage=6.57*18m=118mV
PC33
0.1U_0603_25V7K~D
1 1
2
PC34
1U_0603_10V6K~D
2
1
GNDA_3V5V
GNDA_3V5V
PAD-OPEN 4x4m
GNDA_3V5V
A
A
Title
5
4
3
2
DC/DC +3V/ +5V
Size
Document Number
Date:
Rev
0.2
LA-4151P
Sheet
1
42
of
57
5
4
3
2
1
+1.5V_SUS_P / +1.05V_M
PJP49
DC_5V_ALW2
1
2
+5V_ALW
D2
VX
D1
+1.05V_VX
@ PR48
0_0402_5%~D
PC417
0.1U_0603_25V7K~D
2
1
PC418
0.1U_0603_25V7K~D
2
1
@
@
2
2
@
PC432
6800P_0402_25V7K~D
PJP22
PC431
0.1U_0603_25V7K~D
2
1
2
1
VSENSE2
PC430
22U_1206_6.3V6M~D
2
1
PR47
0_0402_5%~D
1
C2
C1
B4
1.05V_POK2 B5
AVDD2B3
2
GND
GND
STAT
TEMP
AVDD
IRIPL
B2
PR274
31.6K_0402_1%~D
PR276
1_0805_5%~D
PR286
PC429
22U_1206_6.3V6M~D
2
1
C3
PC428
22U_1206_6.3V6M~D
2
1
GND
PC427
22U_1206_6.3V6M~D
2
1
AGND
1000P_0603_50V7K~D
PC426
22U_1206_6.3V6M~D
2
1
B1
+1.05V_MP
PC187
PC425
22U_1206_6.3V6M~D
2
1
C4
PC424
22U_1206_6.3V6M~D
2
1
C5
VDD
PL22
0.2UH +-25%_ MPC0730LR20C_17.5A
1
PC423
22U_1206_6.3V6M~D
2
1
VDD
OE
2
PC422
10U_1206_25V6M~D
2
1
VSENSE+
44.2K_0402_1%
PR275
3.09K_0402_1%
PC420
2200P_0402_50V7K~D
2
1
PR277
38.3K_0402_1%
PC416
10U_1206_25V6M~D
2
1
D4
D3
VX
A5
1
C
D
1.05 Volt +/-5%
Peack current: 6.5A
OCP_MIN: 10A
VX
E1
D5
VX
E2
GND
GND
E4
E3
VT351AFCX-ADJ
VDES
VX
2
EN2
PU25
R_SEL/ILOAD
@
PC421
10U_1206_25V6M~D
2
1
VSENSE2 A4
BIAS
1
A3
GND
E5
+1.05V_VDES
VDD
A1
+1.05V_R_SEL/LOADA2
VDD
PC419
0.22U_0402_10V7K~D
2
1
D
PC415
10U_1206_25V6M~D
2
1
1
GND
1
PR273
10_0402_1%~D
AVDD2
PC65
10U_1206_25V6M~D
2
1
2
PAD-OPEN 4x4m
GNDA_1.05V
PR53
1
C
PAD-OPEN1x1m
GNDA_1.05V
2
0_0402_5%~D
PJP50
DC_5V_ALW1
1
2
+5V_ALW
C2
C1
B5
1
B4
2
GND
GND
STAT
TEMP
AVDD
IRIPL
B3
B2
PR50
PJP20
VSENSE1
2
PAD-OPEN1x1m
@ PR51
0_0402_5%~D
1
GNDA_1.5V
PC436
0.1U_0603_25V7K~D
2
1
@
2
GNDA_1.5V
PJP25
1
1
PR279
24K_0402_1%~D
44.2K_0402_1%
2
56K_0402_1%
PR281
0_0402_5%~D
2
1
PR282
PC438
2200P_0402_50V7K~D
2
1
1.5V_POK1
AVDD1
PR280
3.74K_0402_1%~D
1_0805_5%~D
PR287
25V,X7R,10% PC448
6800P_0402_25V7K~D
C3
PC447
0.1U_0603_25V7K~D
2
1
GND
PC446
22U_1206_6.3V6M~D
2
1
AGND
+1.5V_SUS_P
1000P_0603_50V7K~D
PC445
22U_1206_6.3V6M~D
2
1
B1
B
PC188
PC444
22U_1206_6.3V6M~D
2
1
C4
PL23
0.2UH +-25%_ MPC0730LR20C_17.5A
1
PC443
22U_1206_6.3V6M~D
2
1
C5
VDD
2
PC442
22U_1206_6.3V6M~D
2
1
VDD
OE
+1.5V_VX
PC441
22U_1206_6.3V6M~D
2
1
D1
PC439
10U_1206_25V6M~D
2
1
D2
VX
VSENSE+
PR54
0_0402_5%~D
PC435
0.1U_0603_25V7K~D
2
1
D4
VX
A5
1
1.5 Volt +/-5%
Peak current: 10.7A
OCP_MIN:15A
VX
D5
VX
E1
GND
GND
E3
E4
VDD
GND
E2
PU26
VT351AFCX-ADJ
2
EN1
VDES
D3
1
VSENSE1 A4
B
R_SEL/ILOAD
VX
2
+1.5V_VDES A3
BIAS
1
+1.5V_R_SEL/LOAD A2
VDD
E5
PC437
0.22U_0402_10V7K~D
2
1
1
BIASA1
PC434
10U_1206_25V6M~D
2
1
GND
AVDD1
PC440
10U_1206_25V6M~D
2
1
PR278
10_0402_1%~D
PC433
10U_1206_25V6M~D
2
1
2
PAD-OPEN 4x4m
2
+3.3V_ALW +3.3V_ALW
2
+1.5V_MEM
PAD-OPEN 4x4m
A
EN2
PR64
0_0402_5%~D
1
2
1.05V_POK2
EN_1.05VALW <36>
1.5V_POK1
5
1.5V_POK1
PC449
0.1U_0402_10V7K~D
2
1
1
PR66
100K_0402_1%~D
1
2
PJP24
+1.5V_SUS_P
PR283
0_0402_5%~D
2
1
PR65
100K_0402_1%~D
2
1
PAD-OPEN 4x4m
@
A
PJP23
1.05V_M_PWRGD <34>
<36> EN_1.5VALW
@
EN1
+1.05V_MP
1
2
+1.05V_M
PAD-OPEN 4x4m
Title
<10,34>
4
1.5V_SUS_PWRGD <10,34>
3
2
+1.5V_RUN / +1.05V_VCCP
Size
Document Number
Date:
Rev
0.2
LA-4151P
Sheet
1
43
of
57
5
4
3
2
1
+1.8VRUN/ +0.75V_DDR_VTT
DDR3 Termination
D
D
+0.75V_P
+5V_ALW
+V_DDR_MCH_REF
0.75Volt +/-5%
Peak current: 2A
PU24
2 VLDOIN
1DC_1+0.75V_VTT_PWR_SRC
2
PAD-OPEN 2x2m~D
<10,34,36> DDR_ON
PC410
0.1U_0603_25V7K~D
2
1
PC348
10U_0805_6.3V6M~D
1
2
<33> 0.75V_DDR_VTT_ON
1
VDDQSNS
7
S3
9
S5
3
VTTSNS
5
VTTREF
6
PGND
GND
BP
4
8
11
TPS51100DGQRG4_MSOP10~D
PC343
10U_0805_6.3V6M~D
1
2
VTT
PC342
10U_0805_6.3V6M~D
1
2
PJP48
+1.5V_SUS_P
VIN
PC345
1U_0603_10V6K~D
1
2
10
PJP45
2
+0.75V_P
1
+0.75V_DDR_VTT
PAD-OPEN 2x2m~D
C
C
1.8 Volt +/-5%
Design Current: 221.3mA
Max current: 316.3mA
DC_1+1.8V_RUN_PWR_SRC
+3.3V_ALWP
PC184
PJP28
2
1
10U_0805_6.3V6M~D
PAD-OPEN 2x2m~D
2
1
+3.3V_ALW
PU12
PC181
1U_0603_10V6K~D
2
1
5V_3V_REF
PR270
10K_0402_1%
1
2
PR135
91K_0402_1%~D
1
2
2
VCC
PGND
8
5
PGOOD
AGND
3
7
SHDN#
OUTS
6
4
REFIN REFOUT
BP
1
11
1.8V_OUT
2
+1.8V_RUN
1
B
PAD-OPEN 2x2m~D
1
9
2
<33> 1.8V_RUN_ON
PC182
1U_0603_10V6K~D
2
1
<37> 1.8V_RUN_PWRGD
PJP27
OUT
PC180
10U_0805_6.3V6M~D
1
2
B
MAX8794
10 IN
PC178
1U_0603_10V6K~D
1
2
PR134
@ 100K_0402_5%~D
2
1
PC179
10U_0805_6.3V6M~D
PGND and GND sholud be tied
together at one point near the GND Pin
A
A
Title
5
4
3
2
+1.8VSUSP/ +0.75V_DDR_VT
Size
Document Number
Date:
Rev
0.2
LA-4151P
Sheet
1
44
of
57
7
6
5
4
3
2
1
GNDS
11
VPS
2
1500P_0402_50V7K~D
1
2
B
GNDA_VCORE
@ PR131
10.5K_0402_1%
2
1
@ PR132
1K_0402_1%~D
2
1
2
1
2
PC133
1000P_0402_50V7K~D
1
PC132
2
1
1
@
1000P_0402_50V7K~D
GNDA_VCORE
PC131
@
PC134
0.01U_0402_16V7K~D
A
@
1000P_0402_50V7K~D
@
2
1
PR137
1K_0402_1%~D
1
2
PR136
732_0402_1%~D
@ PC129
2
1
7
PC89
100U_25V_M~D
PC88
100U_25V_M~D
1
2
PC94
10U_1206_25V6M~D
2
1
PC93
10U_1206_25V6M~D
1
2
D
D
D
D
2
1
1
2
1
2
2
2
1
PQ18
2
3
D
1
1
2
@
PC105
10U_1206_25V6M~D
2
1
1
1
1
PC110
PR106
1000P_0603_50V7K~D
4.7_1206_5%~D
PC109
1UU_0603_25V5K~D
2
1
PR109
430_0402_1%~D
1
2
PR267
0_0402_5%~D
D
1
2
PQ20
2
PC104
10U_1206_25V6M~D
2
PC103
2200P_0402_50V7K~D
2
1
2
1
PC102
0.1U_0603_25V7K~D
2
1
8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4
3
G
PR111
7.68K_0805_1%~D
PR112
0_0402_5%~D
@
PR121
0_0402_5%~D
@
VSUM
C SN2 2
VO
B
@
PWR_MON
@
1
2
<18>
A
GNDA_VCORE
Title
+VCORE
GNDA_VCORE
8
1
1
1
330P_0402_50V7K~D
2
1000P_0402_50V7K~D
2
PR138
1
0_0402_5%~D
@ PC128
2
1
PR133
33K_0402_1%~D
2
1
1
@ PC124
PC127
0.47U_0402_10V7KD
1
2
2
+VCC_CORE
22.1K_0402_1%~D
VO
@
1
PR127
71.5K_0402_1%~D
82.5K_0402_1%~D
2
1
@ PR129
G
2
@
@
1
14.3K_0603_1%~D
@ PC121
@ PR126
680P_0402_50V7K~D 2
1
1.69K_0402_1%~D
2
PR139
@
2
1
PC130
0.1U_0402_16V7K~D
2
2
1
3
PR125
17.8K_0402_1%~D
2
1
2
1
PR124
1
MAX8791_QFN8~D
4
C
2
TP
MAX8786GTL+_TQFN40_6X6~D
C SN2
@ PR123
2
1
332_0402_1%~D
PHASE2
LGATE2
VSUM
17
PWR
PR120
2
1
0_0402_5%~D
VSSSENSE
4
LGATE
GNDA_VCORE
PR130
15K_0402_1%~D
TRC
14
GNDA_VCORE
<8>
GND
E
@ PR117
11.5K_0402_1%~D
2
1
7
ILIMPK
41
MAX8786_VCC PR116
154K_0402_1%~D
2
1
PR119
2.43K_0402_1%~D
2
1
8
21
1
R EF
REF
CSP3
PH3
PC117 1000P_0402_50V7K~D
2
1
TIME
9
25
2
PR118
2
1
6.34K_0402_1%
10
PWM3
6.8KB_0603_5%_ERTJ1VR682J~D
C
DRSKP
PC120
0.033U_0402_16V7K~D
1
2
TIME
VO
2
13
VPS
PC112 1000P_0402_50V7K~D
2
1
3
UGATE2
1
CN DS
F
PL14
0.45UH_ETQP4LR45XFC_25A_20%~D
1
FBS
1
7
DRSKP
24
@ PC123
0.01U_0402_16V7K~D
2
PH2
10KB_0603_1%_ERTJ1VG103FA~D
8
PWM PHASE
S
SHDN
12
<33> IMVP_VR_ON
FCCM UGATE
2
PSI
35
PR92
0_0402_5%~D
@
VSUM
1
CLKEN
PC98
1UU_0603_25V5K~D
2
1
2
38
6
@ PC114
2
PGD_IN
CLK_ENABLE#
@
SH DN
10_0402_1%~D
FBS
1
PR88
0_0402_5%~D
1000P_0603_50V7K~D
PR90
430_0402_1%~D
1
2
4.7_1206_5%~D
PR91
7.68K_0805_1%~D
FDMS8670AS_ POWER56-8
2
CSN1
PR114
2
VCCSENSE
DPRSLPVR
CSP2
16
@ PR115 0_0402_5%~D
2
<8> 1
DPRSTP
36
CSP2
22
PR122
4.53K_0402_1%~D
2
1
PC122
0.33U_0603_10V7K
GNDA_VCORE
<33,34,37> RUNPWROK
T55
37
PWM2
26
BOOT
D
VCC
S
5
PWM2
P GD_IN
+VCC_CORE
PC99
PR266
@ PR268
4.7_1206_5%~D
PR98
PC108
2.2_0603_5%~D 0.22U_0603_10V7K~D
1BOOT2
2
1BOOT2_2
1
2
1
PU8
SI4686DY-T1-E3~D
CSP1
PQ19
23
PQ22
CSP1
PWM1
CSN2
PR113
PAD~D
0_0402_5%~D
2
1
1
@ PC111
1U_0603_10V6K~D
D0
D1
D2
D3
D4
D5
D6
1
@ PR110
2
1
10K_0402_5%~D
<18> PWR_MON
28
29
30
31
32
33
34
PSI
2
1
0_0402_5%~D
H_PSI#
2
D
PR108
DPRSLPRV
2
1
40
27
3
CCV
PWM1
D
6
1
THRM
PC106
1U_0603_10V6K~D
OSC
5
2
3
15
<10,24> DPRSLPVR
<8>
D0
D1
D2
D3
D4
D5
D6
PR107
2
1
499_0402_1%~D
S
1
2
VRHOT
CSN3
<8,10,23> H_DPRSTP#
G
1
3
1500P_0603_25V7K~D
IMVPOK
4
39
18
N.C.
VCC
2
IMVP6_PROCHOT#
@
O SC
2 PR99
1
0_0402_5%~D
2 PR100 1
0_0402_5%~D 2 PR101 1
0_0402_5%~D
2 PR102 1
0_0402_5%~D 2 PR103 1
0_0402_5%~D
2 PR104 1
0_0402_5%~D 2 PR105 1
0_0402_5%~D
VID0
VID1
VID2
VID3
VID4
VID5
VID6
G
2
4
G
+CPU_PWR_SRC
GNDA_VCORE
<8>
<8>
<8>
<8>
<8>
<8>
<8>
LGATE1
S
4
LGATE
1
7
GND
MAX8791_QFN8~D
PQ21
PWM PHASE
PL13
0.45UH_ETQP4LR45XFC_25A_20%~D
PHASE1
3
2
4.7_1206_5%~D
UGATE1
8
3
2
PR87
PC96
2.2_0603_5%~D 0.22U_0603_10V7K~D
1BOOT1
2
1BOOT1_1
1
2
D
1
FCCM UGATE
H
PAD-OPEN 4x4m
+5V_ALW
V3P3
PU7
PC107
@ PH1
THRM
2
1
1000P_0402_50V7K~D
CCV
470KB_0402_5%_NCP15WM474J03RB~D
1
2
E
MAX8786_VCC
19
PR97
0_0402_5%~D
PAD~D
T92
6
BOOT
+
+PWR_SRC
2
Iccmax=TDB
I_TDC=TDB
OCP=TDBA, Intel spec=TDBA
IMVP_PWRGD <24,33,37,47>
20
2
GNDA_VCORE
@ PC101
2200P_0402_50V7K~D
2
1
VCC
@ PJP32
1
1
1500P_0603_25V7K~D
PR93
10K_0603_1%~D
GND
@
PR96
0_0402_5%~D
2
1
5
2
1
PR94
143K_0402_1%~D
2
1
+3.3V_RUN
GNDA_VCORE
PR95
0_0603_5%~D
1
PC100
PR89
1U_0603_10V6K~D 10_0603_5%~D
2
1
1
2
F
PR128
2
@
+5V_ALW
2
@ PR269
PU6
33K_0402_1%~D
1
0.01U_0402_25V7K~D
PC97
2
1
G
+
1
2
3
4
PC95
1U_0603_10V6K~D
2
1
2
+5V_ALW
@PR86
10_0603_5%~D
@ PC113
1
S
S
S
G
PQ17
+CPU_PWR_SRC
8
7
6
5
SI4686DY-T1-E3~D
H
PL12
1
2
PC92
2200P_0402_50V7K~D
2
1
PC91
0.1U_0603_25V7K~D
2
1
+CPU_PWR_SRC
2
8
6
5
4
3
Size
Document Number
Date:
Rev
0.2
LA-4151P
2
45
Sheet
1
of
57
5
4
NTR4502PT1G_SOT23-3~D
3
PR341
100K_0402_1%~D
2
1
PC137
0.1U_0603_25V7K~D
2
1
PC136
47P_0402_50V7K~D
2
1
PBATT+
4
PQ32
FDMC8854_POWERPAK 1212-8
MAX8731AETI+_TQFN28~D
PJP34
1
PR289
2.2_1206_5%~D
@ PC139
0.1U_0603_25V7K~D
1
2
@ PC166
0.22U_0402_6.3V6K
1
2
2
GNDA_CHG
PAD-OPEN1x1m
+3.3V_ALW
S
GNDA_CHG
GNDA_CHG
GNDA_CHG
8
P
@
IN+
7
O
IN-
G
PC186
100P_0402_50V8J~D
2
1
6
PR354
100K_0402_1%~D
2
1
+5V_ALW
4
PR345
232K_0402_1%~D
2
1
PR346
47K_0402_1%~D
2
1
PR350
27.4K_0402_1%~D
2
1
2
GNDA_CHG
PR344
1M_0402_1%~D
1
2
5
PC185
100P_0402_50V8J~D
2
1
1
PQ33
RHU002N06_SOT323
1K_0402_5%~D
1
3
S
2
G
PR170
@ PC173
0.01U_0402_25V7K~D
2
1
GNDA_CHG GNDA_CHG
GNDA_CHG
D
@
GNDA_CHG
+3.3V_ALW
MAX8731_REF
+DC_IN
ADAPT_OC <33>
@
PC167
10P_0402_50V8J~D
2
1
P
+5V_ALW
MAX8731_REF
PR349
21.5K_0402_1%~D
2
1
@ PR168
100K_0402_1%~D
2
1
IN+
G
IN-
3
GNDA_CHG
PU11A
LM393DR_SO8~D
O 1
8
@ PC171
100P_0402_50V8J
2
1
2
@ PC172
100P_0402_50V8J
2
1
A
@ PC170
100P_0402_50V8J
2
1
@ PC168
0.01U_0402_25V7K~D
2
1
<33> ADAPT_TRIP_SET
@ PR172
@ PR171
348_0402_1%~D 17.8K_0402_1%
2
1
2
1
@ PC169
0.01U_0402_25V7K~D
2
1
PR169
33.2K_0402_1%~D
1
2
@ PR165
100K_0402_5%~D
2
1
@
4
@ PR166
51.1K_0402_1%~D
2
1
@
1
2
0_0402_5%~D
@
MAX8731_IINP
ACAV_IN
Maximum charging current is 4.7A
GNDA_CHG
PR164
1M_0402_1%~D
1
2
PU11B
LM393DR_SO8~D
PR355
TBD_0402_1%~D
2
1
+5V_ALW
PR347
100K_0402_1%~D
2
1
GNDA_CHG
<18> MAX8731_IINP
B
D
2
G
MAX8731_REF
PR167
PR264
2
100_0402_5%~D
3
2
1
1.8K_1206_5%~D
GND
2
1
16
GND
29
PC190
1000P_0603_50V7K~D
3
FBSB
12
1 PR161
PQ36
RHU002N06_SOT323
FBSA
15 VFB
PC162
10U_1206_25V6M~D
2
1
CSIN
DAC
+VCHGR_B
@
PC161
10U_1206_25V6M~D
2
1
19
18
17
PC152
10U_1206_25V6M~D
2
1
PGND
CSIP
PC160
10U_1206_25V6M~D
2
1
REF
+VCHGR
PR160
PL16
0.01_1206_1%~D
5.6UH +-25%_ MPLCH1040L5R6_7.6A
2
1+VCHGR_L
1
4
3
2
1
PC158
1U_0603_10V6K~D
2
1
PC163
0.1U_0402_10V7K~D
2
1
7
PC154
220P_0402_50V7K~D
CHG_LGATE
PC151
10U_1206_25V6M~D
2
1
20
PC159
0.1U_0603_25V7K~D
2
1
DLO
PC150
0.1U_0603_25V7K~D
2
1
CCS
PC149
2200P_0402_50V7K~D
2
1
3
23
4
1
MAX8731_REF
@ PR263
1
2
0_0402_5%~D
4
CHG_UGATE
2 2
CCI
4
PC148
1U_0603_10V6K~D
1
2
2 PR158 1
0_0603_1%~D
LX
C
PQ31
PR163
0_0402_1%~D
1
24
PQ30
2
21 MAX8731A_LDO
PR153
33_0603_1%~D
5
LDO
PR155
4.7_0603_5%~D
BOOT_D
2
3
2
1
BOOT
25
1
2
PC157
PC242
0.01U_0402_25V7K~D130P_0402_10V7K~D
2
1
1
2
1
1
2
@ PC243
@ PR262
2000P_0402_10V7K~D 7.5K_0402_5%~D
@ PC241
130P_0402_10V7K~D@
1
2
PC156
0.01U_0402_25V7K~D
2
1
PR159
10K_0402_5%~D
2
1
B
PC164
0.1U_0402_10V7K~D
2
1
PR162
8.45K_0402_1%~D
2
1
<6,21,34> CKG_SMBDAT
PC165
0.01U_0402_25V7K~D
2
1
<6,21,34> CKG_SMBCLK
2
GNDA_CHG
1
CCV
5
<48>
5
6
SW_GND
2
BST
2
GNDA_CHG
1
2
@ PR176
200K_0402_5%~D
1
26
DHI
IINP
PR342
100K_0402_1%~D
2
1
1
PR149
0_0402_1%~D
27
CSSN
VCC
BATSEL
8
PR343
100K_0402_1%~D
1
2
PC144
1U_0603_10V6K~D
1
2
5
SDA
DOCK_DCIN_IS- <31>
3
2
1
SCL
9
6
PC155
3300PF_0402_50V7K~D
2
1
10
5
1
VDD
PQ25
1
3
PQ26
NTR4502PT1G_SOT23-3~D
1
2
MAX8731_IINP
1
2
ACOK
11
14
GNDA_CHG
PC153
0.1U_0402_10V7K~D
1
ACIN
D
DOCK_DCIN_IS+ <31>
PD17
RB751V_SOD323~D
2
1
+5V_ALW
2
13
@
PQ63A
NTGD4161PT1G_TSOP6~D
PC147
0.1U_0603_25V7K~D
2
1
0.01U_0402_25V7K~D
GNDA_CHG
DCIN
4
VCC
1
<18,34> ACAV_IN
1
PU10
DCIN 22
PR156
1
2
0_0402_5%~D
PR157
15.8K_0402_1%~D
2
1
PC146
2
GNDA_CHG
@ PC143
0.22U_0402_6.3V6K
1
2
28
1
2
PC142
0.047U_0603_25V7K~D
1
PR150
33K_0402_5%~D
2
PR173
0_0402_5%~D
1
2
PR152
10K_0402_1%~D
2
1
2
C
1
PR177
10K_0402_5%~D
PC145
1U_0805_25V4Z~D
2
1
1
@
2
@2
@ PC138
0.1U_0603_25V7K~D
1
2
PQ63B
D
MAX8731_REF
3
3
2
PAD-OPEN 4x4m
G
MAX8731A_LDO
2
3
1
3
4
PQ67A
2
2
1
2
2
CHAGER_SRC
1
S
4
5
3
D
<48> ACAV_DOCK_SRC
+SDC_IN
365K_0402_1%
PR145
PR154
49.9K_0402_1%~D
2
1
1
PJP33
G
PQ68B
2N7002DW-T/R7_SOT363-6~D
PR52
200K_0402_1%~D
2
1
4
2
+PWR_SRC
S
PQ67B
2N7002DW-T/R7_SOT363-6~D
3
1
1
1
3
NB_AC_OFF#2
+DC_IN_SS
2
PD52
BAT54CW_SOT323~D
1
2
@
GND
2
0_0402_5%~D
PC135
0.1U_0603_25V7K~D
1
@ PR184
6
+DOCK_PWR_BAR
PQ68A
2N7002DW-T/R7_SOT363-6~D
5
PR143
10K_0402_5%~D
PR175
24K_0402_1%~D
2
1
PR140
0.01_1206_1%~D
2N7002DW-T/R7_SOT363-6~D
+DC_IN
1
4
PR174
10K_0402_5%~D
2
1
NB_AC_OFF <33,41,48>
D
PR146
PR141
10K_0402_5%~D 33K_0402_5%~D
6 2
1
2
1
+SDC_IN
CSSP
PQ34
SI4835BDY-T1-E3_SO8~D
8
1
7
2
6
3
5
+DC_IN_SS
2
PD30
B540C~D
1
1
2
3
@
PR348
1
2
0_0402_5%~D
ACAV_IN_NB
<33,34>
PD35
NB_AC_OFF#2
1
GNDA_CHG
GNDA_CHG
A
RB751S40T1_SOD523-2~D
GNDA_CHG GNDA_CHG GNDA_CHG
GNDA_CHG
New Create Part Number
GNDA_CHG GNDA_CHG
Title
5
4
3
2
Charger
Size
Document Number
Date:
Rev
0.2
LA-4151P
Sheet
1
46
of
57
5
4
D
3
<10>
GFX_VID4
<10>
GFX_VID3
<10>
GFX_VID2
<10>
GFX_VID1
<10>
GFX_VID0
2
1
PR216
0_0402_5%~D
2
PR217
0_0402_5%~D
1
2
PR218
0_0402_5%~D
1
2
PR219
0_0402_5%~D
1
2
PR220
0_0402_5%~D
1
2
1
1
<10> GFX_VR_ON
D
2
PR221
0_0402_5%~D
+5V_ALW
+3.3V_RUN
PJP38
1
+VGFX_SRC
1
1
2
PC61
0.1U_0805_50V7K
2
1
PC62
2200P_0402_50V7K~D
2
1
1
1
3
2
1
PC216
2
1
2
76.8K_0402_1%
2
1
2
169K_0402_1%~D
1
1
PR238
69.8K_0603_1%~D
PR239
2
2
2
1200P_0402_50V7K~D
PR241
0_0402_5%~D
1
2
PJP39
2
PR242
340K_0402_1%
2
1
1
PC177
10U_0805_6.3V6M~D
2
1
PC212
PC176
10U_0805_6.3V6M~D
2
1
@
PR243
1K_0402_1%~D
2
1
B
Component select
Input CAP 10uF_1206_25V*2
Output Cap 330U_D2E_2VM_R7*2
H_MOSFET FDMC8878
L_MOSFET FDMC8854(5.6/[email protected], 13A)
Inductor 0.42U_MPCG0740LR42_20A(NEC_TOKIN)
PC219
1
2200P_0402_50V7K~D
@
VOUT=Vgfx_NB(1.25V)
L=0.42uF
Load line:6.9 mohm
Fsw=436K
D=0.0658
Output Ripple Current=5.88A
Output Ripple Voltage=5.88A*3.5mOhm=20.58mV
1
1
2
PR237
@ PC218
+
2
220K_0402_5%_ERTJ0EV224J~D
GNDA_VGAGNDA_VGA
PR240
0_0402_5%~D
+
2
PC214
1
0.1U_0402_16V7K
2
1
PH4
GNDA_VGA
1
PC213
330U_D2E_2.5VM_R7~D
PR265
2.2_1206_5%~D
4
ADP3209JCPZ-RL_LFCSP32_5X5~D
GNDA_VGA
<14> VCC_AXG_SENSE
330U_D2E_2.5VM_R7~D
1
2
1000P_0603_50V7K~D
PC211
1U_0603_10V6K~D
VGFX_CORE_FB
B
2
2
AGND
33
FDMC8854_POWERPAK 1212-8 PC140
1
1000P_0402_50V7K~D
RT
RPM
20
17
VRPM 14
1
2
200K_0402_1%~D
RPM 15
PR234
RT16
2
1
357K_0603_0.5%
RAMP 13
C SFB 12
PR233
CS REF 11
10
9
LLINE
2
PQ51
1
2
VRPM
PGND
CLIM
RAMP
PMONFS
8
CSFB
19 DR VL
18 PG ND
CSREF
DRVL
CSCOMP
PVCC
PMON
7
LLINE
ST
6
GND
PL19
0.42UH_MPCG0740LR42 _20A_20%~D
1
2
5
PR236
0_0402_5%~D
@
C
+VGFX_COREP
21 S W
PMON
VGFX_NB
Peak current: 8.7A
OCP min: 10A
4
DR VH
22
PMONFS
+PWR_SRC
3
2
1
2
26 V DD3
27 V DD2
28 V DD1
25 V DD4
VID4
VID3
VID2
SW
1
1
2
PR235
3K_0402_1%
PC217
2.2U_0603_6.3VAK~D
29 V DD0
DRVH
GNDA_VGA
GNDA_VGA
VID1
BST
CSCOMP
PR232 200K_0402_1%~D
2
1
VCC
PD25
PR225
RB751V-40_SOD323~D
24
0_0603_5%~D
BST2
1 BST_D
1
2
23
5
SS
VID0
32
COMP
4
1
1
GNDA_VGA
<18> PWR_MON_GFX
3
GNDA_VGA
ST
78.7K_0402_1%~D
PR231
1
+VGFX_COREP
PR364
0_0402_5%~D
1
2
PC215
1000P_0402_50V7K~D
2
1
@ PR229
100_0402_1%~D
FB
SS
CLIM
PR230
187K_0402_1%
1
2
1
PC208
470P_0402_50V7K
PC210
680P_0402_50V7K~D
1
2
2
1K_0402_1%~D
PR228
20K_0402_1%~D
2 1
2
PC209
0.012U_0402_16V7K~D
2
1
2
2
PR227
FBRTN
2
COMP
1
1
PC207
22P_0402_50V8J
@ PC206
22P_0402_50V8J
2
1
VSS_AXG_SENSE
2
PR224
33.2K_0402_1%
PR226
100_0402_5%~D
1
PC204
1U_0603_10V4Z~D
PC205
4.7U_0805_10V4Z
FB
1
2
2
PWRGD
C
VARFREQ#
PU15
31
GNDA_VGA
EN
<14> VSS_AXG_SENSE
30 EN
1
5
PC203
10U_1206_25V6M~D
2
1
PC202
10U_1206_25V6M~D
2
1
PQ50
1
<24,33,37,45> IMVP_PWRGD
PR223
10_0603_5%~D
2
PR362
0_0402_5%~D
1
2
2
PAD-OPEN 4x4m
2
PR222
10K_0603_5%
VGFX_CORE_FB
+VGFX_SRC
PAD-OPEN1x1m
GNDA_VGA
PJP40
1
PC220
1000P_0402_50V7K~D
2
2
1
GNDA_VGA
PC221
100P_0402_50V8J
+VGFX_COREP
1
2
+VCC_GFXCORE
PAD-OPEN 4x4m
GNDA_VGA
A
A
Title
ADP3209 Power Up both Intel GMCH and ATI M54
Size
Document Number
Date:
Rev
0.2
LA-4151P
Sheet
47
of
57
5
4
3
2
2
1
PD27
B540C~D
1
1
PR144
22K_0402_5%~D
2
1
1
2
4
1
3
1
2
3
PC175
0.1U_0603_25V7K~D
2
1
PC174
2200P_0402_50V7K~D
2
1
4
1
6
PD20
2
B
1
RB751V-40_SOD323~D
PR328
47K_0402_5%~D
1
1
5
1
4
PR186
47K_0402_5%~D
1
2
1
2
PQ56A
2N7002DW-T/R7_SOT363-6~D
2
PQ70
D
PQ61
RHU002N06_SOT323
3
RHU002N06_SOT323
1
2
1
PR327
47K_0402_5%~D
5
+DOCK_PWR_BAR
2
PR363
1K_1206_5%
3
2
PQ59A
2
G
D
2
G
S
3
S
<33> PBATT_OFF
2
2
2
EN_DOCK_PWR_BAR#
1
PR358
0_0402_5%~D
ACAV_DOCK_SRC
1
@ PR359
0_0402_5%~D
PD34
RB751S40T1_SOD523-2~D
A
1
A
+PWR_SRC
RB715F_SOT323~D
PQ56B
2N7002DW-T/R7_SOT363-6~D
1
2
3
SLICE_BAT_PRES
6 1
1
1
2
PD36
RB751S40T1_SOD523-2~D
PR329
100K_0402_5%~D
24
5
PC192
1U_0603_25V6-K~D
1
+3.3V_ALW2
PQ55B
2N7002DW-T/R7_SOT363-6~D
3
+DC_IN_SS
4
3
2
1
PC193
1U_0805_25V4Z~D
1
2
3
PD51
+NBDOCK_DC_IN_SS
PR326
240K_0402_5%~D
1
2
1
4
4
2
PR325
240K_0402_5%~D
1
2
6 1
4
PR293
620K_0402_5%~D
2
PR291
390K_0402_5%~D
2
1
PR292
390K_0402_5%~D
2
1
RB751V-40_SOD323~D
1
1
2
PR351
240K_0402_5%~D
4
1
6 2
2
1
33_0402_5%~D
2N7002DW-T/R7_SOT363-6~D
4
PQ59B
PD19
+DC_IN_SS
2N7002DW-T/R7_SOT363-6~D
PQ55A
2
PQ42
FDS6679AZ_SO8~D
8
7
6
5
PBATT_IN_SS
PR294
2
2
D
PQ62B
8
7
6
5
3
1
G
<33> PBATT_OFF
1
PR360
0_0402_5%~D
2
1SLICE_BAT_PRES
S
PR352
47K_0402_1%~D
1
2
1
2
3
PD31
PDS5100H-13_POWERDI5-3~D
1
2
D
PR353
100K_0402_5%~D
C
@ PR361
330K_0402_5%~D
G
3
2
PQ66B
2N7002DW-T/R7_SOT363-6~D
PQ69A
2N7002DW-T/R7_SOT363-6~D
5
PQ41
FDS6679AZ_SO8~D
2
<33> PBATT_OFF 5
1
2
1
1
3
3
PQ69B
2N7002DW-T/R7_SOT363-6~D
PBATT+
PQ62A
2N7002DW-T/R7_SOT363-6~D
EN_DOCK_PWR_BAR <33>
NB_AC_OFF_BJT <41>
2
S
B
2
G
S
PR181
22K_0402_5%~D
<46>
6
1
1
SW_GND
4
SI4835BDY_SO8~D
PQ45
+3.3V_ALW
PQ28
RHU002N06_SOT323
D
PR151
22K_0402_5%~D
5
5
+VCHGR
IMD2AT-108_SC74-6~D
1
ACAV_DOCK_SRC <46>
PQ64B
2N7002DW-T/R7_SOT363-6~D
1
2
3
D
+5V_ALW
3
1
2
PR183
100K_0402_5%~D
C
8
7
6
5
PR148
47K_0402_1%~D
1
6 2
2
PR180
100K_0402_5%~D
1
2
1
PR178
100K_0402_5%~D
PR147
100K_0402_5%~D
1
2
5
PQ24A
PQ65
RHU002N06_SOT323
PR179
22K_0402_5%~D
+3.3V_ALW2
<31> ACAV_DOCK_SRC#
S
2
G
2
6
PQ64A
D
2
EN_DOCK_PWR_BAR#
<33,41,46>
2
2N7002DW-T/R7_SOT363-6~D
2
NB_AC_OFF
PQ66A
2N7002DW-T/R7_SOT363-6~D
PR182
100K_0402_5%~D
1
2
+3.3V_ALW2
PR357
330K_0402_5%~D
PQ24B
IMD2AT-108_SC74-6~D
6
+3.3V_ALW
D
PR142
240K_0402_5%~D
3
+3.3V_ALW
1
2
3
4
8
7
6
5
+DOCK_PWR_BAR
PC141
0.47U_0805_25V7K~D
2
1
FDS6679AZ_SO8~D
PQ23
<31,33> DOCK_AC_OFF
Title
5
4
3
2
Selector
Size
Document Number
Date:
Rev
0.2
LA-4151P
Sheet
1
48
of
57
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
1
7
CPU
12/14/2007
HW
Add R1059 H_RESET# pull up +1.05V_VCCP and Depop R1059 Depop R1059
X01
2
9
CPU
12/14/2007
HW
For Intel CPU power transient
Change C56,C57and C58 to 470UF
X01
3
10
MCH
12/14/2007
HW
For Intel request for DP function
Change R180,R181,R182 and R183 to 4.02K
X01
4
10,34
MCH
12/14/2007
HW
For design issue
Change U80 and U57 to 74AHC1G08GW
X01
5
13
MCH
12/14/2007
HW
For Intel request power seq
Depop D1 and R122
X01
6
13
MCH
12/14/2007
HW
For disable TV-OUT function
Modify U78.K30 to GND plane
X01
-Disconnect PWR_MON_GFX from U3.45
-Connect U3.45 to MAX8731_IINP with a 4.7k series resistor
-Identify the values of R1033 and R1061
-Add U93,C1158,R1063,and R1064
-Change R142 to 0ohm
7
18
EMC4002
12/14/2007
Dell
For Dell request
8
18
EMC4002
12/14/2007
Dell
For U3 POWER_SW# Input-Add AND Gate
9
21
12/14/2007
Intel
Follow Intel proposal for DP interoperability
Add U94,U95,Q163,Q164,C1159,R1073,R1074 and C1160
X01
10
31
Docking
12/14/2007
Compal
For Docking ESD concern
Add D73
X01
11
32
USH
12/14/2007
Broadcom
Follow Broadcom request to modify schematics for USH
12
33
SIO
12/14/2007
Dell
GPIO Map update
13
33
SIO
12/14/2007
Dell
The LCD/LED will keep had power with USB
device when unplug AC & Battery
14
33
SIO
12/14/2007
Dell
On Battery Mode U35 have +3.3V backdrive
15
33
SIO
12/14/2007
Dell
Add PD on SYS_LED_MASK#
Add R1069
X01
16
33
SIO
12/14/2007
Compal
Change BID to X01(001)
Pop R529 and depop R534
X01
17
33
SIO
12/14/2007
Dell
GPIO Map update
Add U96 and C1161
X01
18
34
EC
12/14/2007
Dell
GPIO Map update
-Del U59,C1012,R553,R558 and add R1071,Change R1050 from 1K to 33K
X01
-Change ACAV_IN_DOCK# to ACAC_DOCK_SRC# ACAV_IN_MB/DOCK to ACAV_IN
19
35
EC
12/14/2007
Dell
GPIO Map update
-For BKT add U38.15 to BKT_GPIO17 connect to D71.2
20
38
LED
12/14/2007
Compal
Backdrive from +3.3V_WLAN to +5V_RUN on S3 mode
21
38
LED
12/31/2007
Compal
Add Bypass Capacitor for TTL Gate
X01
X01
C
B
D
C
DP
-Add R1066,R1067,R1068 and del R495,R499 and change R771 to 1K
-Depop R1067,R490,C594,C591,R467 and pop R829,add R1072
-Changed pin 82 from USB_CHARGER_PWR_EN# to ESATA_USB_PWR_EN#
-Change pin 104 from ESATA_USB_PWR_EN# to USB_POWERSHARE_PWR_EN#
-Add 100k no pop pull-ups to +3.3V_ALW2 on:
USB_SIDE_EN#,ESATA_USB_PWR_EN#,USB_POWERSHARE_PWR_EN#
-No stuff R502, R504, R1013.
-Add diode on signal INSTANT_ON_SW# to 5028 pin 28
-Add D74 and R1070
X01
X01
X01
X01
X01
Add D75 between Q97 and Q98
X01
Add C1162~C1165
X01
-Change R476 to 5.1M ohms and R488 to 3.3M ohms to lower
-Pop D70, C641, C647,add R1077 and Depop R464,R1077
22
32
USH
23
31
Docking
12/31/2007
Dell
Roush + Docking AC protect issue(crowbar)
Add D77, R1075,R1076,and Depop R124.
X01
24
33
SIO
12/31/2007
Dell
For Power change Media Slice issue
Add D78, R1079 and Depop R1078.
X01
12/31/2007
Broadcom
B
X01
A
A
25
21,40
USB
01/03/2008
Compal
For power leakage for USB switch
Change U97,P/N from FSUSB31K8X_US8 to TS3USB31RSER_QFN8
5
4
3
2
Title
Changed-List History1
Size
Document Number
Date:
Rev
0.5
LA-4151P
Sheet
1
49
of
57
5
4
3
2
1
Item Page#
D
Title
Date
Request
Owner
Issue Description
-Change DIMMA P/N from TYCO_2013022-1 to FOX_AS0A620_U4SN-7F
-Change DIMMB P/N from TYCO_2013297-1 to FOX_AS0A620_U8SN-7F
16,17
DIMM
01/03/2008
ME
For ME team change foxconn to main source
27
34
SIO
01/03/2008
HW
Update Cell charger detect circuit
Add D79
X01
28
29
01/03/2008
HW
Modify JBIO3.5 from U19.A16 to U32.C3(FP_RESET#)
X01
29
24
01/03/2008
HW
For LOM Disable concern
Add R1065 and Depop R1065 and del R935
X01
Fingerprint
SB
X01
-Del U81 and U86.6 connect to GND
BKT function concern and bypass BKT function
-Add RN1~RN6 and depop
-Modify U36.41 to DOCK_POR_RST# connect to JDOCK1.140
GPIO update
-Add C1167,R1082
-Modify LVDS connector to SP02081020
ME team change LVDS connector and cost down action
-Modify LVDS1.4 from PNL_BKLT_CBL_DET# to +3.3V_RUN
BKT function
-Swap netname LCD_VCC_TEST_EN and BKT_GPIO2
Modify pin-name from JBIO1.109,111,113~123 to JBIO1.107,109,
HW concern
111~121 and change JBIO1.139 from +1.8V_LAN_M to +LOM_VCT
-Add D80 and R1083 to pull up +3V_ALW2
HW concern
-Add R1084 pull up to +3V_ALW and depop
30
40
BKT
01/03/2008
HW
For
31
34
SIO
01/04/2008
HW
For
32
19
LVDS
01/07/2008
33
21
BTB
01/08/2008
HW
For
34
21,33
BTB
01/08/2008
HW
For
35
35
ECE1088
01/08/2008
HW
For GPIO update
Modify U38.15 from BKT_GPIO17 to BKT_GPIO19
X01
36
21,33
BTB
01/08/2008
HW
For GPIO update
-Modify from WIRELESS_ON/OFF# to WIRELESS_ON#/OFF
-Del R489,R830 and netname SC_DET from U35.84
X01
37
21
DP
01/09/2008
HW
For Intel DP solution update
Add R1085,R1086,R1087,R1088
X01
Crystal
01/09/2008
HW
For EA test result for crystal
38
A
Rev.
26
HW/ME
For
for
C
B
23,27,32,34
X01
X01
X01
X01
C
X01
-Change Y3 to SJ100005X0L,C674 to 27PF
-Change C608,C296,C297 to 12PF,C609,C1032,C1058 to 15PF
X01
39
35
TouchPAD
01/09/2008
ME
For ME team change connector
Change JTP1 to SP070801070
X01
40
38
LED
01/09/2008
ME
For ME team change LED board to FPC
Change JBIO5 pin-define
X01
41
21,35
WLAN
01/10/2008
HW
For GPIO update for WLAN switch
Add BKT_GPIO12(U38.8) and BKT_GPIO13(U38.9) connect to JBIO1.75
and JBIO1.120
X01
42
07
ITP
01/10/2008
HW
For Intel ITP solution update
Change R62,R64,R65,R66,R67 from 51ohm to 56ohm and R977 depop
X01
43
32
01/11/2008
HW
Add R1089
X01
USH
44
10
MCH
01/14/2008
HW
UMA display TV solution implement
45
10
MCH
01/14/2008
HW
Follow Roush UMA implement (CRT/LVDS)
46
11
MCH
01/14/2008
HW
UMA display TV solution implement
47
23
ICH9M
01/14/2008
HW
Follow Roush UMA implement
48
21
DP/Card1 IO 01/14/2008
HW
Follow Roush UMA implement
49
24,35
ICH9M
01/14/2008
HW
50
19
LVDS
01/15/2008
HW
Remove TV_CVBS/TV_Y/TV_C signals with pull down resistors
(R674,R677 and R678). Connect pin J27,E27 and G27 to GND
Remove R1048,R1049(CRT_H/VSYNC)pull up. Change R688 from
2.37K_1% to 2.4K_1%; Change R672 from 1.02K_1% to 976_1%
Change pin N32 of U78(VCCD_TVDAC) from +1.5V_RUN to GND. Remove
C138 and C139
Remove R952, connect pin AC23 of U79 to pin2 of R237
Remove BIO_DET# net(Del. R823,R932; pin A16 of U79), depop R754
Add R1090(100K)pull up to +3.3V_ALW_ICH on PCIE_MCARD1_DET# net,
make R439 depop; change C1135 from .1uf to 1uf
CIS Symbol update
X01
X01
X01
X01
X01
X01
Add D81 between LVDS and MCH, ADD 1091 pullup.
Title
5
4
3
2
Size
Document Number
Date:
Rev
0.5
LA-4151P
Sheet
1
50
B
X01
Link JP3(Change to JP6) and JTP1
BIA_PWM signal seems to be floating in " BKT mode ".
D
of
57
A
5
4
3
2
1
Item Page#
D
C
B
Title
Date
Request
Owner
Issue Description
Rev.
51
6
CLKGEN
03/04/2008
HW
For component derating
L1 change to SM01002480L
X02
52
7
CPU
03/04/2008
HW
For ITP modify solution
R57 change to 124ohm, R64 change to 39ohm, R65 change to 150ohm,
R66 change to 649ohm, R67 change to 27ohm
X02
53
9
CPU
03/04/2008
HW
For CPU power loadline solution
C52 change to pop and C56,C57,C58 change to 270UF(SGA00003H0L)
X02
54
10
MCH
03/04/2008
HW
For DP modify solution
R180,R181,R182,R183 change to 2.2K ohm
X02
X02
03/04/2008
HW
Add Camera solution for PFG
Add Q165,Q166,R1094(unpop),R1095,R1096,R1097,R1098,C1168,C1169
C1170,C1171,U98(unpop),L70(unpop),JCAM and net CAM_MIC_CBL_DET#
LVDS,JBIO1
03/04/2008
HW
For BKT table updated
Modify D68.2 to BKT_GPIO18 for +LCDVDD power and
X02
21
Audio
03/04/2008
HW
For audio vendor solution
R327,R828 change to 499K ohm and R328 unpop
X02
58
27
R5C833
03/04/2008
HW
For R5C833 crystal solution by test result
Modify X2(SJ124P5M53L)-->Y2(SJ10000690L)
X02
59
29
03/04/2008
ME
For FP connector change
Modify JBIO3(Tyco_1734820-6)-->(TYCO_1734242-6)
X02
55
19
56
19
57
PFG
FP
60
32
BCM5880
03/04/2008
HW
For EMI solution by BCM5880
61
33
ECE5028
03/04/2008
HW
For ECE5028 and board ID updated
62
34
ECE5035
03/04/2008
HW
For ECE5035 updated
63
38
03/04/2008
HW
Add WLAN LED share to BKT LED
64
38
65
LED
X02
X02
Add Q167,Q168
X02
JBIO4 change from Tyco_1734242-4 to Tyco_1734242-6
add PWR_BTN_BD_DET# for PWR board
Modify +3.3V_RUN_BKT_PWR source to alway pop
Add net BKT_LED to control LED
ME
For PWR board connector change
39
BKT function 03/04/2008
HW
For BKT function updated
66
40
HW
Modify U86.9 to BKT_GPIO11(U38.14)
X02
67
24
SPI
03/04/2008
HW
For del recovery bios function
Del U13,R295,R303,R304,R305,R306,R308,R309,C329
X02
68
31
Dock
03/04/2008
HW
For Docking ESD concern
Modify D73 from SC10T24C010 and SC600000N0L
X02
69
36
Power
03/04/2008
HW
For power control concern
Reserve R1100,R1101 to bypass level shift
X02
70
29,35
HW
Add net BKT_GPIO17 and R1104(unpop),D82 for Biometic reset signal
X02
71
35
TP
03/06/2008
HW
For backdrive from Touch PAD
Modify R594,R595 pull-up to +5V_ALW
X02
72
32
USH
03/06/2008
HW
For smart card concern
Modify R849 to 1.5K and R973 to 300ohm
X02
X02
X02
38
74
19,22
C
X02
03/04/2008
73
PWR board
Add L71,L72,C1172,C1173
R841 change to 3K and R473 change to 1K,R849 pop
Del R1084, add PWR_BTN_BD_DET#
R529(unpop),R534(pop),R530(pop),R535(unpop) for X02
Modify R560 to pop,R877 change to 200K and
R565,R567 change to 2.2K ohm
D
X02
X02
LED
03/07/2008
HW
For keyboard LED modify
-Modify JBIO5 to TYCO_1-1734242-2 and add net MASK_BASE_LEDS#
-Q120.3,Q121.3,Q122.3 modify to +5V_ALW
Camera
03/10/2008
HW
For Camera function
Modify net name from CAM_MIC_CBL_DET# to CAM_CBL_DET#
A
B
A
Title
5
4
3
2
Size
Document Number
Date:
Rev
0.5
LA-4151P
Sheet
1
51
of
57
5
4
3
2
1
Item Page#
D
Title
Date
Request
Owner
Issue Description
Rev.
75
31
Docking
04/07/2008
HW
Slice battery issue
change R1076 from 1K to 910K
X03
76
33
EC5028
04/07/2008
HW
Support wireless on#/off switch on BLT mode
change R874 to depop
X03
R659, R663, R125, R661, R556, R596, R655, R1037, R1042, R1045
change from 150 ohm to 1K ohm
X03
77
38
LED
04/07/2008
HW
Blue LED brightness concern
78
33
EC5028
04/07/2008
HW
Roush MB side have backdrive when plug some USB device
R504 change to 10K and made pop.R502 and R1013 change to pop
which have extra-power source
X03
79
18
EMC4002
04/07/2008
HW
Vendor recommend value
R1033 change to 200K
X03
80
34
EC5035
04/07/2008
HW
Remove reserved SPI ROM at EC side.
Remove U37,C672,R589,R590,R591,R592,R593 and R558
X03
81
24
SPI ROM
04/07/2008
HW
Reserved 2nd SPI ROM for code size over 4M byte.
Add U13,C329,R295,R304,R305,R306,R308,,R307 and R309
X03
82
32
USH
04/07/2008
HW
Vendor recommend schematics for EMI
D
D28 and D29 change connect to RFREADER_TXN1_P1 and RFREADER_TXP1_P1
R494 and C639 change connect to RFREADER_TXN1
X03
R498 and C643 change connect to RFREADER_TXP1
C
C
Add U99~U101(SN74CBTD3306) and C1174~C1175(0.1UF)
R1053 change from 100K ohm to 1M ohm
Del Q19,Q20,Q163,Q164,R958,R960,R964,R966,R1073,R1074
83
21
DP
04/07/2008
HW
Vendor recommend schematics for DP switch
84
12
TV
04/07/2008
HW
Vendor recommend schematics for TV disable
85
24,33
EC5028,
SPI ROM
04/07/2008
HW
GPIO table update
Add net name SPI_WP#_SEL and R1108~R1109(0 ohm)
86
35
TouchPAD
04/07/2008
ME
ME concern need to shorten TouchPAD FFC length
Swap JTP1 Pin1~Pin16 net name
X03
87
06
04/07/2008
HW
Isolate CLK_PCI_DOCK signal that has risk for docking
scenarios.
change CLK_PCI_PCM to U1.33
X03
88
40
BlackTop
04/07/2008
HW
USB interface change for BKT to ICH
89
19
Camera
04/07/2008
HW
Camera pinout modify for vendor
90
38
LED
04/09/2008
HW
Add WWAN LED control on BLT mode
Modify R206.1 to +3.3V_RUN_BKT_PWR and Q115.3 to +5V_TP_PWR
X03
Add R1110
X03
Clock
X03
X03
Add R1105~R1107 to 75 ohm
X03
Del U83 and C1144,Modify U97.5 to USB1-,U97.3 to USB1+ and U85.6
from BKT_GPIO3 to GND and change U97.1to BKT_GPIO3
USBP11_D- change to JCAM.2,USBP11_D+ change to JCAM.3
CAM_CBL_DET# change to JCAM.5
B
X03
B
X03
91
27
R5C833
04/09/2008
HW
Add SC CLK impedance control between chip(20~30 ohm)
and connector
92
29
PWR SW
04/09/2008
HW
Remove PWR SW for debug
Remove PWRSW1,PWRSW2 and C684
X03
93
21
I/O
04/10/2008
HW
Vendor I/O connector update
Remove JBIO1.141~144
X03
94
06
Clock
04/14/2008
HW
Modify R27 to 33ohm
X03
95
29,32
Hall sensor
04/16/2008
ME
Modify JSC1 to 10pin and JSPK1 to 9pin connector
X03
96
24,27
RF issue
04/21/2008
HW
Add 14M/33M/48MHz terminator for RF issue
POP R279,C312,R285,C318,R803 and C1057
X03
97
10
04/21/2008
HW
Fixed S3 resume
Vendor recommend schematics modify to damping resistor
for share CLK signals
Modify Hall sensor from smart card connector to
SPK connector
A
A
S3
X03
Modify U80 power to +3.3V_ALW_ICH
Title
5
4
3
2
Size
Document Number
Date:
Rev
0.5
LA-4151P
Sheet
1
52
of
57
5
4
3
2
1
Item Page#
D
C
Date
Request
Owner
Issue Description
Rev.
98
9
CPU
04/21/2008
HW
Reserve 24 pcs high frequence for ULV CPU
Add C1176~C1199
X03
99
18
Thermal
04/22/2008
HW
Modidy thermal protect on 95 degree
change R151 to 1.5K
X03
100
21
DP
04/23/2008
HW
Update new DP swith schematics
Depop R1085~R1088
X03
101
36
backdrive
04/24/2008
HW
Fix +3.3V_RUN backdrive from North bridge
Modify R625 to 33ohm 0603 and pop Q79
X03
102
39
BLT
04/25/2008
HW
Update BLT GPIO table
Add BKT_GPIO5 connect to JBKT1.63
X03
103
10,36
Audio
05/22/2008
HW
Fix WLAN card intermittent can't detect
Add U103,C1200,C1201 and del U92,C1156,C1157,R1060 ,U79.V10
change to +1.5V_ALW_HDA R153 change to 3.16K R154 change to
5.1K, del R314,R315 and U79.AD7 change to +1.5V_RUN
104
38
LED
05/22/2008
HW
Fix +5V_RUN backdrive on BLT mode
Add D83
X04
105
33
06/10/2008
HW
Fix slice battery concern on power
Change R503 from 100K to 4.7K
X05
106
27
1394
06/10/2008
HW
Fix 1394 reset timing
Modify R801 to 47K
X05
107
24
ICH
06/10/2008
HW
Update GPIO table for TPM and TCM
Add R1111
X05
108
36
backdrive
06/10/2008
HW
Fix +3.3V_RUN backdrive from North bridge
Modify R625 to 39ohm 0402
X05
Slice Battery
30,38
connector
06/11/2008
ME
Fix ME concern for factory build
Modify JBT and JBIO5 to SP070805091(TYCO_1-2041070-2)
X05
110
29,38
connector
06/11/2008
ME
Modify JBIO3,JCAM,JCS1 and JBIO4 to SP070805092(TYCO_2041070-6)
X05
connector
06/11/2008
ME
Modify JEXP1 to SP070805271(TYCO_2-2041070-6)
X05
28
Modify JEXP1 to SP070805270(TYCO_1-2041070-6)
JSATA1 to SP01000SE0L(TYCO 2-1759838-5)
Modify L71,L72 change to SHI00005Y0L
and C639,C643 change to +-10%
112
35
connector
06/11/2008
ME
113
32
USH
06/13/2008
HW
Modify USH component tolerance
114
12
NB
06/13/2008
HW
Update NB reference schematics
Add C1202
X05
115
29
SPK
06/16/2008
ME
Modify SPK connector pin define to improve cable
routing for ME concern
Re-define SPK connector pin-out
X05
116
6
CLKGEN
06/20/2008
HW
Fix setup ME power package5 issue when power on
Add R1112
X05
117
38
LED
06/20/2008
HW
Fix LED flash bright when unplug AC
Add R1113
X05
118
21
06/20/2008
HW
Follow Roush reduce USB charge schematics
Delete R995
X05
119
30
06/20/2008
HW
Fix BT cable for factory assemble
Modify BT_DET# from JBT.1 to JBT.12
X05
Update TCM reference schematics
Add R1115~R1119,C1202,C1203 and R383 change to 10K,R884 change to
1K and delete R381,R382
X05
120
USB Charge
BT
30
TCM
06/20/2008
HW
D
X04
109
111
B
Title
C
X05
X05
A
B
A
Title
5
4
3
2
Size
Document Number
Date:
Rev
0.5
LA-4151P
Sheet
1
53
of
57
5
4
3
2
1
Item Page#
D
1
41
2
Title
Battery slice
application
Charger
Date
Request
Owner
12/13
Dell
12/13
Dell
46/48
46
Charger
46
Charger
12/13
Dell
Issue Description
12/13
Dell
C
5
6
46/48
Charger
12/13
Dell
46
Charger
12/13
Dell
48
Selector
12/13
Dell
Selector
12/13
DC_IN
Rev.
for Slice battery to detect NB battery is
Add PQ47(FDN338P_NL), PD22(RB751V) and PR234 (0 ohm)
insert or not.
To block +PWR_SRC (19.5V) from
Add PQ63 A/B(NTGD4161PT1G),P341(100K),PR342(100K),
Docking connector DOCK_DCIN_S +/- pins when NB is not docked PR343(100K).
Add PQ46 RHU002N06 to control PQ62 on/off
Add
Add
Add
Add
Charger of ISL88731 will turn off
When ACIN is no power
3
4
X01
LM393 to replace ISL88731 ACOK function(PU11B)
PR345(232K),PR346(47K),PR349(21.5K),PR350(27.4K)
PR344(1M),PR347(100K), PR348(0)
PC185(0.1U),PC186(100P)
X01
This change to allow charging when AC adapter only in Dock. Remove PR188 and PR187,
Change PR145 from +DC_IN to +SDC_IN.
Note TI and Intersil version of charger will disable
change PR157 net name from ACAV_IN_NB to ACAV_IN.
charging when AC OK goes low.
Maxim charger function was fine.
The added comparator circuit is used to give BIOS
indication when AC adapter is inserted or removed from
notebook.
Replaces charger AC OK function.
Change all notebook signal
name's "ACAV_IN_DOCK" and "ACAV_IN_DOCK#" to
"ACAV_DOCK_SRC" and "ACAV_DOCK_SRC#" respectfully.
X01
C
Change PQ40_Pin1 from "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#"
Change PQ40_Pin2 from "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"
X01
Change PQ43_Pin2 from "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"
Change PQ36.2 connection
from ACAV_IN_NB to "ACAV_IN"
PBATT back drive to Battery Slice
vias charger high side MOSFET
Change PQ36.2 connection
from ACAV_IN_NB to "ACAV_IN"
Add PQ45 between PBATT+ and +VCHGR
Use PBATT_OFF control PQ62 to switch PQ45
Add PR351(240K), PR352(47K) and PR353(100K)
X01
Compal
PBATT_OFF connect to DOCK_AC_OFF
Add PD34 RB751V-40
X01
12/13
Dell
Add PC183 and non-stuff
Add PC183 and non-stuff
X01
7
8
48
9
41
10
42
+3.3V/+5V
12/13
Dell
EE work item
11
48
Selector
12/14
Compal
For save the placement space, use one dule MOS chip to
replace 2pcs MOS chip
12
46
Charger
12/14
13
42
+3.3V/+5V
12/14
Compal
14
45
CPU_VCORE
12/14
Compal
D
X01
X01
B
B
Compal
For save the placement space, use one dule MOS chip to
replace 2pcs MOS chip
ME highet limit issue
Connect MAX8786_VCC to PU7_Pin3 to disable third phase
Change PL6 and PL7 from HMP1350-3R3LD-R to SSC-1350F3-2R8
X01
Change PQ6 and PQ7 from FDMC8878 to FDMS8692
Add PQ64 A/B (2N7002DW-T/R7) to replace PQ29 and
PQ40 (RHU002N06)
X01
PQ46 (RHU002N06)
Add PQ66A/B (2N7002DW-T/R7) to replace PQ 38and
PQ39 (RHU002N06)
X01
PQ43 (RHU002N06)
PQ44 (RHU002N06)
Change PL16 from HMU1356-5R6 to MPLCH1040L5R6
X01
Connect MAX8786_VCC to PU7_Pin3
X01
A
A
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
54
of
57
5
4
3
2
1
Item Page#
D
1
Title
Date
Request
Owner
AJ
Compal
48
Selector
1/7
46
Charger
1/7
3
48
Selector
1/7
Merle
DELL
Merle
DELL
4
41
+DC_IN
1/7
Doug
DELL
PWR
Snubber
2
5
6
41
+DC_IN
1/9
1/9
C
7
8
Issue Description
Charger Isense MOSFET timing change
PJPDC1 change to 7pin connector
Guangyong
DELL
DELL request add a snubber circuit
on every regulator
Add below location of regulator switching node
+3.3V_ALW: PR290, PC191
+5V_ALW: PR288, PC189
+1.5V_RUN:PR287, PC188
+1.05V_M:PR286, PC187
+VCHGR:PR289, PC190
Battery
Team
DELL
Change Battery Pin from 9 to 7pin
Change Battery Pin from 9 to 7pin
Guangyong
DELL
Modify ADP3209 schematic
Follow ADI suggestion
45
CPU_CORE
1/10
Compal
The load line SPEC is 4 mohm for SFF SV CPU
BO
DELL
9
B
10
46
Charger
3/4
11
48
Selector
3/4
12
47
+VGFX_CORE
3/4
13
PWR
Snubber
3/5
Merle
DELL
AJ
Compal
Kenny
Compal
Compal
EMI
X01
X01
X01
X01
C
1/10
2/19
X01
Add PR357 330K_0402 form +DOCK_PWR_BAR to GND.
Add PQ70 RHU002N06 parallel PQ61, series PR358 0_0402
to EN_DOCK_PWR_BAR#,serial PR359 0_0402 to ACAV_DOCK_SRC
PJPDC1 change to MOLEX_87438-0743_7P-T
Change PR20 to 0_0402_5% and populate
Hot dock issue, adapter crowber
D
X01
PC142 change to 0.047u_0603_25V
ADP3209
NB_CORE
Charger
Rev.
Change PQ63 to 2N7002DW
Add PR360 0_0402_5% between PQ63 and SLICE_BAT_PRES
Charger for Battery Slice
47
46
Populate PR224
Change PR239 from220K_0603_1% to 49.9K_0603_1%
Change PR238 from 140K_0402_1% to 169K_0402_1%
Change PC219 from 2200p_0402_50V to 1200p_0402_50V
Change PR124 from 6.49K_0603_1% to 14.3K_0603_1%
Change PR118 from 4.99K_0402_1% to 6.34K_0402_1%
Change PR136 from 1.43K_0402_1% to 732_0402_1%
Change PR90 and PR109 fro, 2K_0402_1% to 430_0402_1%
Change P98 and PC109 from 0.22U_0603_10V to 1U_0603_25V
No stuff PC131, PC132 and PC133
1. Un-pop PR184, PR347.
Maxim Charger from powering on while in S5 and battery only 2.Add PD52 BAT54CW_SOT323,
+DOCK_PWR_BAR/+DC_IN_SS
Reserve PR184 0_0402_5% form +SDC_IN to PU10 PIN22
3. Add PR354 (10K), MAX8731A_REF/PR348_Pin1
ADD PR355 (41.2K) PR348_Pin1/GND
for reducing leakage current.
for VGFX-CORE test
In order to meet the derating requirement,
change the resister component size
X01
X02
B
Add PR363 1K_1206 and PC192 1U_0603_25V from
+NBDOCK_DC_IN_SS to ground.
Add PD35 RB751S40T1_SOD523-2 from NB_AC_OFF# to
ACAV_IN_NB.
Fix BITS CR196131 and CR196130
X01
X02
Change PD31 from SCSB540C08L(S SCH DIO B540C-13-F SMC) to
X02
SCS00002M0L(S SCH DIO PDS5100H-13 POWERDI5).
Add PR364 SD02800008L(S RES 1/16W 0 +-5% 0402 between
X02
VCC_AXG_SENSE and PR227.2
Add PR362:SD02800008L(S RES 1/16W 0 +-5% 0402) between
IMVP_PWRGD and pin31 of PU15.
Change component sixe from 0805 t0 1206 below location of
X02
regulator switching node
+3.3V_ALW: PR290
+5V_ALW: PR288,
+VCHGR:PR289,
Vcore: PR266,PR267,PR268 and PR269
A
A
5
4
3
2
Title
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
55
of
57
5
4
3
2
1
Item Page#
D
Title
1
48
Selector
2
46
Charger
3
41
45
Date
43
42,43,
45,46,
47
Issue Description
3/6
MERLE
DELL
Application for Battery Slice
3/6
Compal
Material smooth control
DC_IN
4/8
AJ
Compal
SPACE limitation
VCORE
4/8
James
Compal
4/8
Compal
4/8
EMI and
Key Part
DELL
4
5
Request
Owner
+1.5V/1.05V
EMC&Noise
Rev.
Delete PR260 and PR261
Change PQ55 from IMD2AT to 2N7002DW
Add PR291, PR292, PR293, PR294, PC193 and PD36
Change PQ30 and PQ31 from SI7326DN-T1-E3 to FDMC8878
Change PQ32 from SI7230DN-T1-E3 to FDMC8854
Change PC5 to SE00000GG8L(22U_0603) from SE002223K8L(22U_0806)
D
X02
X02
X03
PWM circuitry DH/DL still switch a few cycles in all
Add PR128 (10K_0402) between PWM1 to GND
3 phase after power off resulted in a voltage pulse
Add PR133 (10K_0402) Between PWM2 to GND
X03
observed at output Vcore with a negative voltage
( -0.24V approximately).
Chenge logic high level voltage for OE pin
Change PU25 and PU26 from SA000022Y0L(S IC VT351FCX-ADJ CSP 25P)X03
from 5V to 3.3V
to SA00002GE0L (S IC VT351AFCX-ADJ CSP 25P
To solve the EMI and system noisde issue
C
1.Boost resister.
a.CPU Vocre
Change PR87 and PR98 from 0ohm_0603 to 2.2ohm_0603
2 Snubber
a.CPU Vcore
Change PC99 and PC110 from 1500PF_0603 to 1000PF_0603
Stuff PR266 (4.7ohm_1206), PR267(4.7ohm_1206), PC99
and PC110.
b.5V/3.3V/Charger/GPU_Core
Change PC191, PC140, PC190 and PC189 from 1500PF_0603
to 1000PF_0603.
Change PR288, PR265, PR289 and PR290 from 4.7ohm_1206
to 2.2ohm_1206.
Stuff PC189, PC191, PC190, PC140, PR265, PR289,
PR288 and PR290.
C.1.5V/1.05V
Change PC187 and PC188 from 1500PF_0603 to 1000PF_0603.
Change PR286 and PR287 from 4.7ohm_1206 to 1ohm_1206.
Stuff PC187, PC188, PR286 and PR287.
X03
C
B
B
6
48
Selector
4/8
7
42
+3.3V/+5V
4/22
8
45
VCORE
4/22
9
46
Charger
6/2
10
46
11
41
Charger
DC_IN
6/2
6/3
A
12
46
Charger
6/20
Kenny
Compal
Kenny
Compal
LES
DELL
AJ
Compal
AJ
Compal
AJ
Compal
AJ
Compal
Current Derating issue
Change PQ41 and PQ42 from SI4835 to FDS6679Z
X03
Change PL6 and PL7 from SSC-1350F3-2R8 (TMP) to HMP1350-2R8
(Delta)
Material PSL issue
PWM circuitry DH/DL still switch a few cycles in all
3 phase after power off resulted in a voltage pulse
observed at output Vcore with a negative voltage
( -0.24V approximately).
Change PR128 and PR138
from
from
from
from
from
X03
from 10K_0402 to 33K_0402
Change UL setting from 65W to 90W
Change PC185
Change PR175
Change PR166
Cgange PR171
Change PR172
Pop Pr169
SLICE_BAT_PRES# glitch issue
Add PC38 (1500n)
Follow the common design
Change PR354 from 10K to 100K
De-POP PR355
M09 NB_AC_IN design change for sequence issue
X03
1000p to 100p.
100K to 24K
57.6K to 51.1K
13K to 17.8K
105 to 348
X05
between PQ47 to GND
X05
X05
A
X05
5
4
3
2
Title
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
56
of
57
5
4
3
2
1
Item Page#
D
43
1
2
47
45
3
4
42/45/46
Title
+1.5V/1.05V
+Vgfx_Core
Date
Request
Owner
Issue Description
Rev.
6/20
Henry
Compal
Change PR65 pull high voltage from +3.3V_SUS to +3.3V_ALW
Change PR65 pull high voltage from +3.3V_SUS to +3.3V_ALW
6/20
Kenny
Compal
Load lide 6.9mohm to follow HW North Bridge setting
on performance mode
Change PR239 from 49.9K to 69.8K
+Vcore
6/20
Kenny
Compal
EMI ISN
6/25
EMI
Compal
X05
Modify the CPU power monitor error on thermal control panel Change PR139 from 22.1K to 14.3K
EMI ISN issue
D
X05
X05
Add PL15(FBMJ4516HS720NT) and PC222(470P_0402)
Change PR155 from 0 ohm to 4.7 ohm.
Change PR37 from 1ohm to 4.7 ohm.
POP PL12 and de-POP PJP32
X05
C
C
5
46
Charger
7/4
Merle
Dell
Because the the average current is not over 3A(65W adapter).Depop UL circuit, pop PR170
X05
B
B
A
A
5
4
3
2
Title
Size
Document Number
Date:
Rev
1.0
LA-4151P
Sheet
1
57
of
57

compal confidential

Transcription

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