Compal LA-6062P - Schematics. www.s

Transcription

A
B
C
D
E
1
1
NWQAA
Marseille 10G
2
2
LA-6062P REV 2.0 Schematic
Intel Processor(CFD/ARD) / PCH(HM57/HM55/PM55)
2010-03-24 Rev 2.0
3
3
4
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
200910/9
Issued Date
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Cover Page
Size
B
Date:
Document Number
Rev
2.0
NWQAA LA-6062P M/B
W ednesday, March 24, 2010
Sheet
E
1
of
59
A
B
C
D
E
Fan Control
Intel Arrandale /
Clarksfield
PCIE-Express 16X 2.5GHz
VGA Thermal Sensor
APL5607
Clock Generator
ADM1032ARMZ-2
page 6
RTM890N
page 14
page 25
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
1
rPGA-989
Dual Channel
page 5,6,7,8,9,10
1
page 11,12
BANK 0, 1, 2, 3
1.5V DDRIII 800/1066/1333 MT/s
VGA (DDR3)
NVIDIA N11M GE1, 64bit with 512MB/1GB
USB/B Right
CRT
FDI X8
page 26
DMI X4
2.7GHz
NVIDIA N11P GE1, 128bit with 1GB/2GB
Left USB
USB port 0,1
page 37
2.5GHz
BT conn
page 13,14,15,16,17,18,19,20,21,22,23,24
Felica
USB port 5
page 38
USB
FingerPrinter
USB port 2
page 37
USB port 8
page 38
Int. Camera
USB port 9
page 38
USB port 11
page 25
5V 480MHz
LVDS Conn.
page 25
2
USB
5V 480MHz
EC SMBus
HDMI-CEC
Level Shifter
HDMI Conn.
page 27
PCIe 1x
page 27
page 40
PCIeMini Card
WLAN PCIe port 2
PCIeMini Card
JET
PCIe port 4
page 39
Intel Ibex Peak
RTL8105E 10/100M
RTL8111E 1G PCIe port 1
RJ45
PCIeMini Card
page 39
1.5V 2.5GHz(250MB/s)
page 27
PCIeMini Card
WiMax USB port 13
SATA port 1
PCIe 1x
5V 3GHz(300MB/s)
B-CAS
page 38
SATA port 1
page 37
Express Card
USB USB port 4
2
page 39
Express Card
PCIe PCIe port 3
page 39
SIM
page 39
BGA-951
SATA port 4
Cardreader
JMB385C/389C
USB port 12
USB port 10
page 39
page 39
SATA HDD
1.5V 2.5GHz(250MB/s)
page 40
3G/TV#1
TV#2
5V 3GHz(300MB/s)
SATA ODD
SATA port 4
page 37
PCIe 1x
1.5V 2.5GHz(250MB/s)
page 28,29,30,31,32,33,34,35,36
PCIe port5
page 41
3
SATA port 5
5V 3GHz(300MB/s)
eSATA
SATA port 5
page 37
USB port 3
5V 480MHz
LPC BUS
USB
3
USB port 3
page 37
3.3V/1.5V 24MHz
HD Audio
3.3V 33 MHz
TP& Light Pipe/B
LS-6061P page 45
RTC CKT.
page 28
DC/DC Interface CKT.
Cap Sensor
& Light Sensor/B
LS-6062P page 45
LED/B
LS-6063P
Debug Port
ENE KB926 D3/E0
page 44
Touch Pad
page 45
Int.KBD
page 44
page 36
EC ROM
(256KB)
page 44
Power Circuit DC/DC
page 47,48,49,50,51,52
53,54,55,56
Power On/Off CKT.
page 45
CIR
page 43
page 42
G-Sensor
page 44
Int.
MIC Conn
37
JPIO
(HP &page
MIC)
37
page 42
Finger Printer/B
LS-6065P page
38
4
200910/9
Issued Date
Compal Secret Data
Deciphered Date
2010/01/23
Title
Size
page 45
Date:
A
SPK Conn
page 25
EC SMBus
Audio & USB/B
LS-6064P page
Power/B_FPC
DA300006F00
ALC269
page 38
page 43
page 46
4
HDA Codec
MDC 1.5 Conn
SPI ROM
(4MB)
page 28
B
C
D
Block Diagram
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Tuesday, March 23, 2010
Sheet
E
2
of
59
5
4
3
2
1
DESIGN CURRENT 0.1A
+3VL
+5VL
DESIGN CURRENT 0.1A
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9
DESIGN CURRENT 5A
+5VALW
DESIGN CURRENT 2A
+1.8VS
SUSP#
MP2121DQ
SUSP
DESIGN CURRENT 4A
N-CHANNEL
D
+5VS
D
BCPWON
SI4800
DESIGN CURRENT 0.5A
+5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED
RT8205EGQW
DESIGN CURRENT 400mA
+5VS_LED
+3VS_HDP
DESIGN CURRENT 1.6A
+5VS_ODD
P-CHANNEL
AO-3413
+5VS
LDO
G9191
ODD_EN#
P-CHANNEL
AO-3413
DESIGN CURRENT 5A
+3VALW
WOL_EN#
P-CHANNEL
AO-3413
SUSP
+3V_LAN
DESIGN CURRENT 4A
N-CHANNEL
+3VS
LCD_ENVDD
SI4800
P-CHANNEL
AO-3415
C
DESIGN CURRENT 1.5A
+LCD_VDD
C
BT_PWR#
P-CHANNEL
AO-3413
+BT_VCC
FELICA_PWR
DESIGN CURRENT 0.5A
+FLICA_VCC
DESIGN CURRENT 0.5A
+3VS_DGPU
DESIGN CURRENT 48A
+CPU_CORE
DESIGN CURRENT 28A
+VGA_CORE
P-CHANNEL
AO-3413
DGPU_PWR_EN
P-CHANNEL
AO-3413
VR_ON
ISL62883HRZ
SUSP# or DGPU_PWR_EN
APW7138NITRL
VTTP_EN
DESIGN CURRENT 18A
+VTT
APW7138NITRL
SUSP#
B
DESIGN CURRENT 7A
+1.05VS
DESIGN CURRENT 3A
+1.05VS_DGPU
RT8209BGQW
B
DGPU_PWR_EN
P-CHANNEL
AO-3413
SUSP#
DESIGN CURRENT 15A
+1.5V
SUSP
RT8209BGQW
DESIGN CURRENT 2A
N-CHANNEL
+1.5V_CPU
FDS6676AS
SUSP
DESIGN CURRENT 2A
N-CHANNEL
+1.5VS
FDS6676AS
VGA_PWROK
DESIGN CURRENT 10A
N-CHANNEL
+VRAM_1.5VS
FDS6676AS
SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A
G2992F1U
A
+0.75VS
A
GFXVR_EN
DESIGN CURRENT 22A
ADP3211AMNR2G
+GFX_CORE
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
Title
Size
Date:
5
4
3
2
Power Tree
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
3
of
59
A
B
C
D
Platform
Voltage Rails
( O MEANS ON
+RTCVCC
+5VL
+5VALW
+3VL
+3VALW
+1.5V
+5VS
Calpella
+3VS
+1.8VS
+VSB
power
plane
1
SKU
CPU
PCH
UMA(OPT@) Arrandale
HM55@/HM57@
Discrete Clarksfield/
HM55@/HM57@/PM55@
Arrandale
(DIS@)
Optimus
Arrandale
HM55@/HM57@
(OPT@)
X MEANS OFF )
B+
E
VGA
N/A
N11P@/N11M@
N11P@/N11M@
+1.5VS
1
+1.05VS
BTO Option Table
+0.75VS
+CPU_CORE
+VGA_CORE
HDMI
Function
+GFX_CORE
+VTT
State
+VRAM_1.5VS
explain
UMA
Discrete/
Optimus
BTO
IHDMI@
DHDMI@
+3VS_DGPU
+1.05VS_DGPU
O
O
O
O
O
O
S1
O
O
O
O
O
O
S3
O
O
O
O
O
X
O
O
O
O
X
X
O
O
O
X
X
X
explain
O
X
X
X
X
X
BTO
BTO
2
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
3G
3
Device
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
Clock Generator
D2 H
1101 0010 b
+3VS
New Card
+3VS
WLAN/WIMAX
+3VS
Clock Generator
+3VS
3G
Clarksfield with
S3 Power Saving
CEC@
M1@
M3@
PSM3@
LAN
SLOT1
Fingerprint
LAN
WIMAX
10/100M
TV@
WIMAX@
8105E@
Felica
G-SENSOR
description Felica
BLUE TOOTH
G-SENSOR
SKU
Felica
BLUE TOOTH
G-SENSOR
Discrete
BT@
GSENSOR@
FELICA@
KB Light
KB Light
8111E@
FP@
MDC@
CIR@
KBL@
No Power Saving
BTO
NOPS@
Camera & Mic
Discrete
Camera & Mic
3D@
Optimus
NO3D@
Camera & Mic
OPTFH@
CAM@
GPU
New Card
N11P & N11E
Power Saving
PS@
New Card
N11M
VRAM
N11P
N11E
N11M-GE1
N11M-OP1
8PCS@
N11P@
N11E@
N11MGE@
N11MOP@
New Card
NEW@
3
Card reader
Function
JMB385C/389C
explain
JMB385C
JMB389C
BTO
JMB385@
JMB389@
SIGNAL
Full ON
SLP_S3# SLP_S4# SLP_S5#
HIGH
HIGH
HIGH
Address
Power
Device
HEX
Address
S1(Power On Suspend)
HIGH
HIGH
HIGH
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
S3 (Suspend to RAM)
LOW
HIGH
HIGH
+3VL
HDMI-CEC
34 H
0011 0100 b
+3VS
NVIDIA GPU
9A H
1001 1010 b
LOW
LOW
HIGH
G-Sensor
40 H
S4 (Suspend to Disk)
+3VS
0100 0000 b
+3VS
Light Sensor
52 H
0101 0010 b
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
Cap. Sensor
CIR
CIR
OPT@
HEX
+3VL
Modem
Modem
S3 Power Saving
explain
EC SM Bus2 Address
DIS@
Smart Battery
Address
Fingerprint
3D Panel
Device
HEX
KB Light
Fingerprint
Optimus
Power
Device
CIR
LVDS
+3VL
Power
Modem
Giga
SKU
S3 Power Saving
STATE
4
Clarksfield
BLUE TOOTH
Function
description
EC SM Bus1 Address
Arrandale
2
description
Power
Clarksfield
CEC
TV Tuner
3G@
Function
PCH SM Bus Address
COMMON
HDMI@
SLOT2
description
explain
Arrandale
MINI PCI-E SLOT
Function
S0
CPU
HDMI
description
4
Virtual I2C
200910/9
Issued Date
Compal Secret Data
Deciphered Date
2010/01/23
Title
Size Document Number
Custom
Notes List
Rev
2.0
NWQAA LA-6062P M/B
Date:
A
B
C
D
Sheet
E
4
of
59
5
4
3
2
1
JCPUB
1 C488 VTTPWROK_CPU
+VTT
TP_SKTOCC#
AH24
SKTOCC#
2
49.9_0402_1%
CATERR#
AK14
CATERR#
PECI
<33> PECI
AT15
THERMAL
1
R18
D
T41 PAD
PECI
Power has removed VR_TT#
H_PROCHOT#
2
68_0402_5%
1
R9
+VTT
+VTT
H_THERMTRIP#
<33> H_THERMTRIP#
2
AN26
AK15
PROCHOT#
THERMTRIP#
BCLK_ITP
BCLK_ITP#
AR30
AT30
PEG_CLK
PEG_CLK#
E16
D16
CLK_CPU_XDP_R 1
CLK_CPU_XDP
2
CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP#
R42 @
0_0402_5%
CLK_PEG
CLK_PEG <29>
CLK_PEG#
CLK_PEG# <29>
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A18
A17
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
XDP_RST#_R
<30> PMSYNCH
2
0_0402_5%
+1.5V_CPU
RESET_OBS#
AL15
PM_SYNC
1 H_PWRGOOD1_R
R25
AN14
VCCPW RGOOD_1
H_PWRGOOD
<33> H_PWRGOOD
AN27
VCCPW RGOOD_0
2
C
AP26
PMSYNCH
PWR MANAGEMENT
H_CPURST#
2
1K_0402_5%
1
R36
R28
1.1K_0402_1%
NOPS@
<30> DRAMPWROK
1
<51> VTTPWROK_CPU
DRAMPWROK
AK13
SM_DRAMPW ROK
VTTPWROK_CPU
AM15
VTTPW RGOOD
TAPPWRGD
AM26
TAPPW RGOOD
AL14
RSTIN#
2
DRAMPWROK
R29
3K_0402_1%
NOPS@
BUF_PLT_RST#_R
<32> BUF_PLT_RST#
1.5K_0402_1%
R30
R31
750_0402_1%
1
R29
750_0402_1%
PS@
JTAG & BPM
H_CPURST#
Unused by Clarksfield rPGA989
AN15 PM_EXTTS#0
AP15 PM_EXTTS#_R
2
R12
AT28
AP27
XDP_PRDY#
XDP_PREQ#
TCK
TMS
TRST#
AN28
AP28
AT27
XDP_TCK
XDP_TMS
XDP_TRST#
TDI
TDO
TDI_M
TDO_M
AT29
AR27
AR29
AP29
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
DBR#
AN25
XDP_DBRESET#
IC,AUB_CFD_rPGA,R0P9
PM_EXTTS#0
R6 1
R7 1
R8 1
PRDY#
PREQ#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
+VTT
SM_DRAMRST#_CPU
AL1 SM_RCOMP_0
AM1 SM_RCOMP_1
AN1 SM_RCOMP_2
1
R10
68_0402_5%
@
F6
CLK_CPU_BCLK <33>
CLK_CPU_BCLK# <33>
DDR3 Compensation Signals
Layout Note:Please these
resistors near Processor
2 100_0402_1%
2 24.9_0402_1%
2 130_0402_1%
1
0_0402_5%
2
R312
1
1K_0402_5%
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_PRDY#
1
R40
XDP_PREQ#
1
R51
XDP_TCK
1
R449
XDP_TMS
1
R450
XDP_TRST#
1
R453
XDP_BPM#0
1
R454
XDP_BPM#1
1
R452
XDP_BPM#2
1
R451
XDP_BPM#3
1
R455
XDP_DBRESET# 1
R456
@
@
@
@
@
@
@
@
@
@
@
XDP_BPM#0_R
XDP_BPM#1_R
1
PS@
R123
100K_0402_5%
DRAMPWROK
1.5K_0402_1%
2
H_PWRGOOD
TAPPWRGD
SM_DRAMRST# <11,12>
Q41
BSS138_NL_SOT23-3
PS@
R32 1
R35 1
@
@
2 1K_0402_5% H_PWRGOOD_R
TAPPWRGD_R
2 0_0402_5%
CLK_CPU_XDP
CLK_CPU_XDP#
+VTT
XDP_RST#_R
XDP_DBRESET#_R
RST_GATE <11,33>
2
2
1
C140
0.047U_0402_25V6K
PS@
C1
0.1U_0402_10V6K
@ 2
Add C140 for RST_GATE Glitch issue
R14
1
51_0402_5%
1
1
SN74AHC1G08DCKR_SC70-5
PS@
XDP_TDO_M
1 @
R21
2
0_0402_5%
XDP_TDO
1 @
R26
2
0_0402_5%
1
R27
2
0_0402_5%
C
JTAG MAPPING
Scan Chain
(Default)
STUFF -> R20, R23, R27
NO STUFF -> R21, R26
CPU Only
STUFF -> R20, R21
NO STUFF -> R23, R26, R27
GMCH Only
STUFF -> R26, R27
NO STUFF -> R20, R21, R23
R11
51_0402_5%
1
0_0402_5%
XDP_TDO
XDP_TRST#_R
XDP_TDI
XDP_TMS_R
XDP_TCK_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
@
GND
GND
25
26
2
@
R33
1
2
5
P
G
3
2
R52
4
3
G
O
IN2
D
2
IN1
XDP_TDI
XDP_TDO_R
XDP_PRDY#_R
2
0_0402_5%
XDP_PREQ#_R
2
0_0402_5%
XDP_TCK_R
2
0_0402_5%
XDP_TMS_R
2
0_0402_5%
XDP_TRST#_R
2
0_0402_5%
XDP_BPM#0_R
2
0_0402_5%
XDP_BPM#1_R
2
0_0402_5%
XDP_BPM#2_R
2
0_0402_5%
XDP_BPM#3_R
2
0_0402_5%
XDP_DBRESET#_R
2
0_0402_5%
1
0_0402_5%
S
<46,51> VTTPWROK
2
0_0402_5%
XDP_TDI_M
XDP_BPM#2_R
XDP_BPM#3_R
PS@
1
R20
B
SM_DRAMRST#_CPU
U10
XDP_TDI_R
XDP Connector
2
R19
1
1 10K_0402_5%
+3VS
NOPS@
VTTPWROK
2
XDP_DBRESET# <30>
JXDP
PS@
1
2
C163
0.1U_0402_16V4Z
PM_EXTTS#_R R13
D
R23
0_0402_5%
XDP_PREQ#_R
XDP_PRDY#_R
+3VALW
1 10K_0402_5%
Routed as a single daisy chain
For S3 CPU Power Saving
B
2
PM_EXTTS# <11,12>
Close to CPU for EMI
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
R15
1
COMP0
@
1000P_0402_50V7K 2
CLK_CPU_BCLK
CLK_CPU_BCLK#
2
COMP1
A16
B16
BCLK
BCLK#
CLOCKS
DRAMPWROK
COMP2
DDR3
MISC
1 C487
COMP3
MISC
@
1000P_0402_50V7K 2
H_COMP3 AT23
2
20_0402_1%
H_COMP2 AT24
2
20_0402_1%
H_COMP1 G16
2
49.9_0402_1%
H_COMP0 AT26
2
49.9_0402_1%
1
R1
1
R2
1
R4
1
R3
MOLEX_52435-2472
A
A
Issued Date
Compal Secret Data
200910/9
2010/01/23
Deciphered Date
Title
CPU_CLK/MISC/JTAG/XDP
Custom
Rev
2.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Wednesday, March 24, 2010
Sheet
1
5
of
59
5
4
3
2
1
FAN Control Circuit
+5VS
1A
JFAN
2
C3
10U_0805_10V4Z
D
1
2
U1
1
2
3
4
+FAN1
<43> EN_DFAN1
10mil
1
2
EN
VIN
VOUT
VSET
GND
GND
GND
GND
8
7
6
5
1
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
<30>
<30>
<30>
<30>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<30>
<30>
<30>
<30>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B24
D23
B23
A22
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
D24
G24
F23
H23
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
D25
F24
E23
G23
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
E22
D21
D19
D18
G21
E19
F21
G18
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
D22
C21
D20
C18
G22
E20
F20
G19
<30> FDI_FSYNC0
<30> FDI_FSYNC1
FDI_FSYNC0
FDI_FSYNC1
F17
E17
<30> FDI_INT
FDI_INT
C17
<30> FDI_LSYNC0
<30> FDI_LSYNC1
FDI_LSYNC0
FDI_LSYNC1
F18
D17
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
Intel(R) FDI
B
<30>
<30>
<30>
<30>
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
DMI
C
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
Close to CPU
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
A
FDI_LSYNC0
FDI_LSYNC1
1 DIS@
R689
1 DIS@
R690
1 DIS@
R695
1 DIS@
R696
1 DIS@
R697
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
1
2
3
C4
1000P_0402_25V8J
@
4
5
GND
GND
B26
A26
B27
A25
PEG_COMP 1
R38
R34
2
PEG_RBIAS 1
2
R39
750_0402_1%
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_N15
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P15
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15
PCIE_GTX_C_CRX_N[0..15]
10K_0402_5%
1
+3VS
FAN_SPEED1 <43>
2
49.9_0402_1%
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
D
ACES_85204-0300N
C6
0.01U_0402_16V7K
@
PCI EXPRESS -- GRAPHICS
<30>
<30>
<30>
<30>
A24
C23
B22
A21
1
2
3
APL5607KI-TRG_SO8
C5
10U_0805_10V4Z
JCPUA
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
@
+FAN1
2
1
<13>
C
PCIE_GTX_C_CRX_P[0..15]
<13>
PCIE_CTX_C_GRX_N[0..15]
<13>
B
PCIE_CTX_C_GRX_P[0..15]
<13>
A
@
200910/9
Issued Date
Compal Secret Data
Deciphered Date
2010/01/23
Title
Custom
CPU_DMI/FDI/PEG/FAN
Rev
2.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Sheet
1
6
of
59
5
4
3
2
JCPUC
1
JCPUD
<12> DDR_B_D[0..63]
C
B
<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2
<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_W E#
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AC3
AB2
U7
SA_BS[0]
SA_BS[1]
SA_BS[2]
DDR_A_CAS#
DDR_A_RAS#
DDR_A_W E#
AE1
AB3
AE9
SA_CAS#
SA_RAS#
SA_WE#
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AA6
AA7
P7
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
Y6
Y5
P6
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1
SA_CS#[0]
SA_CS#[1]
AE2
AE8
DDRA_SCS0#
DDRA_SCS1#
SA_ODT[0]
SA_ODT[1]
AD8
AF9
DDRA_ODT0
DDRA_ODT1
DDRA_CLK0 <11>
DDRA_CLK0# <11>
DDRA_CKE0 <11>
DDRA_CLK1 <11>
DDRA_CLK1# <11>
DDRA_CKE1 <11>
DDRA_SCS0# <11>
DDRA_SCS1# <11>
DDRA_ODT0 <11>
DDRA_ODT1 <11>
DDR_A_DM[0..7]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
DDR SYSTEM MEMORY A
D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
B9
D7
H7
M7
AG6
AM7
AN10
AN13
<11>
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
C9
F8
J9
N9
AH7
AK9
AP11
AT13
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
C8
F9
H9
M9
AH8
AK10
AN11
AR13
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
<11>
<11>
<11>
<12> DDR_B_BS0
<12> DDR_B_BS1
<12> DDR_B_BS2
<12> DDR_B_CAS#
<12> DDR_B_RAS#
<12> DDR_B_W E#
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AB1
W5
R7
SB_BS[0]
SB_BS[1]
SB_BS[2]
DDR_B_CAS#
DDR_B_RAS#
DDR_B_W E#
AC5
Y7
AC6
SB_CAS#
SB_RAS#
SB_WE#
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
W8
W9
M3
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
V7
V6
M2
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1
SB_CS#[0]
SB_CS#[1]
AB8
AD6
DDRB_SCS0#
DDRB_SCS1#
SB_ODT[0]
SB_ODT[1]
AC7
AD1
DDRB_ODT0
DDRB_ODT1
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
D4
E1
H3
K1
AH1
AL2
AR4
AT8
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D5
F4
J4
L4
AH2
AL4
AR5
AR8
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C5
E3
H4
M5
AG2
AL5
AP5
AR7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDRB_CLK0 <12>
DDRB_CLK0# <12>
DDRB_CKE0 <12>
D
DDRB_CLK1 <12>
DDRB_CLK1# <12>
DDRB_CKE1 <12>
DDRB_SCS0# <12>
DDRB_SCS1# <12>
DDRB_ODT0 <12>
DDRB_ODT1 <12>
DDR_B_DM[0..7]
<12>
C
DDR SYSTEM MEMORY - B
<11> DDR_A_D[0..63]
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
<12>
<12>
B
DDR_B_MA[0..15]
<12>
@
A
A
@
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
5
4
3
2
Title
CPU_DDR3
Size
B
Date:
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
7
of
59
5
4
A
1
(Place these capacitors under CPU socket Edge, top layer)
(Place these capacitors between inductor and socket on Bottom)
+VTT
+CPU_CORE
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
10U_0805_10V4K
Change C144 to 4.5mm height at DVT
C144 1
C267 1
2 330U_2.5V_M_R17
C81 1
2 10U_0805_10V4K
2 390U_2.5V_M_R10
C83 1
2 10U_0805_10V4K
C85 1
2 10U_0805_10V4K
C89 1
2 10U_0805_10V4K
C88 1
2 10U_0805_10V4K
C90 1
2 10U_0805_10V4K
C92 1
2 10U_0805_10V4K
C94 1
2 10U_0805_10V4K
1
2
1
C71
2
10U_0805_10V4K
C87 1
C91 1
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
D
+
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
+
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
1
C72
2
1
C73
2
10U_0805_10V4K
1
C74
2
1
C75
2
10U_0805_10V4K
1
C76
2
1
C77
2
10U_0805_10V4K
1
C78
2
C79
10U_0805_10V4K
2 22U_0805_6.3V6M
2 22U_0805_6.3V6M
(Place these capacitors under CPU socket, top layer)
+CPU_CORE
@
10U_0805_10V4K
1
2
10U_0805_10V4K
1
C98
2
10U_0805_10V4K
1
C99
2
1
C100
2
10U_0805_10V4K
10U_0805_10V4K
1
C101
2
1
C102
10U_0805_10V4K
2
1
C103
C104
2
10U_0805_10V4K
(Place these capacitors on CPU cavity, Bottom Layer)
5/25: Add for power team request.
C
+CPU_CORE
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
C158
1
C150
1
C128
22U_0805_6.3V6M
1
C127
1
22U_0805_6.3V6M
C120
1
C118
1
C119
C117
1
C129
1
C105
1
C106
2
2
2
2
2
2
2
2
2
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C107
2
1
C108
2
1
C109
22U_0805_6.3V6M
2
1
C110
2
1
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
22U_0805_6.3V6M
1
C111
C112
2
POWER
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
1.1V RAIL POWER
Auburndale:18A
CPU CORE SUPPLY
B
Clarksfield: 21A
Auburndale:48A
PSI#
CPU VIDS
C
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
Clarksfield: 65A
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
VTT_SELECT
AN33
H_PSI#
AK35 CPU_VID0
AK33 CPU_VID1
AK34 CPU_VID2
CPU_VID3
AL35
CPU_VID4
AL33
AM33 CPU_VID5
AM35 CPU_VID6
AM34 H_DPRSLPVR_R 1
R62
G15
CRB default setting:
VID[6:0]=[0100111]
H_PSI# <54>
2
0_0402_5%
H_VTTSELECT
CPU_VID0 <54>
CPU_VID1 <54>
CPU_VID2 <54>
CPU_VID3 <54>
CPU_VID4 <54>
CPU_VID5 <54>
CPU_VID6 <54>
H_DPRSLPVR <54>
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
AN35
IMVP_IMON
AJ34
AJ35
VCCSENSE_R R65
VSSSENSE_R R66
B15
A15
VTT_SENSE
VSS_SENSE_VTT
C113
22U_0805_6.3V6M
1
C114
2
1
C115
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C116
2
1
2
22U_0805_6.3V6M
B
TOP side (under inductor)
Auburndale +1.1VS_VTT=1.05V
Clarksfield +1.1VS_VTT=1.1V
H_VTTSELECT <51>
1
2
22U_0805_6.3V6M
VTT Rail
+CPU_CORE
1
1
+
+
330U_D2_2.5VM_R9M
1
C123
+
330U_D2_2.5VM_R9M
2
2
330U_D2_2.5VM_R9M
2
C121
H_VTTSELECT = low, 1.1V
H_VTTSELECT = high, 1.05V
SENSE LINES
D
2
Material Note (+VTT):
390uF/ 10mohm, number are 3,
power x1, HW x2
JCPUF
+CPU_CORE
3
C122
1
+
C124
1
C125
@
+
330U_D2_2.5VM_R9M
2
2
330U_D2_2.5VM_R9M
IMVP_IMON <54>
1
1
2 0_0402_5%
2 0_0402_5%
1
R64
VCCSENSE
VSSSENSE
1
VTT_SENSE <51>
VSS_SENSE_VTT <51>
R67
2
100_0402_1%
+CPU_CORE
VCCSENSE <54>
VSSSENSE <54>
Check list:
2
100_0402_1%
+CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF
Close to CPU
+VTT: 4x 330uF, 7x 22uF, 8x 10uF
A
Issued Date
Compal Secret Data
@
200910/9
2010/01/23
Deciphered Date
Title
Custom
CPU_POWER-1
Rev
2.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Sheet
1
8
of
59
5
4
3
2
1
+1.5V_CPU
For EMI
+1.5V
Q33
1
2
3
4
2
+GFX_CORE
S
S
S
G
D
D
D
D
8
7
6
5
FDS6676AS_SO8
R418
1
2
220K_0402_5%
PS@
SUSP
+VSB
D
R417
820K_0402_5%
PS@
2
Q46A
PS@
2 SUSP
1
2N7002DW-T/R7_SOT363-6
C472
0.1U_0402_25V6
PS@
2
47P_0402_50V8J
1
6
1
3 1
Q46B
PS@
5
D
47P_0402_50V8J
2
C179
10U_0805_10V4K
PS@
4
1
C272
@
2
1
C281
@
1
R424
470_0805_5%
PS@
47P_0402_50V8J
2
1
C280
@
2
C279
@
2
1
47P_0402_50V8J
PS@
SUSP <46,53>
2N7002DW-T/R7_SOT363-6
Close to CPU
+GFX_CORE
22U_0805_6.3V6M
C
2
C247
OPT@
C286
OPT@
2
1U_0402_6.3V4Z
C250
OPT@
2
1
C248
OPT@
2
10U_0805_6.3V6M
C247
0_0402_5%
DIS@
Co-layout with C271
+GFX_CORE
1
C494 +
330U_D2_2VM_R6M
@
2
22A
GRAPHICS
Change C271 to OS-CON at PVT
C266
OPT@
1
Clarksfield: 5A
Auburndale:3A
+VTT
1
2
1
2
C142
VTT1_45
VTT1_46
VTT1_47
FDI
C141
22U_0805_6.3V6M
J24
J23
H25
1 OPT@ 2
R510
100_0402_1%
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
AR25
AT25
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
2
C147
22U_0805_6.3V6M
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
2 0.1U_0402_16V4Z
C185 1
2 0.1U_0402_16V4Z
1 1K_0402_5%
1U_0402_6.3V4Z
C133
C134
2
1
C135
2
1U_0402_6.3V4Z
1
C136
2
22U_0805_6.3V6M
1
C137
2
1U_0402_6.3V4Z
1
1
C138
2
1
+1.5V
JUMP_43X79
+ C216
For EMI
C139
2
1U_0402_6.3V4Z
C
1
JUMP_43X79
PJ31 @
2 2
1 1
1
1
@
2
2
+1.5V_CPU
1U_0402_6.3V4Z
1
2 0.1U_0402_16V4Z
PJ30
2
2
390U_2.5V_M_R10
+1.5V_CPU
+1.5V
22U_0805_6.3V6M
@
1
2
@
1
2
@
1
2
@
1
2
(Place these capacitors under CPU socket Edge, top layer)
P10
N10
L10
K10
1
2
C143
B
10U_0805_10V4K
J22
J20
J18
H21
H20
H19
1
2
C145
22U_0805_6.3V6M
+1.8VS
VCCPLL1
VCCPLL2
VCCPLL3
Clarksfield: 1.35A
L26
L27
M26
+1.8VS_H_PLL 1U_0402_6.3V4Z
C151
1U_0402_6.3V4Z
Auburndale:1.35A
2 0.1U_0402_16V4Z
C186 1
C180 1
GFXVR_EN
T54 PAD
GFXVR_IMON <55>
GFXVR_DPRSLPVR
GFXVR_IMON
C205 1
+VTT
1.1V
1
For EMI
470 ohm
+VTT
VTT0_59
VTT0_60
VTT0_61
VTT0_62
1.8V
2
<55>
<55>
<55>
<55>Change R136 to
<55>for GFX issue
<55>
<55>
OPT@
1
2
R136
470_0402_5%
<55>
Auburndale:18A
PEG & DMI
22U_0805_6.3V6M
GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6
DIS@
Clarksfield: 21A
1
GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6
R687 2
B
C146
AM22
AP22
AN22
AP23
AM23
AP24
AN24
GFXVR_EN
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
22U_0805_6.3V6M
+VTT
C257
0.1U_0402_16V4Z
2
1
1 OPT@ 2
+GFX_CORE
R509
100_0402_1%
2 0_0402_5%
VCC_AXG_SENSE <55>
2 0_0402_5%
VSS_AXG_SENSE <55>
R117 1 OPT@
R142 1 OPT@
C258
0.1U_0402_16V4Z
C249
OPT@
2
1
VCC_AXG_SENSE_R
VSS_AXG_SENSE_R
AR22
AT22
C256
0.1U_0402_16V4Z
+
2
1
VAXG_SENSE
VSSAXG_SENSE
C160
0.1U_0402_16V4Z
C271
330U_2.5V_M_R17
OPT@
1
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
- 1.5V RAILS
1
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
DDR3
10U_0805_6.3V6M
GRAPHICS VIDs
1U_0402_6.3V4Z
POWER
22U_0805_6.3V6M
SENSE
LINES
JCPUG
1
1
2
2
4.7U_0603_6.3V6K
1
C152
2
R71
1
0_0805_5%
1
C153
2
C154
C155
2 22U_0805_6.3V6M
2.2U_0603_6.3V4Z
@
A
A
Issued Date
Compal Secret Data
200910/9
Deciphered Date
2010/01/23
Title
Custom
CPU_POWER-2
Rev
2.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Sheet
1
9
of
59
4
3
JCPUI
C
B
1
JCPUH
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
NCTF
D
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
2
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
H_NCTF1
H_NCTF2
H_NCTF6
H_NCTF7
PAD T4
PAD T5
PAD T6
PAD T7
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUE
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
@
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30
+VREF_DQA_M3
+VREF_DQB_M3
WW41 Recommend not pull down
PCIE2.0 Jitter is over on ES1
3.01K_0402_1% 1 @ R74
2
3.01K_0402_1% 1 @ R75
3.01K_0402_1% 1 @ R76
2
2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86
RSVD32
RSVD33
AJ13
AJ12
RSVD34
RSVD35
AH25
AK26
RSVD36
RSVD_NCTF_37
AL26
AR2
RSVD38
RSVD39
AJ26
AJ27
RSVD_NCTF_40
RSVD_NCTF_41
AP1
AT2
RSVD_NCTF_42
RSVD_NCTF_43
AT3
AR1
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65
E15
F15
A2
D15
C15
AJ15
AH15
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
Reserve via for test
B19
A19
RSVD15
RSVD16
A20
B20
RSVD17
RSVD18
U9
T9
RSVD19
RSVD20
AC9
AB9
RSVD21
RSVD22
CFG0 - PCI-Express Configuration Select
*1:Single PEG
0:Bifurcation enabled
C1
A3
CFG3 - PCI-Express Static Lane Reversal
*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
RSVD_NCTF_23
RSVD_NCTF_24
J29
J28
RSVD26
RSVD27
A34
A33
RSVD_NCTF_28
RSVD_NCTF_29
C35
B35
RSVD_NCTF_30
RSVD_NCTF_31
D
C
B
VSS
CFG4 - Display Port Presence
*1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
@
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9 (SA_DIMM_VREF)
RSVD10(SB_DIMM_VREF)
RSVD11
RSVD12
RSVD13
RSVD14
RESERVED
5
AP34
@
*:Default
A
A
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
5
4
3
2
Title
CPU_GND/RESERVED
Size
Document Number
Custom
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
1
10
of
59
3
+1.5V
DDR3 SO-DIMM A
Reverse Type
JDDRL
DDR_A_MA3
DDR_A_MA1
DDR_A_MA13
DDRA_SCS1#
<7> DDRA_SCS1#
DDR_A_D32
DDR_A_D33
B
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
R90 1
2
10K_0402_5%
A
2
1
2
5
R91
10K_0402_5%
2
1
1
C182
0.1U_0402_16V4Z
C181
2.2U_0603_6.3V4Z
+3VS
+0.75VS
205
207
GND1
GND2
2
1
2
DDR_A_DQS#3
DDR_A_DQS3
+1.5V
M3@
2
DDR_A_D30
DDR_A_D31
1
0_0402_5%
R94
+VREF_DQA
R111
1K_0402_1%
PSM3@
Q40
PSM3@
BSS138_NL_SOT23-3
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDRA_CKE1
DDRA_CKE1 <7>
3
+VREF_DQA_M3
DDR_A_MA15
DDR_A_MA14
PSM3@
R122
100K_0402_5%
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
2
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
RST_GATE
1
0_0402_5%
R95
+VREF_DQB
R116
1K_0402_1%
PSM3@
Q39
PSM3@
BSS138_NL_SOT23-3
3
+VREF_DQB_M3
DDRA_CLK1 <7>
DDRA_CLK1# <7>
PSM3@
R121
100K_0402_5%
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>
1
R115
1K_0402_1%
PSM3@
RST_GATE <5,33>
+V_DDR3_DIMM_REF
DDRA_ODT1 <7>
R89
1
0_0402_5%
+DDR_VREF_CA_DIMMA
DDR_A_D36
DDR_A_D37
C
R114
1K_0402_1%
+1.5V
PSM3@
M3@
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1
DDRA_CLK1#
1
G
DDR_A_W E#
DDR_A_CAS#
<7> DDR_A_W E#
<7> DDR_A_CAS#
M3@: Clarksfield
For Clarksfield S3 CPU Power Saving
DDR_A_D28
DDR_A_D29
D
DDR_A_MA10
DDR_A_BS0
<7> DDR_A_BS0
DDR_A_D22
DDR_A_D23
S
DDRA_CLK0
DDRA_CLK0#
<7> DDRA_CLK0
<7> DDRA_CLK0#
DDR_A_DM2
1
DDR_A_MA8
DDR_A_MA5
DDR_A_D20
DDR_A_D21
2
DDR_A_MA12
DDR_A_MA9
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
SM_DRAMRST# <5,12>
DDR_A_D14
DDR_A_D15
G
<7> DDR_A_BS2
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
D
R81
1K_0402_1%
1
R93
D
DDR_A_BS2
M1@
S
<7> DDRA_CKE0
C
R80
1K_0402_1%
PS@
DDR_A_D12
DDR_A_D13
1
DDRA_CKE0
R79
1K_0402_1%
2
DDR_A_D26
DDR_A_D27
+V_DDR3_DIMM_REF
<7>
2
DDR_A_DM3
DDR_A_MA[0..15]
1
DDR_A_D24
DDR_A_D25
+VREF_DQB
2
0_0402_5%
1
R92
2
DDR_A_D18
DDR_A_D19
2
0_0402_5%
2
DDR_A_DQS#2
DDR_A_DQS2
+VREF_DQA
<7>
2
DDR_A_D16
DDR_A_D17
+1.5V
M1@
<7>
1
DDR_A_D10
DDR_A_D11
DDR_A_DM[0..7]
DDR_A_D6
DDR_A_D7
DDR_A_DM1
SM_DRAMRST#
DDR_A_D[0..63]
+1.5V
<7>
2
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#0
DDR_A_DQS0
M1@: Arrandale
<7>
DDR_A_DQS#[0..7]
1
Close to JDDRL.1
DDR_A_DQS[0..7]
2
DDR_A_D8
DDR_A_D9
D
DDR_A_D4
DDR_A_D5
1
2
2
Layout Note:
Place near JDDRL
1
2
+1.5V
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA
+1.5V
C218 1
C166 1
+0.75VS
2 390U_2.5V_M_R10
close to JDDRL.126
DDR_A_D46
DDR_A_D47
B
Layout Note:
Place near JDDRL1.203 and 204
Change C218 to OSCON at DVT
+
DDR_A_D2
DDR_A_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
DDR_A_DM0
2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
1
2
1
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
C162
0.1U_0402_16V4Z
2
DDR_A_D0
DDR_A_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C161
2.2U_0603_6.3V4Z
1
C157
2.2U_0603_6.3V4Z
C156
0.1U_0402_16V4Z
+VREF_DQA
2
1
4
+1.5V
1
5
C164 1
2 0.1U_0402_16V4Z
C167 1
2 0.1U_0402_16V4Z
C170 1
2 0.1U_0402_16V4Z
C165 1
2 10U_0805_6.3V6M
C169 2
1 1U_0402_6.3V4Z
C172 2
1 1U_0402_6.3V4Z
2 10U_0805_6.3V6M
C168 1
2 10U_0805_6.3V6M
DDR_A_D52
DDR_A_D53
C171 1
2 10U_0805_6.3V6M
DDR_A_DM6
C174 1
2 10U_0805_6.3V6M
C175 2
1 1U_0402_6.3V4Z
DDR_A_D54
DDR_A_D55
C176 1
2 10U_0805_6.3V6M
C177 2
1 1U_0402_6.3V4Z
C178 1
2 10U_0805_6.3V6M
C173 1
2 0.1U_0402_16V4Z
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#
PM_SMBDATA
PM_SMBCLK
+0.75VS
A
PM_EXTTS# <5,12>
PM_SMBDATA <12,25,29,39>
PM_SMBCLK <12,25,29,39>
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
FOX_AS0A626-U2SN-7F_204P
@
4
3
2
Title
DDRIII-SODIMM0
Size
Document Number
Custom
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
1
11
of
59
A
B
+1.5V
C
D
E
+1.5V
JDDRH
2
DDR_B_DM0
1
DDR_B_D2
DDR_B_D3
2
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
close to JDDRH.1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDRB_CKE0
<7> DDRB_CKE0
2
DDR_B_BS2
<7> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDRB_CLK0
DDRB_CLK0#
<7> DDRB_CLK0
<7> DDRB_CLK0#
DDR_B_MA10
DDR_B_BS0
<7> DDR_B_BS0
DDR_B_W E#
DDR_B_CAS#
<7> DDR_B_W E#
<7> DDR_B_CAS#
DDR_B_MA13
DDRB_SCS1#
<7> DDRB_SCS1#
DDR_B_D32
DDR_B_D33
3
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R98 1
2
10K_0402_5%
4
+3VS
2.2U_0603_6.3V4Z
1
1
1 R99
2
10K_0402_5%
C207
C208
2
2
0.1U_0402_16V4Z
+0.75VS
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
205
207
GND1
GND2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
SM_DRAMRST#
1
SM_DRAMRST# <5,11>
DDR_B_DQS#[0..7]
DDR_B_D14
DDR_B_D15
DDR_B_DQS[0..7]
<7>
<7>
DDR_B_D20
DDR_B_D21
DDR_B_D[0..63]
<7>
DDR_B_DM2
DDR_B_DM[0..7]
<7>
DDR_B_MA[0..15]
DDR_B_D22
DDR_B_D23
<7>
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1
DDRB_CKE1 <7>
DDR_B_MA15
DDR_B_MA14
2
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>
+V_DDR3_DIMM_REF
DDRB_ODT1 <7>
R97
+DDR_VREF_CA_DIMMB
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
Layout Note:
Place near JDDRH
1
2
0_0402_5%
1
2
DDR_B_D46
DDR_B_D47
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB
Layout Note:
Place near JDDRH.203 and 204
3
+1.5V
1
+1.5V
@
C189 1
+0.75VS
2 330U_B2_2.5VM_R15M
2
DDR_B_DQS#5
DDR_B_DQS5
C191 1
2 10U_0805_6.3V6M
C195 2
1 1U_0402_6.3V4Z
C198 2
1 1U_0402_6.3V4Z
2 10U_0805_6.3V6M
C201 2
1 1U_0402_6.3V4Z
C202 1
2 10U_0805_6.3V6M
C203 2
1 1U_0402_6.3V4Z
C204 1
2 10U_0805_6.3V6M
C192 1
2 10U_0805_6.3V6M
C194 1
2 10U_0805_6.3V6M
C197 1
2 10U_0805_6.3V6M
C200 1
C190 1
2 0.1U_0402_16V4Z
C193 1
2 0.1U_0402_16V4Z
C196 1
C199 1
close to JDDRH.126
DDR_B_D52
DDR_B_D53
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#
PM_SMBDATA
PM_SMBCLK
+0.75VS
4
PM_EXTTS# <5,11>
PM_SMBDATA <11,25,29,39>
PM_SMBCLK <11,25,29,39>
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
FOX_AS0A626-UASN-7F_204P
@
A
Reverse Type
DDR3 SO-DIMM B
DDR_B_D4
DDR_B_D5
+
1
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
C188
0.1U_0402_16V4Z
1
C184
0.1U_0402_16V4Z
C183
2.2U_0603_6.3V4Z
DDR_B_D0
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C187
2.2U_0603_6.3V4Z
+VREF_DQB
B
C
D
Title
DDRIII-SODIMM1
Size
Document Number
Custom
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
E
12
of
59
4
3
CV10
2
1
CV11
2
1
1
2
2 0.1U_0402_16V4Z
CV12
1U_0402_6.3V4Z
D
50mA
100NH_LQW18ANR10J00D_5%_0603
1
2
+1.05VS_DGPU
LV2
1
CV7
1U_0402_6.3V4Z
+SP_PLLVDD
1
2
2
CV8
4.7U_0603_6.3V6K
Lane Reversal
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
C
Reserve 27MHZ Crystal at PVT
CV43
CV44
CV41
CV42
CV39
CV40
CV37
CV38
CV35
CV36
CV33
CV34
CV31
CV32
CV29
CV30
CV27
CV28
CV25
CV26
CV23
CV24
CV21
CV22
CV19
CV20
CV17
CV18
CV15
CV16
CV13
CV14
@
1
RV28
B
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
AL17
AM17
AM18
AM19
AL19
AK19
AL20
AM20
AM21
AM22
AL22
AK22
AL23
AM23
AM24
AM25
AL25
AK25
AL26
AM26
AM27
AM28
AL28
AK28
AK29
AL29
AM29
AM30
AM31
AM32
AN32
AP32
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#
AR16
AR17
AR13
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
AJ17
AJ18
@
1
2
RV16
200_0402_1%
Differential signal
2
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
<29> CLK_PCIE_VGA
<29> CLK_PCIE_VGA#
2
10M_0402_5%
YV1
XTALIN
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XTAL_OUT
27MHZ_16PF_X5H027000FG1H
@
1
CV45
20P_0402_50V8J
@
2
1
RV18
1
RV19
<32> PLTRST_VGA#
1
2
CV46
20P_0402_50V8J
@
PLTRST_VGA_R#
2
0_0402_5%
2
2.49K_0402_1%
+PLLVDD
Change YV1 to SJ100006R00 at pre-MP
1
RV26
10K_0402_5%
LVDS
VGA_EDID_CLK E3
VGA_EDID_DATA E4
2
G3
G2
VGA_CRT_CLK
G1
VGA_CRT_DATA G4
HDCP_SCL
HDCP_SDA
RV118
10K_0402_5%
OPT@
3
2N7002_SOT23-3
MIOA_HSYNC
MIOA_VSYNC
MIOB_HSYNC
MIOB_VSYNC
MIOA_DE
MIOA_CTL3
MIOA_VREF
MIOB_DE
MIOB_CTL3
MIOB_VREF
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
MIOA_CLKIN
MIOA_CLKOUT
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
MIOB_CLKIN
MIOB_CLKOUT
PEX_RST_N
PEX_TERMP
MIOA_CLKOUT_N
MIOB_CLKOUT_N
MIOACAL_PD_VDDQ
MIOACAL_PU_GND
PLLVDD
SP_PLLVDD
VID_PLLVDD
XTAL_IN
XTAL_OUT
MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND
XTAL_OUTBUFF
XTAL_SSIN
F6
G6
I2CS_SCL
I2CS_SDA
I2CC_SCL
I2CC_SDA
I2CB_SCL
I2CB_SDA
I2CA_SCL
I2CA_SDA
I2CH_SCL
I2CH_SDA
VGA_BL_PWM <25>
VGA_ENVDD <25>
VGA_ENBKL <25>
GPU_VID0 <56>
GPU_VID1 <56>
DACA_VDD
DACA_VREF
DACA_RSET
DACB_RED
DACB_GREEN
DACB_BLUE
DACB_HSYNC
DACB_VSYNC
DACB_VDD
DACB_VREF
DACB_RSET
PCIE_CTX_C_GRX_P[0..15]
<6> PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
THERM#_VGA <14>
TV1
TV6
D
VGA_HDMI_HPD
VGA_HDMI_HPD <27,33>
VGA_ENVDD
1 DIS@ 2
RV1
10K_0402_5%
2 DIS@ 1
RV2
10K_0402_5%
2 DIS@ 1
RV3
10K_0402_5%
VGA_ENBKL
VGA_BL_PWM
N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
+3VS_DGPU
VGA_EDID_CLK
1
2
2.2K_0402_5%
2
2.2K_0402_5%
RV6
VGA_EDID_DATA
1
RV7
SMB_CLK_GPU
RV9
1
2
2.2K_0402_5%
2
2.2K_0402_5%
THERM#_VGA
1
RV10
2
100K_0402_5%
HDCP_SCL
1
RV11
1
RV12
2
2.2K_0402_5%
2
2.2K_0402_5%
1
RV13
1
RV14
2
2.2K_0402_5%
2
2.2K_0402_5%
1
RV121
1
RV122
2
2.2K_0402_5%
2
2.2K_0402_5%
RV8
Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6
SMB_DATA_GPU
1
C
HDCP_SDA
VGA_CRT_DATA
N3
L3
VGA_CRT_CLK
W1
W2
I2CB_SCL
N2
P5
N5
I2CB_SDA
Y5
W3
AF1
N4
R4
1
RV15
2
10K_0402_5%
AE1
V4
1
RV17
2
10K_0402_5%
T4
W4
Change LV3 to always stuff
at pre-MP
120mA
+DACA_VDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z
U5
T5
1
AA7
AA6
2
1
CV81
DIS@
AM15
AM14
AL14
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
AM13
AL13
VGA_CRT_HSYNC
VGA_CRT_VSYNC
AJ12
AK12
AK13
+DACA_VDD
+DACA_VREF
DACA_RSET
2
1
CV73
DIS@
2
AK4
AL4
AJ4
2
0.1U_0402_16V4Z
1
CV48
DIS@
AG7 +DACB_VDD 2
RV31
AK6
AH7
2
1
CV80
DIS@
2
CV50
DIS@
B
MMZ1608D301BT_0603
1
2
+3VS_DGPU
LV3
1
1
CV51
CV49
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DIS@
DIS@
2
2
470P_0402_50V7K
VGA_CRT_R <26>
VGA_CRT_G <26>
VGA_CRT_B <26>
VGA_CRT_HSYNC <26>
VGA_CRT_VSYNC <26>
Close to GPU
VGA_CRT_R
1
RV27
124_0402_1%
DIS@
AM1
AM2
4700P_0402_25V7K
1
CV72
DIS@
2
VGA_CRT_G
CV47
0.1U_0402_16V4Z
DIS@
VGA_CRT_B
1 DIS@
RV20
1 DIS@
RV21
1 DIS@
RV23
2
150_0402_1%
2
150_0402_1%
2
150_0402_1%
1
10K_0402_5%
A
N11P-GE1-A3 BGA 969P
N11PR1@
2009/01/01
Issued Date
1
2
0_0402_5%
Compal Secret Data
RV123
10K_0402_5%
@
Deciphered Date
2010/01/01
Title
Size
Date:
5
PCIE_GTX_C_CRX_N[0..15]
<6> PCIE_GTX_C_CRX_N[0..15]
<6> PCIE_CTX_C_GRX_N[0..15]
THERM#_VGA
1U_0402_6.3V4Z
DACA_RED
DACA_GREEN
DACA_BLUE
PCIE_GTX_C_CRX_P[0..15]
<6> PCIE_GTX_C_CRX_P[0..15]
VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL
GPU_VID0
GPU_VID1
CLK_REQ_GPU#
DIS@
1
RV110
<26> VGA_CRT_CLK
<26> VGA_CRT_DATA
MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOBD_10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
2
D
CRT
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14
DACA_HSYNC
DACA_VSYNC
<25> VGA_EDID_CLK
<25> VGA_EDID_DATA
I2CB_SCL
I2CB_SDA
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
S
QV2
1
<29> CLK_REQ_VGA#
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
Part 1 of 7
1
2 1
G
A
D1
D2
SMB_CLK_GPU E2
SMB_DATA_GPU E1
2
RV124
10K_0402_5%
OPT@
Add Level Shifter for
CLK_REQ_VGA# at DVT
XTALOUT
1 XTALSSIN
10K_0402_5%
B1
B2
<14> SMB_CLK_GPU
<14> SMB_DATA_GPU
+3VS_DGPU
<33,46,56> DGPU_PWR_EN
XTALIN
XTAL_OUT
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
Internal Thermal Sensor
2
XTALSSIN
2
0_0402_5%
2 0_0402_5%
2
RV25
1
@
1
RV105
AF9
AD9
RV103
<25> 27M_CLK
<25> 27M_SSC
AM16
AG21
AE9
+SP_PLLVDD
1
1
CV9
4.7U_0603_6.3V6K
1
AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34
2
LV1
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
GPIO
+PLLVDD
PCI EXPRESS
DVO
+1.05VS_DGPU
150mA
0.1U_0402_16V4Z
2
DACs
1
CLK
Lane Reversal
100NH_LQW18ANR10J00D_5%_0603
2
UV1A
I2C
5
4
3
2
PCIE/DAC/GPIO
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
13
of
59
5
4
3
2
1
UV1D
Part 4 of 7
VGA_HDMI_TX2+
VGA_HDMI_TX2VGA_HDMI_TX1+
VGA_HDMI_TX1VGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_CLK+
VGA_HDMI_CLK-
<27> VGA_HDMI_TX2+
<27> VGA_HDMI_TX2<27> VGA_HDMI_TX1+
<27> VGA_HDMI_TX0<27> VGA_HDMI_CLK+
<27> VGA_HDMI_CLK-
B
AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
AL2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2
D35
P7
AD20
GND_SENSE_0
GND_SENSE_1
GND_SENSE_2
AD19
E35
R7
AP2
AN3
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
TEST
AP4
AN4
+3VS_DGPU
VGA_HDMI_CLK
2
4.7K_0402_5%
1
RV120
VGA_HDMI_DATA
2
4.7K_0402_5%
HDMI
VGA_HDMI_CLK
VGA_HDMI_DATA
<27> VGA_HDMI_CLK
<27> VGA_HDMI_DATA
AE4
AD4
AF3
AF2
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
GENERAL
A4
+3VS_DGPU
1
RV49
<24> STRAP0
<24> STRAP1
<24> STRAP2
2
10K_0402_5%
STRAP0
STRAP1
STRAP2
AB5
W5
W7
V7
NC/SPDIF
BUFRST_N
MULTI_STRAP_REF0_GND
CEC
MULTI_STRAP_REF1_GND
STRAP0
STRAP1
STRAP2
THERMDP
THERMDN
A
1
1
0.1U_0402_16V4Z
2
THERM_D+
CV54
2
3
2200P_0402_50V7K
4
1
THERM_D-
SCLK
8
VGA_SMB_CK2
D+
SDATA
7
VGA_SMB_DA2
D-
ALERT#
6
THERM#_VGA
GND
5
VDD
THERM#
+3VS_DGPU
2
2
+3VS_DGPU
RV24
2.2K_0402_5%
OPT@
VGA_SMB_CK2
OPT@
QV1B
3
4
2
VGA_SMB_DA2
5
RV22
2.2K_0402_5%
OPT@
OPT@
QV1A
1
C
EC_SMB_CK2 <29,43,44,45>
2N7002DW-T/R7_SOT363-6
6
EC_SMB_DA2 <29,43,44,45>
2N7002DW-T/R7_SOT363-6
VGA_SMB_CK2
VDD_SENSE
EC_SMB_CK2
1 DIS@ 2
RV35
0_0402_5%
EC_SMB_DA2
1 DIS@ 2
RV36
0_0402_5%
VDD_SENSE <56>
Reserve VBIOS ROM at PVT
AP35
AP14
AN14
AN16
AR14
AP16
1
RV41 @
B
+3VS_DGPU
TESTMODE
TV2
TV3
TV4
TV5
FLASH ROM
10K_0402_5%
RV47
2
10K_0402_5%
RV44
10K_0402_5%
@
C3
D3
C4
D4
ROM_CS#
ROM_SI
ROM_SO
ROM_SCLK
UV4
ROM_SI
5
ROM_SCLK
6
ROM_CS#
1
7
+3VS_DGPU
ROM_SI <24>
ROM_SO <24>
ROM_SCLK <24>
CV56
0.1U_0402_16V4Z
@
3
1
8
2
@
D
Q
ROM_SO
2
C
S
HOLD
W
VCC
VSS
4
M25P05-AVMN6TP SO 8P
A5
N9
M9
B5
B4
1
2
RV48
40.2K_0402_1%
1
2
RV50
40.2K_0402_1%
THERM_D+
THERM_D-
N11PR1@
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Size
Date:
4
THERM#_VGA <13>
ADM1032ARMZ-2REEL_MSOP8
5
1
1
Address: 0x9A H
UV2
2
CV53
D
2
+3VS_DGPU
SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
RV34
0_0402_5%
@
2
RV33
0_0402_5%
@
VGA_SMB_DA2
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
SMB_DATA_GPU <13>
2
1
RV119
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
SMB_CLK_GPU <13>
1
C
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
Internal Thermal Sensor
External VGA Thermal Sensor
1
AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
A2
A7
B7
C5
C7
D5
D6
D7
E5
E7
F4
G5
G11
G12
G14
G15
G27
G28
G24
G25
H32
J18
J19
J25
J26
L29
M7
M29
P6
P29
R29
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AD29
AE29
AF6
AG6
AG20
AG29
AH29
AJ5
AK15
AL7
1
AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
1
AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
2
<25> VGA_TZCLK+
<25> VGA_TZCLK<25> VGA_TZOUT0+
<25> VGA_TZOUT0<25> VGA_TZOUT1+
<25> VGA_TZOUT2-
VGA_TZCLK+
VGA_TZCLKVGA_TZOUT0+
VGA_TZOUT0VGA_TZOUT1+
VGA_TZOUT1VGA_TZOUT2+
VGA_TZOUT2-
D
AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11
NC
VGA_TXCLK+
VGA_TXCLKVGA_TXOUT0+
VGA_TXOUT0VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT2+
VGA_TXOUT2-
LVDS/TMDS
<25> VGA_TXCLK+
<25> VGA_TXCLK<25> VGA_TXOUT0+
<25> VGA_TXOUT0<25> VGA_TXOUT1+
<25> VGA_TXOUT2-
3
2
LVDS/HDMI/DP/THM
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
14
of
59
5
4
3
N11E-GE1-LP Performance Mode
Mode
D
NVCLK (MHz)
2
N11P-GE1 Performance Mode
MCLK (MHz)
+VGA_CORE
Mode
NVCLK (MHz)
1
N11M-GE1 & N11M-OP1 Performance Mode
MCLK (MHz)
+VGA_CORE
Mode
NVCLK (MHz)
MCLK (MHz)
+VGA_CORE
P0
450
790
0.90 V
P0
575
790
0.95 V
P0
625
790
1.03 V
P8
405
324
0.85 V
P8
405
324
0.85 V
P8
405
405
0.85 V
P12
135
135
0.80 V
P12
135
135
0.80 V
P12
135
135
0.85 V
+VGA_CORE
D
+VGA_CORE
UV1G
32A for N11E-GE1-LP
28A for N11P-GE1
16A for N11M-GE1 & N11M-OP1
Change CV57 and CV58
to OS-CON at PVT
1
CV57
330U_2.5V_M_R17
1
+
+ CV58
2
2
330U_2.5V_M_R17
+VGA_CORE
4.7U_0603_6.3V6K
1U_0402_6.3V4Z
4700P_0402_25V7K
C
CV59
10U_0603_6.3V6M
2
2
1
1
1
CV60
2
10U_0603_6.3V6M
1
CV61
@
1
CV212
2
CV62
CV63
CV64
2
4.7U_0603_6.3V6K
4700P_0402_25V7K
+VGA_CORE
0.047U_0402_25V6K
CV66
0.047U_0402_25V6K
1
1
2
2
1
CV67
0.022U_0402_25V7K
1
CV68
2
0.047U_0402_25V6K
CV69
2
1
CV70
2
0.022U_0402_25V7K
1
1
CV71
2
2
CV65
0.022U_0402_25V7K
0.022U_0402_25V7K
B
Add CV1 and CV2
+VGA_CORE
0.01U_0402_25V7K
CV74
0.01U_0402_25V7K
+VGA_CORE
N11PR1@
1
1
2
2
CV75
0.01U_0402_25V7K
1
2
CV76
0.01U_0402_25V7K
1
CV77
2
0.01U_0402_25V7K
1
2
CV78
0.22U_0402_6.3V6K
1
CV79
2
0.01U_0402_25V7K
CV1
1
P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24
CV2
2
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110
1
B
Part 7 of 7
2
C
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
POWER
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19
0.22U_0402_6.3V6K
A
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Size
Date:
5
4
3
2
VGA CORE
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
15
of
59
5
4
3
2
UV1E
3.5A
CV82
N11P@
4.7U_0603_6.3V6K
1
1
2
2
0.1U_0402_16V4Z
1
CV83
2
1
CV84
N11P@
2
1
CV85
N11P@
CV86
N11P@
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
D
0.047U_0402_25V6K
+VRAM_1.5VS
CV99
0.047U_0402_25V6K
1
1
2
1
CV100
2
CV101
2
0.01U_0402_25V7K
1
CV102
N11P@
2
0.047U_0402_25V6K
1
0.01U_0402_25V7K
1
CV103
2
CV104
2
0.01U_0402_25V7K
1
CV218
2
0.01U_0402_25V7K
Close to Pin
CV82
4.7U_0603_6.3V6K
N11E@
CV84
0.1U_0402_16V4Z
N11E@
CV85
0.1U_0402_16V4Z
N11E@
CV86
0.1U_0402_16V4Z
N11E@
Part 5 of 7
J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34
W 27
Y27
CV102
0.01U_0402_25V7K
N11E@
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
0.1U_0402_16V4Z
AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24
1
CV87
AK9
AJ11
IFPAB_PLLVDD
IFPAB_RSET
+IFPAB_IOVDD
AG9
AG10
IFPA_IOVDD
IFPB_IOVDD
500mA
1 +IFPC_IOVDD
10K_0402_5%
AJ8
IFPC_IOVDD
2
@
1
2 RV99
RV52
1K_0402_1%
2
RV97
1 +IFPD_PLLVDD
10K_0402_5%
AC6
AB6
IFPD_PLLVDD
IFPD_RSET
1 +IFPD_IOVDD
10K_0402_5%
AK8
IFPD_IOVDD
AJ6
AL1
IFPEF_PLLVDD
IFPEF_RSET
AE7
AD7
IFPE_IOVDD
IFPF_IOVDD
2
1K_0402_1%
PEX_SVDD_3V3_0
PEX_SVDD_3V3_1
1
2
200mA
1
CV117
4.7U_0603_6.3V6K
DIS@
2
1
CV118
DIS@
4.7U_0603_6.3V6K
2
1
CV119
DIS@
2
1
CV120
DIS@
2
IFPC_PLLVDD
IFPC_RSET
0.1U_0402_16V4Z
+3VS_DGPU
+1.8VS
A
LV8
0.1U_0402_16V4Z
2
1 4.7U_0603_6.3V6K
BLM18PG181SN1D_0603
DIS@
1
1
1
1
CV132
CV134
4.7U_0603_6.3V6K
CV133
CV135
DIS@
DIS@
DIS@
DIS@
2
2
2
2
285mA
1
CV4
CV98
2
2
2
22U_0805_6.3V6M
4.7U_0603_6.3V6K
1U_0402_6.3V4Z
1
CV105
@
2
1
CV107
CV106
@
2
100NH_LQW18ANR10J00D_5%_0603
1
2
+1.05VS_DGPU
LV4
1
1
CV109
CV108
4.7U_0603_6.3V6K
2 4.7U_0603_6.3V6K
2
C
120mA
MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
AA9
AB9
W9
Y9
1
1
2
CV111
0.1U_0402_16V4Z
2 @
CV110
120mA
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
1
CV217
1
CV216
2
1
2
1
CV113
CV112
2
2
CV114
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
+3VS_DGPU
240mA
CV115
1
1
2
2
CV116
0.1U_0402_16V4Z
N11PR1@
B
CV131 IHDMI@
10K_0402_5%
200mA
CV127
4.7U_0603_6.3V6K
DHDMI@
1U_0402_6.3V4Z
1
2
0.1U_0402_16V4Z
1
CV128
DHDMI@
2
1
CV129
DHDMI@
2
+IFPEF_PLLVDD
1
CV130
DHDMI@
2
1
CV131
DHDMI@
2
CV215
0.1U_0402_16V4Z
DHDMI@
0.1U_0402_16V4Z
285mA
+IFPE_IOVDD
1
2
CV145
0.1U_0402_16V4Z
DHDMI@
A
+IFPAB_IOVDD
CV143 IHDMI@
10K_0402_5%
1U_0402_6.3V4Z
1
2
CV213
0.1U_0402_16V4Z
DIS@
Compal Secret Data
2009/01/01
Issued Date
1U_0402_6.3V4Z
Deciphered Date
2010/01/01
Title
Size
CV213 OPT@
10K_0402_5%
Date:
5
1
CV97
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P9
R9
T9
U9
+1.05VS_DGPU
LV10
2
1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
BLM18PG181SN1D_0603
DHDMI@
1
1
1
1
CV141
CV143
4.7U_0603_6.3V6K
CV142
CV144
DHDMI@
DHDMI@ DHDMI@
DHDMI@
2
2
2
2
+IFPAB_IOVDD
2
1
BLM18PG181SN1D_0603
@
D
+1.05VS_DGPU
+PEX_PLLVDD
J10
J11
J12
J13
J9
MIOA_VDDQ_0
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
4.7U_0603_6.3V6K
LV9
22U_0805_6.3V6M
Add CV3 and CV4
1
2
1U_0402_6.3V4Z
2
LV7
2
1
BLM18PG181SN1D_0603
DHDMI@
2
2
Close to Pin
+3VS_DGPU
1
CV121
0.1U_0402_16V4Z
@
2
10U_0603_6.3V6M
CV96
2
120mA
AG19
F7
CV3
CV92
2
1
CV95
2
0.1U_0402_16V4Z
CV91
+1.05VS_DGPU
1
4.7U_0603_6.3V6K
1
CV94
2
1
1U_0402_6.3V4Z
1
CV93
2
PEX_PLLVDD
B
+IFPAB_PLLVDD
1U_0402_6.3V4Z
1
0.1U_0402_16V4Z
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z
1
AG14
CV90
2
0.1U_0402_16V4Z
AK16
AK17
AK21
AK24
AK27
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
AJ9
AK7
+IFPE_IOVDD
LV5
2
1
BLM18PG181SN1D_0603
DIS@
CV89
CV88
2
10U_0603_6.3V6M
1
+3VS_DGPU
+IFPEF_PLLVDD
+1.05VS_DGPU
1
+3VS_DGPU
+IFPAB_PLLVDD
1 +IFPC_PLLVDD
10K_0402_5%
CV120 OPT@
10K_0402_5%
1
0.1U_0402_16V4Z
110mA
2
@
1
2 RV107
RV51
1K_0402_1%
2
RV109
1
RV53
1U_0402_6.3V4Z
1
2
C
@
1
2
RV96
1K_0402_1%
Close to Pin
2000mA
1600mA
POWER
4.7U_0603_6.3V6K
+VRAM_1.5VS
1
4
3
2
POWER
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
16
of
59
5
4
3
2
1
UV1F
D
C
B
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
Part 6 of 7
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND
B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F31
F34
F5
J2
J5
J31
J34
K9
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16
V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33
D
C
B
A
A
N11PR1@
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Size
Date:
5
4
3
2
GND
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
17
of
59
5
4
3
2
1
UV1B
Part 2 of 7
MDA[0..63]
<20,21> MDA[0..63]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
C
1
+VRAM_1.5VS
RV55
1.1K_0402_1%
@
+FB_VREF
1
2
12mil
1
RV56
1.1K_0402_1%
@
2
2
B
CV146
0.01U_0402_25V7K
@
+1.05VS_DGPU
CV147
4.7U_0603_6.3V6K
1
2
MMZ1608D301BT_0603
1
2
LV11
1
CV148
4.7U_0603_6.3V6K
2
20 mil
1U_0402_6.3V4Z
1
2
CV149
1
+FB_AVDD
CV150
@
2
1U_0402_6.3V4Z
+FB_VREF
+VRAM_1.5VS
2
RV57
1
10K_0402_5%
L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
AG27
AF27
FB_DLLAVDD
FB_PLLAVDD
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
MEMORY INTERFACE
A
D
J27
FB_VREF
T30
FBA_DEBUG
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29
P32
H34
J30
P30
AF32
AL32
AL34
AF35
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
L35
G35
H31
N32
AD32
AJ31
AJ35
AC34
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
L34
H35
J32
N31
AE31
AJ32
AJ34
AC33
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
<20>
<20,21>
<20>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<21>
<20,21>
<20,21>
<20,21>
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
<21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
<20,21>
<20>
<20,21>
<21>
<20,21>
<20,21>
<20,21>
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
DQMA[7..0]
CLKA0
CLKA0#
FBA_CLK1
FBA_CLK1_N
AC31
AC30
CLKA1
CLKA1#
0..31
CMD0
CKE_L
CMD1
CMD2
32..63
A8
A8
CS0#_L
CMD3
A7
A6
CMD4
A2
A1
CMD5
A11
A9
CMD6
A5
A4
CMD7
A0
A12
CMD8
CAS#
CAS#
CMD9
BA1
A3
CMD10
A9
A11
<20,21>
DQSA#[7..0]
DQSA[7..0]
<20,21>
<20,21>
CMD12
BA0
CMD13
BA2
A15
CMD14
A3
BA1
BA0
CS1#_H
ODT_H
CMD17
A4
CMD18
A13
A5
A14
CMD19
WE#
A10
CMD20
A1
A2
CMD21
A10
WE#
CMD22
A12
A0
CMD23
CS1#_L
CMD24
RAS#
CMD25
ODT_L
CMD26
A6
B
RAS#
A7
CMD27
CLKA0 <20>
CLKA0# <20>
C
CS0#_H
CMD11
CMD15
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
T32
T31
DATA Bus
Address
CMD16
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
FBA_CLK0
FBA_CLK0_N
D
Mode C - Mirror Mode Mapping
CKE_H
CMD28
RST
RST
CMD29
A14
A13
CMD30
A15
BA2
CLKA1 <21>
CLKA1# <21>
N11PR1@
A
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Size
Date:
5
4
3
2
MEM Interface A
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
18
of
59
5
4
3
2
1
UV1C
MDB[0..63]
D
C
B
+VRAM_1.5VS
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25
2
40.2_0402_1%
1
2
RV59
40.2_0402_1%
1 N11P@ 2
RV60
40.2_0402_1%
RV58
1
K27
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
MEMORY INTERFACE C
Part 3 of 7
<22,23> MDB[0..63]
FBCAL_PD_VDDQ
L27
FBCAL_PU_GND
M27
FBCAL_TERM_GND
CMDB0
CMDB1
CMDB2
CMDB3
CMDB4
CMDB5
CMDB6
CMDB7
CMDB8
CMDB9
CMDB10
CMDB11
CMDB12
CMDB13
CMDB14
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
C17
B19
D18
F21
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
A16
D10
F11
D15
D27
D34
A34
D28
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
B14
B10
D9
E14
F26
D31
A31
A26
DQSB#0
DQSB#1
DQSB#2
DQSB#3
DQSB#4
DQSB#5
DQSB#6
DQSB#7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
C14
A10
E10
D14
E26
D32
A32
B26
CMDB16
CMDB17
CMDB18
CMDB19
CMDB20
CMDB21
CMDB22
CMDB24
CMDB25
CMDB26
CMDB27
CMDB28
CMDB29
CMDB30
CMDB0
CMDB1
CMDB2
CMDB3
CMDB4
CMDB5
CMDB6
CMDB7
CMDB8
CMDB9
CMDB10
CMDB11
CMDB12
CMDB13
CMDB14
<22>
<22,23>
<22>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<23>
<22,23>
<22,23>
<22,23>
CMDB16
CMDB17
CMDB18
CMDB19
CMDB20
CMDB21
CMDB22
<23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
CMDB24
CMDB25
CMDB26
CMDB27
CMDB28
CMDB29
CMDB30
<22,23>
<22>
<22,23>
<23>
<22,23>
<22,23>
<22,23>
DATA Bus
Address
0..31
CMD0
CKE_L
A8
CMD1
CMD2
A8
CS0#_L
CMD3
A7
A6
CMD4
A2
A1
CMD5
A11
A9
CMD6
A5
A4
CMD7
A0
A12
CMD8
CAS#
CAS#
CMD9
BA1
A3
CMD10
A9
A11
CS0#_H
CMD11
DQMB[7..0]
<22,23>
CMD12
BA0
CMD13
BA2
A15
CMD14
A3
BA1
CMD15
DQSB0
DQSB1
DQSB2
DQSB3
DQSB4
DQSB5
DQSB6
DQSB7
DQSB[7..0]
<22,23>
<22,23>
ODT_H
CMD17
A4
CMD18
A13
A5
A14
CMD19
WE#
A10
CMD20
A1
A2
CMD21
A10
WE#
CMD22
A12
A0
CMD23
CS1#_L
CMD24
RAS#
CMD25
ODT_L
CMD26
A6
E17
D17
CLKB0
CLKB0#
FBC_CLK1
FBC_CLK1_N
D23
E23
CLKB1
CLKB1#
FBC_DEBUG
G19
1 N11P@ 2
10K_0402_5%
RV61
CLKB0 <22>
CLKB0# <22>
CLKB1 <23>
CLKB1# <23>
RAS#
B
A7
CMD27
FBC_CLK0
FBC_CLK0_N
C
BA0
CS1#_H
CMD16
DQSB#[7..0]
D
32..63
CKE_H
CMD28
RST
RST
CMD29
A14
A13
CMD30
A15
BA2
+VRAM_1.5VS
RV60 N11MGE@
60.4_0402_1%
N11PR1@
RV60 N11MOP@
60.4_0402_1%
RV61 N11E@
10K_0402_5%
RV60 N11E@
40.2_0402_1%
A
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Size
Date:
5
4
3
2
MEM Interface C
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
19
of
59
5
4
3
2
1
MDA[0..63]
Memory Partition A - Lower 32 bits
UV5
+VRAM_1.5VS
1
+FBA_VREF0
D
RV62
2
1.1K_0402_1%
1
+FBA_VREF0
1
RV63
2
1.1K_0402_1%
CV151
0.01U_0402_25V7K
2
VREFCA
VREFDQ
CMDA7
CMDA20
CMDA4
CMDA14
CMDA17
CMDA6
CMDA26
CMDA3
CMDA1
CMDA10
CMDA21
CMDA5
CMDA22
CMDA18
CMDA29
CMDA30
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDA12
CMDA9
CMDA13
M2
N8
M3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA1
MDA5
MDA0
MDA3
MDA4
MDA7
MDA2
MDA6
RV64
243_0402_1%
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA29
MDA26
MDA30
MDA24
MDA27
MDA25
MDA31
MDA28
VREFCA
VREFDQ
CMDA7
CMDA20
CMDA4
CMDA14
CMDA17
CMDA6
CMDA26
CMDA3
CMDA1
CMDA10
CMDA21
CMDA5
CMDA22
CMDA18
CMDA29
CMDA30
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA12
CMDA9
CMDA13
M2
N8
M3
CLKA0
CLKA0#
CMDA0
J7
K7
K9
CLKA0
CLKA0#
CMDA0
J7
K7
K9
CMDA25
CMDA2
CMDA24
CMDA8
CMDA19
K1
L2
J3
K3
L3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDA25
CMDA2
CMDA24
CMDA8
CMDA19
K1
L2
J3
K3
L3
DQSA2
DQSA1
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA2
DQMA1
E7
D3
DML
DMU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Group0
Group3
+VRAM_1.5VS
BA0
BA1
BA2
CK
CK
CKE/CKE0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA22
MDA19
MDA23
MDA16
MDA20
MDA18
MDA21
MDA17
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA14
MDA9
MDA12
MDA11
MDA13
MDA8
MDA15
MDA10
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
CK
CK
CKE/CKE0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
<18,21>
DQSA[7..0]
<18,21>
DQSA#[7..0]
<18,21>
Group2
D
Mode C - Mirror
Mode Mapping
DATA Bus
Group1
+VRAM_1.5VS
BA0
BA1
BA2
<18,21>
DQMA[7..0]
Address
0..31
CMD0
CKE_L
A8
CMD1
CMD2
32..63
A8
CS0#_L
CMD3
A7
A6
CMD4
A2
A1
CMD5
A11
A9
CMD6
A5
A4
CMD7
A0
A12
CMD8
CAS#
CAS#
CMD9
BA1
A3
CMD10
A9
C
1
F3
C7
DQSL
DQSU
DQMA0
DQMA3
E7
D3
DML
DMU
DQSA#0
DQSA#3
CMDA28
G3
B7
T2
RESET
CMDA28
J1
L1
J9
L9
RV66
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
2
10K_0402_5%
T2
L8
DQSL
DQSU
RESET
ZQ/ZQ0
J1
L1
J9
L9
RV67
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
RV65
1
B
G3
B7
CMDA0
96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@
A11
CMD11
RV98
10K_0402_5%
RV102
10K_0402_5%
CS0#_H
CMD12
BA0
CMD13
BA2
BA0
A15
CMD14
A3
BA1
CMD15
CS1#_H
CMD16
1
ZQ/ZQ0
DQSA#2
DQSA#1
1
L8
DQSL
DQSU
CMDA25
2
DQSA0
DQSA3
ODT/ODT0
CS/CS0
RAS
CAS
WE
1
ODT/ODT0
CS/CS0
RAS
CAS
WE
2
CLKA0#
1
C
<18> CLKA0
<18> CLKA0#
+FBA_VREF0
M8
H1
2
CLKA0
UV6
M8
H1
<18,21>
CMDA[30..0]
96-BALL
SDRAM DDR3
@
ODT_H
CMD17
A4
CMD18
A13
A14
CMD19
WE#
A10
CMD20
A1
A2
CMD21
A10
WE#
CMD22
A12
A0
CMD23
CS1#_L
CMD24
RAS#
CMD25
ODT_L
CMD26
A6
A5
RAS#
A7
CMD27
+VRAM_1.5VS
+VRAM_1.5VS
1U_0402_6.3V4Z
1
CV152
1
2
2
1U_0402_6.3V4Z
CV153
0.1U_0402_16V4Z
1
CV154
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV155
CV156
1
2
2
0.1U_0402_16V4Z
CV157
1U_0402_6.3V4Z
1
1
CV158
2
0.1U_0402_16V4Z
CV159
1
2
2
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
CV160
CV161
1
2
2
0.1U_0402_16V4Z
CV162
0.1U_0402_16V4Z
1
CV163
1
2
2
0.1U_0402_16V4Z
CV164
1
CV165
B
CKE_H
CMD28
RST
RST
CMD29
A14
A13
CMD30
A15
BA2
2
0.1U_0402_16V4Z
A
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Size
Date:
5
4
3
2
VRAM A Lower
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
20
of
59
5
4
3
2
1
Memory Partition A - Upper 32 bits
MDA[0..63]
UV8
+VRAM_1.5VS
+FBA_VREF1
M8
H1
VREFCA
VREFDQ
CMDA22
CMDA4
CMDA20
CMDA9
CMDA6
CMDA17
CMDA3
CMDA26
CMDA1
CMDA5
CMDA19
CMDA10
CMDA7
CMDA29
CMDA18
CMDA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDA12
CMDA14
CMDA30
M2
N8
M3
1
RV68
D
2
1.1K_0402_1%
1
+FBA_VREF1
1
RV69
1.1K_0402_1%
CV166
0.01U_0402_25V7K
2
2
RV70
243_0402_1%
CLKA1
CLKA1#
CMDA27
J7
K7
K9
CMDA16
CMDA11
CMDA24
CMDA8
CMDA21
K1
L2
J3
K3
L3
MDA38
MDA33
MDA39
MDA32
MDA37
MDA34
MDA36
MDA35
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA45
MDA41
MDA42
MDA44
MDA43
MDA46
MDA40
MDA47
+FBA_VREF1
M8
H1
VREFCA
VREFDQ
CMDA22
CMDA4
CMDA20
CMDA9
CMDA6
CMDA17
CMDA3
CMDA26
CMDA1
CMDA5
CMDA19
CMDA10
CMDA7
CMDA29
CMDA18
CMDA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA12
CMDA14
CMDA30
M2
N8
M3
CLKA1
CLKA1#
CMDA27
J7
K7
K9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDA16
CMDA11
CMDA24
CMDA8
CMDA21
K1
L2
J3
K3
L3
DQSA7
DQSA6
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA7
DQMA6
E7
D3
DML
DMU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Group4
Group5
BA0
BA1
BA2
CK
CK
CKE/CKE0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA51
MDA52
MDA48
MDA53
MDA49
MDA54
MDA50
MDA55
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Group7
CK
CK
CKE/CKE0
<18,20>
DQMA[7..0]
<18,20>
DQSA[7..0]
<18,20>
DQSA#[7..0]
<18,20>
D
DATA Bus
Group6
+VRAM_1.5VS
BA0
BA1
BA2
<18,20>
CMDA[30..0]
Address
0..31
CMD0
CKE_L
CMD1
CMD2
32..63
A8
A8
CS0#_L
CMD3
A7
A6
CMD4
A2
A1
CMD5
A11
A9
CMD6
A5
A4
CMD7
A0
A12
CMD8
CAS#
CAS#
CMD9
BA1
A3
CMD10
A9
C
1
C
<18> CLKA1
<18> CLKA1#
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
+VRAM_1.5VS
2
CLKA1
UV7
CLKA1#
CMDA27
DQSA4
DQSA5
F3
C7
DQSL
DQSU
DQMA4
DQMA5
E7
D3
DML
DMU
G3
B7
DQSL
DQSU
2
DQSA#4
DQSA#5
2
CMDA16
ODT/ODT0
CS/CS0
RAS
CAS
WE
RV100
10K_0402_5%
RV104
10K_0402_5%
CMDA28
T2
ZQ/ZQ0
G3
B7
CMDA28
T2
L8
DQSL
DQSU
RESET
ZQ/ZQ0
2
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
J1
L1
J9
L9
RV72
243_0402_1%
96-BALL
SDRAM DDR3
@
CV167
1
2
2
1U_0402_6.3V4Z
CV168
0.1U_0402_16V4Z
1
CV169
1
CV170
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV171
1
2
2
0.1U_0402_16V4Z
CV172
1U_0402_6.3V4Z
1
1
CV173
2
CV174
1
2
2
1U_0402_6.3V4Z
0.1U_0402_16V4Z
BA0
CMD13
BA2
BA0
A15
CMD14
A3
BA1
CS1#_H
ODT_H
CMD17
A4
CMD18
A13
A14
CMD19
WE#
A10
CMD20
A1
A2
CMD21
A10
WE#
CMD22
A12
A0
CMD23
CS1#_L
CMD24
RAS#
CMD25
ODT_L
CMD26
A6
A5
CV175
0.1U_0402_16V4Z
1
CV176
1
2
2
0.1U_0402_16V4Z
CV177
0.1U_0402_16V4Z
1
CV178
1
2
2
0.1U_0402_16V4Z
CV179
1
CV180
B
RAS#
A7
CMD27
+VRAM_1.5VS
1U_0402_6.3V4Z
CMD12
CMD15
96-BALL
SDRAM DDR3
@
+VRAM_1.5VS
1
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
J1
L1
J9
L9
RV71
243_0402_1%
CS0#_H
CMD16
1
1
B
A11
CMD11
1
1
L8
RESET
DQSA#7
DQSA#6
ODT/ODT0
CS/CS0
RAS
CAS
WE
CKE_H
CMD28
RST
RST
CMD29
A14
A13
CMD30
A15
BA2
2
0.1U_0402_16V4Z
A
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Size
Date:
5
4
3
2
VRAM A Upper
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
21
of
59
5
4
3
2
1
MDB[0..63]
Memory Partition C - Lower 32 bits
+VRAM_1.5VS
UV9
1
+FBB_VREF0
RV73
CMDB7
CMDB20
CMDB4
CMDB14
CMDB17
CMDB6
CMDB26
CMDB3
CMDB1
CMDB10
CMDB21
CMDB5
CMDB22
CMDB18
CMDB29
CMDB30
+FBB_VREF0
1
1.1K_0402_1%
8PCS@
2
D
1
RV74
2
2
1.1K_0402_1%
8PCS@
CV181
0.01U_0402_25V7K
8PCS@
CMDB12
CMDB9
CMDB13
M8
H1
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB3
MDB5
MDB2
MDB4
MDB1
MDB6
MDB0
MDB7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB31
MDB25
MDB29
MDB24
MDB28
MDB26
MDB30
MDB27
RV75
243_0402_1%
8PCS@
CMDB7
CMDB20
CMDB4
CMDB14
CMDB17
CMDB6
CMDB26
CMDB3
CMDB1
CMDB10
CMDB21
CMDB5
CMDB22
CMDB18
CMDB29
CMDB30
Group0
Group3
J7
K7
K9
CK
CK
CKE/CKE0
CMDB25
CMDB2
CMDB24
CMDB8
CMDB19
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDB12
CMDB9
CMDB13
CLKB0
CLKB0#
CMDB0
J7
K7
K9
CK
CK
CKE/CKE0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDB25
CMDB2
CMDB24
CMDB8
CMDB19
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
M2
N8
M3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB16
MDB17
MDB19
MDB18
MDB20
MDB21
MDB22
MDB23
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB13
MDB9
MDB14
MDB11
MDB12
MDB8
MDB15
MDB10
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
BA0
BA1
BA2
<19,23>
DQSB[7..0]
<19,23>
DQSB#[7..0]
<19,23>
D
Group2
Mode C - Mirror
Mode Mapping
DATA Bus
Group1
Address
0..31
CMD0
CKE_L
CMD1
+VRAM_1.5VS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BA0
BA1
BA2
CLKB0
CLKB0#
CMDB0
M8
H1
<19,23>
DQMB[7..0]
CMD2
32..63
A8
A8
CS0#_L
CMD3
A7
A6
CMD4
A2
A1
CMD5
A11
A9
CMD6
A5
A4
CMD7
A0
A12
CMD8
CAS#
CAS#
CMD9
BA1
A3
CMD10
A9
C
1
C
<19> CLKB0
<19> CLKB0#
+FBB_VREF0
+VRAM_1.5VS
2
CLKB0
UV10
<19,23>
CMDB[30..0]
CLKB0#
DQSB0
DQSB3
F3
C7
DQSL
DQSU
DQSB2
DQSB1
F3
C7
DQSL
DQSU
CMDB25
G3
B7
DQSL
DQSU
CMDB28
T2
L8
RESET
ZQ/ZQ0
E7
D3
DML
DMU
DQSB#2
DQSB#1
G3
B7
DQSL
DQSU
CMDB28
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
RV106
10K_0402_5%
8PCS@
RV111
10K_0402_5%
8PCS@
2
RV78
243_0402_1%
8PCS@
2
8PCS@
8PCS@
1
1
RV77
243_0402_1%
2
1
RV76
10K_0402_5%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
96-BALL
SDRAM DDR3
@
96-BALL
SDRAM DDR3
@
+VRAM_1.5VS
CV182
1
CV183
0.1U_0402_16V4Z
1
CV184
1
CV185
0.1U_0402_16V4Z
1
CV186
1
CV187
1U_0402_6.3V4Z
1
CV188
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
0.1U_0402_16V4Z
2
2
2
2
2
2
2 8PCS@
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A
1
CV189
1
CV190
0.1U_0402_16V4Z
1
CV191
1
CV192
0.1U_0402_16V4Z
1
CV193
1
CV194
1
A15
CMD14
A3
BA1
CS1#_H
ODT_H
CMD17
A4
CMD18
A13
A5
A14
CMD19
WE#
A10
CMD20
A1
A2
CMD21
A10
WE#
CMD22
A12
A0
CMD23
CS1#_L
CMD24
RAS#
CMD25
ODT_L
CMD26
A6
B
RAS#
A7
CKE_H
CMD28
RST
RST
CMD29
A14
A13
CMD30
A15
BA2
CV195
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Custom
Date:
4
BA0
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
0.1U_0402_16V4Z
2
2
2
2
2
2
2 8PCS@
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
BA2
CMD27
+VRAM_1.5VS
1U_0402_6.3V4Z
1
BA0
CMD13
CMD16
B
J1
L1
J9
L9
CMD12
CMD15
2
DQSB#0
DQSB#3
DQMB2
DQMB1
CS0#_H
1
DML
DMU
1
E7
D3
2
CMDB0
DQMB0
DQMB3
A11
CMD11
3
2
VRAM C Lower
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
22
of
59
5
4
3
2
1
Memory Partition C - Upper 32 bits
MDB[0..63]
UV11
+VRAM_1.5VS
1
CMDB22
CMDB4
CMDB20
CMDB9
CMDB6
CMDB17
CMDB3
CMDB26
CMDB1
CMDB5
CMDB19
CMDB10
CMDB7
CMDB29
CMDB18
CMDB13
2
RV79
+FBB_VREF1
1
1.1K_0402_1%
8PCS@
1
1.1K_0402_1%
8PCS@
2
RV80
2
M8
H1
CV196
0.01U_0402_25V7K
8PCS@
CMDB12
CMDB14
CMDB30
2
1
C
CLKB1
CLKB1#
CMDB27
<19> CLKB1
<19> CLKB1#
DQSB4
DQSB5
DQSL
DQSU
DQMB4
DQMB5
E7
D3
DML
DMU
DQSB#4
DQSB#5
G3
B7
DQSL
DQSU
2
2
ODT/ODT0
CS/CS0
RAS
CAS
WE
F3
C7
CMDB27
CMDB16
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
RV112
10K_0402_5%
8PCS@
CMDB28
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB41
MDB46
MDB42
MDB47
MDB44
MDB45
MDB40
MDB43
+FBB_VREF1
CMDB22
CMDB4
CMDB20
CMDB9
CMDB6
CMDB17
CMDB3
CMDB26
CMDB1
CMDB5
CMDB19
CMDB10
CMDB7
CMDB29
CMDB18
CMDB13
Group4
Group5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
M8
H1
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB63
MDB57
MDB61
MDB59
MDB60
MDB56
MDB62
MDB58
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB48
MDB55
MDB49
MDB52
MDB51
MDB54
MDB50
MDB53
M2
N8
M3
CLKB1
CLKB1#
CMDB27
J7
K7
K9
CMDB16
CMDB11
CMDB24
CMDB8
CMDB21
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
DQSB7
DQSB6
ODT/ODT0
CS/CS0
RAS
CAS
WE
F3
C7
DQSL
DQSU
DQMB7
DQMB6
E7
D3
DML
DMU
DQSB#7
DQSB#6
G3
B7
DQSL
DQSU
CMDB28
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
<19,22>
DQSB[7..0]
<19,22>
DQSB#[7..0]
<19,22>
DATA Bus
Group6
Address
0..31
CMD0
CKE_L
CMD1
+VRAM_1.5VS
BA0
BA1
BA2
<19,22>
DQMB[7..0]
D
Group7
CMD2
CMDB12
CMDB14
CMDB30
<19,22>
CMDB[30..0]
32..63
A8
A8
CS0#_L
CMD3
A7
A6
CMD4
A2
A1
CMD5
A11
A9
CMD6
A5
A4
CMD7
A0
A12
CMD8
CAS#
CAS#
CMD9
BA1
A3
CMD10
A9
C
A11
CMD11
CS0#_H
CMD12
BA0
CMD13
BA2
BA0
A15
CMD14
A3
BA1
CMD15
CS1#_H
CMD16
ODT_H
CMD17
A4
CMD18
A13
A5
A14
CMD19
WE#
A10
CMD20
A1
A2
CMD21
A10
WE#
CMD22
A12
A0
CMD23
CS1#_L
1
B
1
1
1
RV108
10K_0402_5%
8PCS@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
MDB37
MDB35
MDB36
MDB34
MDB38
MDB32
MDB39
MDB33
+VRAM_1.5VS
BA0
BA1
BA2
J7
K7
K9
CMDB16
CMDB11
CMDB24
CMDB8
CMDB21
CLKB1#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
CLKB1
RV81
243_0402_1%
8PCS@
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
E3
F7
F2
F8
H3
H8
G2
H7
8PCS@
2
RV82
243_0402_1%
RV83
243_0402_1%
8PCS@
2
D
+FBB_VREF1
UV12
96-BALL
SDRAM DDR3
@
96-BALL
SDRAM DDR3
@
+VRAM_1.5VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
+
2
CV122
390U_2.5V_M_R10
8PCS@
0.1U_0402_16V4Z
CV198
1
1
CV199
CV200
1
CV201
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
0.1U_0402_16V4Z
1
CV202
1
CV203
1
CV205
1
CV206
1
CV207
1
CV208
1
RAS#
CMD25
ODT_L
CMD26
A6
RAS#
A7
CMD27
+VRAM_1.5VS
+VRAM_1.5VS
CMD24
1
CV209
CV210
1
CV211
B
CKE_H
CMD28
RST
RST
CMD29
A14
A13
CMD30
A15
BA2
CV204
8PCS@
2
2
1U_0402_6.3V4Z
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
8PCS@
0.1U_0402_16V4Z
2
2
2
2
2
2
2 8PCS@
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
8PCS@
8PCS@
2
2
0.1U_0402_16V4Z
8PCS@
8PCS@
2
2
0.1U_0402_16V4Z
8PCS@
0.1U_0402_16V4Z
2 8PCS@
A
A
Compal Secret Data
2009/01/01
Issued Date
Deciphered Date
2010/01/01
Title
Custom
Date:
5
4
3
2
VRAM C Upper
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
23
of
59
5
4
3
RV86
10K_0402_1%
N11P@
1
1
D
RV85
34.8K_0402_1%
1
RV87
45.3K_0402_1%
2
2
2
+3VS_DGPU
2
RV88
34.8K_0402_1%
@
1
1
RV84
45.3K_0402_1%
@
RV89
30K_0402_1%
N11MGE@
1
2
2
STRAP0
STRAP1
STRAP2
<14> STRAP0
<14> STRAP1
<14> STRAP2
2
Power Rail
Logical
Strapping Bit3
+3VS_DGPU
XCLK_417
ROM_SCLK
+3VS_DGPU
ROM_SI
+3VS_DGPU
STRAP2
+3VS_DGPU
PCI_DEVID[3]
STRAP1
+3VS_DGPU
3GIO_PADCFG[3]
3GIO_PADCFG[2]
3GIO_PADCFG[1]
3GIO_PADCFG[0]
STRAP0
+3VS_DGPU
USER[3]
USER[2]
USER[1]
USER[0]
RV89
4.99K_0402_1%
N11E@
Resistor Values
RV89
15K_0402_1%
N11MOP@
RV92
15K_0402_1%
N11MGE@
1
RV91
4.99K_0402_1%
@
1
1
RV90
4.99K_0402_1%
@
2
2
2
+3VS_DGPU
C
Logical
Strapping Bit2
FB_0_BAR_SIZE
Logical
Strapping Bit1
SMB_ALT_ADDR
Logical
Strapping Bit0
VGA_DEVICE
PCI_DEVID[4]
SUB_VENDOR
SLOT_CLK_CFG
PEX_PLLEN_TERM
RAMCFG[3]
RAMCFG[2]
RAMCFG[1]
RAMCFG[0]
PCI_DEVID[2]
PCI_DEVID[1]
PCI_DEVID[0]
Pull-up to +3VS
1000
0000
10K
1001
0001
15K
1010
0010
20K
1011
0011
25K
1100
0100
30K
1101
0101
35K
1110
0110
45K
1111
0111
RV92
15K_0402_1%
N11E@
C
RV92
15K_0402_1%
N11MOP@
2
2
2
RV93
15K_0402_1%
@
RV94
10K_0402_1%
RV95
15K_0402_1%
N11P@
SUB_VENDOR
XCLK_417
0
No VBIOS ROM (Default)
0
277MHz (Default)
1
BIOS ROM is present
1
Reserved
1
1
1
X76
D
Pull-down to Gnd
5K
ROM_SI
ROM_SO
ROM_SCLK
<14> ROM_SI
<14> ROM_SO
<14> ROM_SCLK
1
Physical
Strapping pin
ROM_SO
DeviceID
ROM_SCLK
STRAP2
FB_0_BAR_SIZE
USER Straps
N11M-GE1
0xA75
Pull up 15K
Pull down 30K
0
256MB (Default)
User[3:0]
N11P-GE1
0xA29
Pull down 15K
Pull up 10K
1
Reserved
1000-1100
N11M-OP1
0xA72
Pull up 15K
Pull down 15K
0xCB0
Pull up 15K
Pull down 5K
Customer defined
B
B
N11E-GE1(LP)
3GIO_PADCFG
PEX_PLL_EN_TERM
3GIO_PADCFG[3:0]
0
Disable (Default)
1
Enable
1110
Hynix
H5TQ1G63BFR-12C
SA000032400
Samsung K4W1G1646E-HC12
SA000035700
512M
0010
PD 15K
1G
0010
PD 15K
512M
0011
PD 20K
SLOT_CLOCK_CFG
SD034150280
SD034200280
1G
0011
Notebook Default
0
GPU and MCH don't share a common reference clock
1
GPU and MCH share a common reference clock (Default)
SMBUS_ALT_ADDR
VGA_DEVICE
0
0x9E (Default)
0
3D Device
1
0x9C (Multi-GPU usage)
1
VGA Device (Default)
PD 20K
A
Compal Secret Data
Issued Date
2009/01/01
Deciphered Date
2010/01/01
Title
Custom
Date:
5
4
3
2
A
MSIC
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
24
of
59
A
B
Clock Generator
C
D
E
F
G
H
For SED
+3VS_CK505
For SED
2
1
1
C212
2
0.1U_0402_16V4Z
C251
47P_0402_50V8J
FBMH1608HM601-T_0603
10U_0805_10V4Z
1
2
R101
1
+1.05VS
C219
1
For SED
+1.5VS_CK505
1
C213
1
1
C214
2
0.1U_0402_16V4Z
C221
R110
10K_0402_5%
+1.05VS_CK505
1
C222
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C252
47P_0402_50V8J
CK_PWRGD
Change C214 to 1U for NALAA
ESATA issue at pre-MP
Q35B
For RF
5
2
CLK_ENABLE#
2N7002DW-T/R7_SOT363-6
C215
2
0.1U_0402_16V4Z
CPU_SEL
C484 1
1
2
100P_0402_50V8J
+3VS_CK505
+1.05VS_CK505
+1.05VS_CK505
+3VS_CK505
1 R391
1 R143
<13> 27M_CLK
<13> 27M_SSC
2 33_0402_5%
2 33_0402_5%
Silego Have Internal Pull-Up
+3VS_CK505
27M_CLK_R C495 1
+1.5VS_CK505
U5
1
2
3
4
5
6
7
8
<29> CLK_DOT
<29> CLK_DOT#
27M_CLK_R
27M_SSC_R
9
10
11
12
13
14
15
16
<29> CLK_SATA
<29> CLK_SATA#
<29> PCH_CLK_DMI
<29> PCH_CLK_DMI#
H_STP_CPU#
<54>
4
+1.5VS
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
C220
2
FBMH1608HM601-T_0603
1
2
R120
For SED
1
2
C211
2
3
C210
2
10U_0805_10V4Z
1
C209
For SED
+3VS_CK505
1
R401
0_0603_5%
@
0.1U_0402_16V4Z
1
1
2
2
0.1U_0402_16V4Z
1
1
2
FBMH1608HM601-T_0603
1
2
R100
+3VS
33
H_STP_CPU#
2
10K_0402_5%
1 R105
2
33P_0402_50V8K
VDD_USB_48
VSS_48M
DOT_96
DOT_96#
VDD_27
27MHZ
27MHZ_SS
USB_48
SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#
VSS_27M
SATA
SATA#
VSS_SRC
SRC_1
SRC_1#
VDD_SRC_IO
CPU_STOP#
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
PM_SMBCLK
PM_SMBDATA
CPU_SEL 1
R102
CLK_XTAL_IN
CLK_XTAL_OUT
32
31
30
29
28
27
26
25
PM_SMBCLK <11,12,29,39>
PM_SMBDATA <11,12,29,39>
CLK_14M_PCH <29>
2
33_0402_5%
27M_SSC_R C496 1
2
33P_0402_50V8K
10K_0402_5%
@
2
1 R119
+1.05VS
CK_PWRGD
CPU_SEL
24
23
22
21
20
19
18
17
10K_0402_5%
1 R106
2
CLK_XTAL_OUT
CLK_BCLK <29>
CLK_BCLK# <29>
IDT Have Internal Pull-Down
Y1
CLK_XTAL_IN
1
2
2 14.318MHZ_16PF_7A14300083 2
+1.5VS_CK505
C223
22P_0402_50V8J
TGND
1
1
C224
22P_0402_50V8J
CPU_SEL
CPU_0/0#
CPU_1/1#
0 (Default)
133MHz
133MHz
1
100MHz
100MHz
RTM890N-631-VB-GRT QFN 32P
OPTIMUS
2
2
+LCD_VDD
<31> UMA_ENBKL
3
<14> VGA_TXOUT1+
<14> VGA_TXOUT2<14> VGA_TXCLK+
<14> VGA_TXCLK<13> VGA_EDID_CLK
<13> VGA_EDID_DATA
<13> VGA_BL_PWM
<13> VGA_ENVDD
<13> VGA_ENBKL
1 DIS@
2
R331
0_0402_5%
1 DIS@
2
R309
0_0402_5%
1 DIS@
2
R317
0_0402_5%
1 DIS@
2
R315
0_0402_5%
1 DIS@
2
R308
0_0402_5%
1 DIS@
2
R302
0_0402_5%
1 DIS@
2
R305
0_0402_5%
1 DIS@
2
R304
0_0402_5%
1 DIS@
2
R314
0_0402_5%
DIS@
1
2
R310
0_0402_5%
1 3D@
2
R349
0_0402_5%
1 DIS@
2
R356
0_0402_5%
1 DIS@
2
R358
0_0402_5%
12
R109 2
1
47K_0402_5%
Q17
AO3415_SOT23-3
1
1
LVDS_EDID_CLK
W=80mils
2
3
2
C228
0.1U_0402_16V7K
2
3
LVDS_TXCLK-
1
6
Q1A
2N7002DW-T/R7_SOT363-6
1 CAM@ 2
R96
0_0402_5%
C229
0.01U_0402_25V7K
LVDS_EDID_DATA
LCD_ENVDD
LCD_ENVDD
+LCD_VDD
W=80mils
2
5
LED_PWM
EC_ENBKL
Q1B
2N7002DW-T/R7_SOT363-6
1
W=20mils
+3VS
LVDS_TXOUT0+
LVDS_TXOUT0LVDS_TXOUT1+
LVDS_TXOUT1LVDS_TXOUT2+
LVDS_TXOUT2LVDS_TXCLK+
LVDS_TXCLK-
CAM@
D84
0.1U_0402_16V4Z
2
1
2
1
C225
3
@
LVDS_EDID_CLK
PACDN042Y3R_SOT23-3
2
2
LVDS_EDID_DATA
4
4
INT_MIC_CLK
6
INT_MIC_CLK <42>
6
INT_MIC_DATA
8
INT_MIC_DATA <42>
8
LED_PWM
R387 2 NO3D@ 1 0_0402_5%
10
INVT_PWM <43>
10
BKOFF#_R
12
2
1
BKOFF# <43>
12
R103
33_0402_5%
14
14
LCD_ENVDD
16
1
2
16
R113
10K_0402_5%
18
18
20
20
22
3A
22
24
+LCD_VDD
24
26
Remove
L1 for
1
1
26
28
+LCD_INV 3D Panel at DVT
28
C226
C227
30
30
0.1U_0402_16V4Z
4.7U_0805_10V4Z
2
2
GND1
GND2
1 CAM@ 2 +3VS_LVDS_CAM
R388
0_0603_5%
JLVDS
1
1
USB20_P11_R
3
3
USB20_N11_R
5
5
7
7
LVDS_TXOUT0+
9
9
LVDS_TXOUT011
11
LVDS_TXOUT1+
13
13
LVDS_TXOUT115
15
LVDS_TXOUT2+
17
17
LVDS_TXOUT219
19
LVDS_TXCLK+
21
21
LVDS_TXCLK23
23
25
25
27
27
29
29
LVDS_EDID_CLK
31
32
LVDS_EDID_DATA
ACES_87242-3001-09
LED_PWM
2
R112
100K_0402_5%
OPT@
LCD/PANEL BD. Conn.
EC_ENBKL <43>
DISCRETE
<14> VGA_TXOUT0-
3
WCM-2012-900T_0805
LVDS_TXCLK+
Close to LVDS Connector
<14> VGA_TXOUT0+
4
+3VS
R108
100K_0402_5%
C233
0.1U_0402_16V4Z
+LCD_INV
C234
68P_0402_50V8J
1
B+
L2
2
1
1 FBMA-L11-201209-221LMA30T_0805
2
C235
0.1U_0402_25V6
2
3
+3VS
For EMI
1
@
C231
680P_0402_50V7K
2
1
2
B+
C232
0.1U_0402_16V4Z
For EMI
Add +LCD_VDD and LCD_ENVDD
for CMO 3D Panel at PVT
LCD_ENVDD
EC_ENBKL
1
2
C236
1
2
C268
1
2
C489
@
0.1U_0402_16V4Z
<31> UMA_ENVDD
LVDS_TXOUT2-
USB20_P11_R
0.1U_0402_16V4Z
<31> PCH_PWM
LVDS_TXOUT2+
3
+3VS
R107
150_0603_5%
USB20_N11_R
0.1U_0402_16V4Z
<31> LCD_EDID_DATA
<32> USB20_P11
4
1 CAM@ 2
R78
0_0402_5%
L55
@
2
1
2
0.1U_0402_16V4Z
<31> LCD_EDID_CLK
1
4
<31> LCD_TXCLK-
<32> USB20_N11
1
<31> LCD_TXOUT2<31> LCD_TXCLK+
LVDS_TXOUT1-
2
<31> LCD_TXOUT2+
LVDS_TXOUT1+
1
<31> LCD_TXOUT1-
Reserve for EMI request
1
LVDS_TXOUT0-
2
1 OPT@ 2
R263
0_0402_5%
1 OPT@ 2
R265
0_0402_5%
1 OPT@ 2
R264
0_0402_5%
1 OPT@ 2
R298
0_0402_5%
1 OPT@ 2
R277
0_0402_5%
1 OPT@ 2
R297
0_0402_5%
1 OPT@ 2
R296
0_0402_5%
1 OPT@ 2
R300
0_0402_5%
1 OPT@ 2
R299
0_0402_5%
1 OPT@ 2
R332
0_0402_5%
1 OPT@ 2
R350
0_0402_5%
1 OPT@ 2
R357
0_0402_5%
<31> LCD_TXOUT1+
G
<31> LCD_TXOUT0-
D
LVDS_TXOUT0+
S
<31> LCD_TXOUT0+
1 OPT@ 2
R262
0_0402_5%
1
C490
2
Close to LVDS Connector
OPTIMUS for Full-HD
For Full-HD LCD
DISCRETE for Full-HD and 3D Panel
JLVDS1
<31> LCD_TZOUT0+
<31> LCD_TZOUT0<31> LCD_TZOUT1+
<31> LCD_TZOUT1<31> LCD_TZOUT2+
4
<31> LCD_TZOUT2<31> LCD_TZCLK+
<31> LCD_TZCLK-
1OPTFH@ 2
R448
0_0402_5%
1OPTFH@ 2
R445
0_0402_5%
1OPTFH@ 2
R447
0_0402_5%
1OPTFH@ 2
R446
0_0402_5%
1OPTFH@ 2
R444
0_0402_5%
1OPTFH@ 2
R441
0_0402_5%
1OPTFH@ 2
R443
0_0402_5%
1OPTFH@ 2
R442
0_0402_5%
LVDS_TZOUT0+
LVDS_TZOUT0LVDS_TZOUT1+
LVDS_TZOUT2LVDS_TZCLK+
LVDS_TZCLK-
<14> VGA_TZOUT0+
<14> VGA_TZOUT2<14> VGA_TZCLK+
<14> VGA_TZCLK-
LVDS_TZOUT0+
LVDS_TZOUT2LVDS_TZCLK+
LVDS_TZCLK-
LVDS_TZOUT0+
1 3D@
2
R500
0_0402_5%
1 3D@
2
R501
0_0402_5%
1 3D@
2
R502
0_0402_5%
1 3D@
2
R503
0_0402_5%
1 3D@
2
R504
0_0402_5%
1 3D@
2
R505
0_0402_5%
1 3D@
2
R507
0_0402_5%
1 3D@
2
R508
0_0402_5%
LVDS_TZOUT2-
+5VALW
1
2
3
4
5
6
7
8
9
10
Add +5VALW for
3D Panel at PVT
LVDS_TZCLK+
1
2
3
4
5
6
7
8
9
10
4
11
12
LVDS_TZCLK-
GND1
GND2
ACES_87213-1000N
@
Issued Date
Compal Secret Data
200910/9
Deciphered Date
2010/01/23
Title
A
B
C
D
E
F
G
CCLK GEN/LVDS
Size
Document Number
Custom
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
H
25
of
59
A
B
C
D
E
D4
@
D5
1
@
1
1
CRT CONNECTOR
D3
@
+3VS
If=1A
+5VS
DAN217_SC59
1
1
RB491D_SOT23-3
3
1
1
2 NBQ100505T-800Y_0402
CRT_R_L
L4
1
2 NBQ100505T-800Y_0402
CRT_G_L
CRT_B
L5
1
2 NBQ100505T-800Y_0402
2
1
1.1A_6V_MINISMDC110F-2
C237
0.1U_0402_16V4Z
2
@
1
CRT_HSYNC
CRT_B_L
CRT_VSYNC
JCRT
C238
1
C239
2
1
C240
2
2
1
C241
2
1
C242
2
1
C243
2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
CRT_R_L
2.2P_0402_50V8C
Close to CRT Connector
1
2.2P_0402_50V8C
R138 R139 R140
2.2P_0402_50V8C
CRT_DATA
2.2P_0402_50V8C
CRT_CLK
2.2P_0402_50V8C
<31> UMA_CRT_DATA
L3
CRT_G
2.2P_0402_50V8C
<31> UMA_CRT_CLK
CRT_R
40 mils
CRT_B
2
1
150_0402_1%
<31> UMA_CRT_VSYNC
CRT_G
2
1
150_0402_1%
<31> UMA_CRT_HSYNC
CRT_R
2
1
150_0402_1%
<31> UMA_CRT_G
<31> UMA_CRT_B
1 OPT@ 2
R200
0_0402_5%
1 OPT@ 2
R204
0_0402_5%
1 OPT@ 2
R211
0_0402_5%
1 OPT@ 2
R213
0_0402_5%
1 OPT@ 2
R235
0_0402_5%
1 OPT@ 2
R236
0_0402_5%
1 OPT@ 2
R261
0_0402_5%
+CRT_VCC
F1
2
3
2
DAN217_SC59
3
3
2
DAN217_SC59
2
OPTIMUS
<31> UMA_CRT_R
+CRT_VCC_R
D6
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+CRT_VCC
VSYNC
CRT_DDC_CLK
DISCRETE
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
ALLTO_C10532-11505-L_15P-T
@
2
2
5
1
2
R141
CRT_VSYNC
CRT_HSYNC
CRT_CLK
2
A
Y
4
U6
SN74AHCT1G125GW _SOT353-5
CRT_DATA
1
10K_0402_5%
D_CRT_HSYNC
1
L6
2
10_0402_5%
D_CRT_VSYNC
1
L7
2
10_0402_5%
+CRT_VCC
CRT_VSYNC
A
4
Y
G
2
U7
SN74AHCT1G125GW _SOT353-5
C245
@
3
Close to CRT Connector
HSYNC
VSYNC
1
2
1
C246
@
2
10P_0402_50V8J
<13> VGA_CRT_DATA
CRT_HSYNC
10P_0402_50V8J
<13> VGA_CRT_CLK
2
0.1U_0402_16V4Z
5
1
<13> VGA_CRT_VSYNC
1
C244
CRT_B
P
OE#
<13> VGA_CRT_HSYNC
CRT_G
P
OE#
<13> VGA_CRT_B
+CRT_VCC
CRT_R
G
<13> VGA_CRT_G
1 DIS@
2
R178
0_0402_5%
1 DIS@
2
R181
0_0402_5%
1 DIS@
2
R167
0_0402_5%
1 DIS@
2
R177
0_0402_5%
1 DIS@
2
R179
0_0402_5%
1 DIS@
2
R193
0_0402_5%
1 DIS@
2
R194
0_0402_5%
3
<13> VGA_CRT_R
3
3
+CRT_VCC
2
2
+3VS
5
Q205B
4
CRT_DATA
1
C282
33P_0402_50V8K
2
@
1
1
2
Q205A
1
CRT_CLK
R159
4.7K_0402_5%
1
R153
4.7K_0402_5%
CRT_DDC_CLK
6
2N7002DW -T/R7_SOT363-6
CRT_DDC_DAT
3
2N7002DW -T/R7_SOT363-6
C285
33P_0402_50V8K
2 @
C284
470P_0402_50V8J
@
1
1
2
C283
470P_0402_50V8J
2 @
4
4
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
A
B
C
D
Title
CRT
Size
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
E
26
of
59
5
4
C262
1
0.1U_0402_16V4Z
CEC@
2
2
8
HDMI_CECIN
9
HDMI_CECOUT
10
P4_5/INT0#/RXD1
P3_3/TCIN/INT3#/SSI00/CMP1_0
P1_7/CNTR00/INT10#
P3_4/SCS#/SDA/CMP1_1
R5F211A4C33SP-W4_LSSOP20
20
HDMI_CLK
Q48
BSH111_SOT23-3
CEC@
3
1
1
D
2
HDMI_HPD_R
3
R184
2.2K_0402_5%
HDMI@
VGA_HDMI_CLK <14>
G
19
2
HDMI_DATA
2
18
R185
2.2K_0402_5%
HDMI@
HDMI_SCLK
1
HDMI_DATA
3
2
P1_0/KI0#/AN8/CMP0_0
1
HDMI_SDATA
2 CEC@ 1
R176
4.7K_0402_5%
R166
4.7K_0402_5%
CEC@
Q18
BSH111_SOT23-3
DHDMI@
1
HDMI_SDATA
Q19
BSH111_SOT23-3
DHDMI@
3
VGA_HDMI_DATA <14>
G
MODE
HDMI_SCLK
+3VS_DGPU
S
VCC/AVCC
17
16
R164
4.7K_0402_5%
CEC@
2
P4_2/VREF
Q47
BSH111_SOT23-3
CEC@
1
C848
1
C263
G
XIN/P4_6
CEC@
2
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z
CEC@
HDMI_CLK
15
1
14
G
P1_2/KI2#/AN10/CMP0_2
+HDMI_5V_OUT
S
Q50
2N7002_SOT23-3
CEC@
VSS/AVSS
+3VL
2
+3VL
CEC_FSHUPD (Pin13)
Low= Force to update flash.
D
3
1
P1_3/KI3#/AN11/TZOUT
CEC_FSHUPD1 CEC@ 2
R170
4.7K_0402_5%
D
1
3
6
D
S
XOUT/P4_7
13
Change Q18 and Q19 power to
+3VS_DGPU at pre-MP
CEC_INT# <43> +3VL
1 CEC@ 2
R168
4.7K_0402_5%
S
2 CEC@ 1CEC_XIN
R174
47K_0402_5%
7
R165
100K_0402_5%
CEC@
P1_4/TXD0
CEC_TEST
D
2
HDMI_CEC
2
G
P1_5/RXD0/CNTR01/INT11#
RESET#
CEC_INT#
12
+3VL
5
S
1 R163
2
27K_0402_5%
CEC@
P3_7/CNTR0#/SSO/TXD1
11
S
1
2
G
P1_6/CLK0/SSI01
2
1 1
2 CEC@ 1CEC_XOUT 4
R171
47K_0402_5%
D
HDMI_CECOUT
3
R581
27K_0402_5%
CEC@
D
Q49
2N7002_SOT23-3
CEC@
2 CEC@ 1CEC_RST#
R169
4.7K_0402_5%
P3_5/SSCK/SCL/CMP1_2
1
2
1
D9
CH751H-40PT_SOD323-2
CEC@
2
HDMI_CECIN
2
1
1
<43,48> EC_SMB_CK1
+3VL
R162
10K_0402_5%
CEC@
1
U16
Address: 0011010X
+3VL
D
+3VL
2
2
HDMI CEC Controller
3
EC_SMB_DA1 <43,48>
CEC@
Add R145 for U9 ESD issue at DVT
+5VL
HDMI@
R145
HDMI_HPD_U 1
2
1K_0402_5%
+3VS
+3VS
<14> VGA_HDMI_TX2-
2 0.1U_0402_16V7K DHDMI@
VGA_DVI_TXC-
1
2 0.1U_0402_16V7K DHDMI@
VGA_DVI_TXD0+
CV297
1
2 0.1U_0402_16V7K DHDMI@
CV299
1
2 0.1U_0402_16V7K DHDMI@
CV298
1
2 0.1U_0402_16V7K DHDMI@
VGA_DVI_TXD1-
CV295
1
2 0.1U_0402_16V7K DHDMI@
VGA_DVI_TXD2+
CV300
1
2 0.1U_0402_16V7K DHDMI@
VGA_DVI_TXD2-
VGA_HDMI_HPD
R438
2
1
0_0402_5%
IHDMI@
2
2
0.1U_0402_16V4Z
1
C340
IHDMI@
2
0.1U_0402_16V4Z
1
1
C319
C315
IHDMI@
IHDMI@
0.1U_0402_16V4Z
2
2
C264
0.1U_0402_16V4Z
HDMI@
R303
10K_0402_5%
IHDMI@
0.1U_0402_16V4Z
PCH_HDMI_HPD
OE#
1
2
A
D
VGA_DVI_TXD0-
U18
Q25
2N7002_SOT23-3
IHDMI@ S
VGA_DVI_TXD1+
+3VS
OE*
2
11
15
21
26
33
40
46
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
SCL_SINK
SDA_SINK
HPD_SINK
DDC_EN
2
G
HDMI_HPD
2
C339
IHDMI@
1
1
5
C317
IHDMI@
P
2
1
R186
100K_0402_5%
HDMI@
HDMI_HPD_R
U9
4
Y
2
1
C265
0.1U_0402_16V4Z
HDMI@
1
1
CV294
2
C292
IHDMI@
OE#
CV293
2
1
G
VGA_DVI_TXC+
C371
IHDMI@
3
<14> VGA_HDMI_TX0+
2 0.1U_0402_16V7K DHDMI@
1
1
<14> VGA_HDMI_CLKC
1
1
2
74AHCT1G125GW_SOT353-5
HDMI@
C
HDMI_HPD
3
<14> VGA_HDMI_CLK+
CV296
C314
IHDMI@
10U_0805_10V4Z
0.1U_0402_16V4Z
1
For DISCRETE
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
25
OE# 2
R199
28
HDMI_SCLK
@
1
10K_0402_5%
29
HDMI_SDATA
30
HDMI_HPD
32
DDC_EN R374 2 IHDMI@ 1 4.7K_0402_5%
+3VL
+3VS
HDMI@
2
1
R570
100K_0402_5%
DHDMI@
2
1
R571
2.2K_0402_5%
+3VS
D55
1 HDMI@ 2
R157
0_0402_5%
L8
@
1
2
1
2
4
B
VGA_DVI_TXC+
VGA_DVI_TXD0+
3
1 HDMI@ 2
R175
0_0402_5%
L9
@
1
2
1
2
4
3
<31> UMA_HDMI_DATA
<31> UMA_HDMI_CLK
HDMI_R_CK+
HDMI_R_D0+
1 HDMI@ 2
R182
0_0402_5%
L10
@
1
2
1
2
8
9
VGA_DVI_TXC+
VGA_DVI_TXC-
13
14
VGA_DVI_TXD2+
VGA_DVI_TXD2-
16
17
VGA_DVI_TXD1+
VGA_DVI_TXD1-
19
20
VGA_DVI_TXD0+
VGA_DVI_TXD0-
22
23
HDMI_R_D1-
HDMI_R_CK+
1 DHDMI@2
R195 499_0402_1%
1 DHDMI@2
R197 499_0402_1%
HDMI_R_D1- 1 DHDMI@2
R198 499_0402_1%
HDMI_R_D1+ 1 DHDMI@2
R202 499_0402_1%
R201 499_0402_1%
R203 499_0402_1%
R205 499_0402_1%
R206 499_0402_1%
1 HDMI@ 2
R187
0_0402_5%
L11
@
1
2
1
2
4
VGA_DVI_TXD2-
4
3
R360
R371
R373
R370
2 IHDMI@ 1 2.2K_0402_5%
2 IHDMI@ 1 2.2K_0402_5%
@
1
2 0_0402_5%
@
1
2 0_0402_5%
HDMI_HPD_R
+3VS
1
VGA_HDMI_HPD
HDMI_R_D2+
R1394
100K_0402_5%
SDA_SOURCE
SCL_SOURCE
HDMI@
D53
ANALOG2
OUT_D4+
OUT_D4-
IN_D4+
IN_D4-
OUT_D3+
OUT_D3-
IN_D3+
IN_D3-
OUT_D2+
OUT_D2-
IN_D2+
IN_D2-
OUT_D1+
OUT_D1-
IN_D1+
IN_D1-
48
47
HDMI_TXC+
HDMI_TXC-
45
44
HDMI_TX2+
HDMI_TX2-
42
41
HDMI_TX1+
HDMI_TX1-
39
38
HDMI_TX0+
HDMI_TX0-
IHDMI@
C430 1
C374 1
IHDMI@
C456 1
C432 1
IHDMI@
C372 1
C434 1
IHDMI@
C455 1
C373 1
2
+5VS
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
IHDMI@
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
IHDMI@
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
IHDMI@
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
IHDMI@
UMA_HDMI_TXC+ <31>
UMA_HDMI_TXC- <31>
UMA_HDMI_TX2+ <31>
UMA_HDMI_TX2- <31>
UMA_HDMI_TX1+ <31>
UMA_HDMI_TX1- <31>
1
F2
+HDMI_5V_OUT_F 2
1
+HDMI_5V_OUT
1.1A_6V_MINISMDC110F-21
HDMI@
C259
B
HDMI@
0.1U_0402_16V4Z
2
PMEG2010AEH_SOD123
D54
2
+5VL
1
PMEG2010AEH_SOD123
IHDMI@
Add D54 for HDMI CEC issue at pre-MP
UMA_HDMI_TX0+ <31>
UMA_HDMI_TX0- <31>
+5VS
JHDMI
HDMI_HPD
THERMAL_PAD
49
S
@
1
2
R207 100K_0402_5%
HDMI_SDATA
HDMI_SCLK
HDMI_CEC
HDMI_R_CK-
R208
2.2K_0402_5%
IHDMI@
IHDMI@
HDMI_R_CK+
HDMI_R_D0-
HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
Q24
2N7002_SOT23-3
DHDMI@
@
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
A
TYCO_1939864-1_19P
Compal Secret Data
200910/9
Deciphered Date
2010/01/23
Title
Size
Date:
4
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
HDMI_TXC-
Add R208 for AOC monitor
issue at PVT
2
G
HDMI_R_D2-
HDMI Connector
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI_R_D0+
HDMI_R_D1-
D
<13,33>
HPD_SOURCE
Issued Date
5
2
DHDMI@
2
34
35
ANALOG1(REXT)
ASM1442 QFN_48P_7X7
3
OCE2012120YZF
1 HDMI@ 2
R188
0_0402_5%
FUNCTION3
FUNCTION4
2
HDMI_R_D1+
1
A
3
10
1
5
12
18
24
27
31
36
37
43
3
VGA_DVI_TXD2+
4
7
FUNCTION1
FUCNTION2
HDMI_R_D0-
3
OCE2012120YZF
1 HDMI@ 2
R183
0_0402_5%
VGA_DVI_TXD1+
6
UMA_HDMI_CLK
HDMI_R_CK4
3
4
UMA_HDMI_DATA
R692 1 IHDMI@ 2 2.2K_0402_5%
3
OCE2012120YZF
1 HDMI@ 2
R180
0_0402_5%
VGA_DVI_TXD0-
2.2K_0402_5%
2.2K_0402_5%
0_0402_5%
0_0402_5%
2 R161
1
IHDMI@ 3.48K_0402_1%
PCH_HDMI_HPD
<31> PCH_HDMI_HPD
HDMI_R_CK-
3
OCE2012120YZF
1 HDMI@ 2
R173
0_0402_5%
4
VGA_DVI_TXD1-
4
1 IHDMI@ 2
1 IHDMI@ 2
@
1
2
@
1
2
1
VGA_DVI_TXC-
R375
R196
R367
R154
1
+3VS
3
2
HDMI Conn./CEC
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
27
of
59
5
4
CMOS Setting, near DDR Door
JCMOS
Y3
2
1U_0402_6.3V4Z
3
NC
OSC
4
2
NC
OSC
1
J2
32.768KHZ_12.5PF_Q13MC14610002
2
1U_0402_6.3V4Z
2
C290
U11A
PCH_RTCX1
PCH_RTCX2
B13
D13
RTCX1
RTCX2
PCH_RTCRST#
C14
RTCRST#
PCH_SRTCRST#
D17
SRTCRST#
SM_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%
A16
INTRUDER#
A14
INTVRMEN
1
15P_0402_50V8J
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
D33
B33
C32
A32
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
FWH4 / LFRAME#
C34
LPC_FRAME#
LDRQ0#
LDRQ1# / GPIO23
A34
F34
FELICA_PW R
SERIRQ
AB9
SERIRQ
Integrated SUS 1.05V VRM Enable
1
R285
1
R275
High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)
A30
HDA_BCLK
HDA_SYNC
AZ_SYNC
D29
HDA_SYNC
This signal has a weak internal pull down.
H=>On Die PLL is supplied by 1.5V
Die PLL is supplied by 1.8V
PCH_SPKR
This signal has a weak internal pull down.
This signal can't PU
HDA_RST#
<42> AZ_SDIN0_HD
AZ_SDIN0_HD
G30
HDA_SDIN0
<38> AZ_SDIN1_MD
AZ_SDIN1_MD
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
Flash Descriptor Security Overide
@
AZ_SDOUT
R118 1
*
2 1K_0402_5%
<43> PW RME_CTRL#
<38> AZ_RST_MD#
<42> AZ_RST_HD#
R291 1 MDC@ 2 33_0402_5%
R292 1
2 33_0402_5%
AZ_RST#
<38> AZ_SDOUT_MD
<42> AZ_SDOUT_HD
R293 1 MDC@ 2 33_0402_5%
R294 1
2 33_0402_5%
AZ_SDOUT
SPI_MOSI
PCH_JTAG_TCK
M3
JTAG_TCK
PCH_JTAG_TMS
K3
JTAG_TMS
PCH_JTAG_TDI
K1
JTAG_TDI
PCH_JTAG_TDO
J2
JTAG_TDO
PCH_JTAG_RST#
J4
TRST#
AZ_SYNC
Internal: Pull down 20k
High = Enabled
Low = Disabled (Default)
2
R273
@
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AH6
AH5
AH9
AH8
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF11
AF9
AF7
AF6
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AH3
AH1
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AD9
AD8
AD6
AD5
SATA_PRX_C_DTX_N4
SATA_PRX_C_DTX_P4
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4
AD3
AD1
AB3
AB1
SATA_PRX_C_DTX_N5
SATA_PRX_C_DTX_P5
SATA_PTX_DRX_N5
SATA_PTX_DRX_P5
SATAICOMPO
AF16
SATAICOMPI
AF15
1
PCH Pin
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TCK
PCH_JTAG_RST#
RefDes
R358
R535
R355
R354
R536
R537
R156
R643
R353
5
SATA ODD
SATA_PRX_C_DTX_N5 <37>
SATA_PRX_C_DTX_P5 <37>
SATA_PTX_DRX_N5 <37>
SATA_PTX_DRX_P5 <37>
eSATA
2
37.4_0402_1%
+1.05VS
+3VS
SPI_CS0#
AY3
SPI_CS1#
SATALED#
T3
SATA_LED#
AY1
SPI_MOSI
SATA0GP / GPIO21
Y9
CR_W AKE#
SATA1GP / GPIO19
V1
VGA_PW ROK
SPI_MISO
HM55R1@
SATA_LED# <45>
CR_W AKE# <41>
CR_W AKE#
R330 2
SATA_LED#
R301 2
1 10K_0402_5%
1 10K_0402_5%
B
@
VGA_PW ROK <32,46,56>
VGA_PW ROK
R306 1
2 10K_0402_5%
For Optimus
+3VS
4MB
PCH_JTAG_RST#
@
R364
10K_0402_5%
1
C293
0.1U_0402_16V4Z
for EMI
PCH JTAG Disable (Default)
ES1
ES2
No Install
No Install
No Install
No Install
No Install
No Install
No Install
No Install
20Kohm
No Install
10Kohm
No Install
51ohm
51ohm
No Install
No Install
No Install
No Install
2
VCC
3
W
7
HOLD
PCH_SPI_CS0#
1
S
PCH_SPI_CLK
6
C
PCH_SPI_MOSI
5
D
VSS
PCH_SPI_CLK
4
D13
BAS40-04_SOT23-3
R385
10_0402_5%
@
+RTCVCC
Q
2
PCH_SPI_MISO
C86
10P_0402_50V8J
@
C291
1
+CHGRTC
1
0.1U_0402_16V4Z
2
Change power to +CHGRTC
for RTC issue at pre-MP
2
A
MX25L3205DM2I-12G SO8
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
4
+RTCBATT
U13
8
2
@
R537
100_0402_5%
Socket: SP07000F500 & SP07000H900
06/01 change R156 from 4.7K to 51 ohm
PCH JTAG Enable
ES1
ES2
No Install
200ohm
No Install
100ohm
200ohm
200ohm
100ohm
100ohm
200ohm
200ohm
100ohm
100ohm
51ohm
51ohm
20Kohm
20Kohm
10Kohm
10Kohm
1
1
1
2
PCH_JTAG_TDI
PCH_JTAG_TCK
2
51_0402_5%
1
R156
SATAICOMP
1
R295
SPI_CLK
@
R643
20K_0402_5%
@
R536
200_0402_5%
PCH_JTAG_TDO
@
R535
100_0402_5%
2
2
@
R363
200_0402_5%
1ST HDD
+3VALW
1
1
@
R355
100_0402_5%
A
2
1
PCH_JTAG_TMS
+3VALW
2
1
2
@
R386
200_0402_5%
2
1
+3VALW
C
AV3
AV1
+3VS
Desktop Only
BA2
IBEXPEAK-M QV20 A0_FCBGA1071
+3VALW
SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
PCH_SPI_CS0#
1PCH_SPI_MOSI
1K_0402_5%
PCH_SPI_MISO
2
10K_0402_5%
AK7
AK6
AK11
AK9
PCH_SPI_CLK
+3VS
FELICA_PW R <38>
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG
<38> AZ_SYNC_MD
<42> AZ_SYNC_HD
R289 1 MDC@ 2 33_0402_5%
R290 1
2 33_0402_5%
ITPM Enabled
B
AZ_BITCLK
D
LPC_FRAME# <43,44>
1
R287 1 MDC@ 2 33_0402_5%
R288 1
2 33_0402_5%
<38> AZ_BITCLK_MD
<42> AZ_BITCLK_HD
CR_CPPE#
<41> CR_CPPE#
SPI
HDA_DOCK_EN#
SPKR
C30
IHDA
HDA_SDO
P1
AZ_RST#
SATA
<31,42> PCH_SPKR
*L=>On
<43,44>
<43,44>
<43,44>
<43,44>
SERIRQ <43,44>
1
R286
AZ_BITCLK
Low = Enabled
High = Disabled
RTC
+RTCVCC
LPC
D
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
2
2
3
1
2PCH_SRTCRST# 1
R284 20K_0402_1%
1
C289
C
1
2
1
C288
iME Setting.
2
2
1
R283
10M_0402_5%
2
1
1
2PCH_RTCRST#
R282 20K_0402_1%
+RTCVCC
3
C287
15P_0402_50V8J
2
1
3
2
Title
PCH_SPI/SATA/LPC/RTC/HDA
Size
B
Date:
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
28
of
59
4
3
2
1
+3VALW
2 R229
1 2.2K_0402_5%
2 R230
1 2.2K_0402_5%
+3VS
Q3B
PCH_SMBDATA
R231
R232
5
5
PCH_SMBCLK
4
PM_SMBDATA <11,12,25,39>
2
3
Q3A
4.7K_0402_5%
4.7K_0402_5%
2N7002DW-T/R7_SOT363-6
6
1
PM_SMBCLK <11,12,25,39>
2N7002DW-T/R7_SOT363-6
D
D
U11B
BA32
BB32
BD32
BE32
C312 1
C301 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PRX_C_CRTX_N5
PCIE_PRX_C_CRTX_P5
PCIE_PTX_CRRX_N5
PCIE_PTX_CRRX_P5
BF33
BH33
BG32
BJ32
C302 1
C868 1
C
NC
CLK_LAN#
CLK_LAN
<40> CLK_LAN#
<40> CLK_LAN
LAN
CLKREQ_LAN#
<40> CLKREQ_LAN#
+3VS
1
10K_0402_5%
2 CLKREQ_NEW#
R246
1
10K_0402_5%
2 CLKREQ_WLAN#
R248
CLKREQ_WLAN#
<39> CLKREQ_WLAN#
CLK_NEW#
CLK_NEW
<39> CLK_NEW#
<39> CLK_NEW
NewCard
B
CLK_WLAN#
CLK_WLAN
<39> CLK_WLAN#
<39> CLK_WLAN
WLAN
CLKREQ_NEW#
<39> CLKREQ_NEW#
+3VALW
1
10K_0402_5%
2 CLKREQ_LAN#
R244
1
10K_0402_5%
2 CLKREQ_JET#
R245
1
10K_0402_5%
2 CLKREQ_CR#
R249
1
10K_0402_5%
2 PCH_GPIO44
R250
1
10K_0402_5%
2 PCH_GPIO56
R251
CLK_JET#
CLK_JET
<39> CLK_JET#
<39> CLK_JET
JET
CLKREQ_JET#
<39> CLKREQ_JET#
Card Reader
CLK_CR#
CLK_CR
<41> CLK_CR#
<41> CLK_CR
CLKREQ_CR#
AT34
AU34
AU36
AV36
PERN7
PERP7
PETN7
PETP7
BG34
BJ34
BG36
BJ36
AK48
AK47
P9
AM43
AM45
U4
AM47
AM48
N4
AH42
AH41
A8
AM51
AM53
M9
H6
P13
PCH_GPIO60
SML0CLK
C6
PCH_SMLCLK0
SML0DATA
G8
PCH_SMLDATA0
M14
PCH_GPIO74
E10
PCH_SMLCLK1
G12
PCH_SMLDATA1
SMBus
SML1ALERT# / GPIO74
SML1DATA / GPIO75
CL_DATA1
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PERN8
PERP8
PETN8
PETP8
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
1 2.2K_0402_5%
+3VS
PCH_SMLDATA1
3
Q4A
PCH_SMLCLK1
CLKOUT_PCIE3N
CLKOUT_PCIE3P
6
1
T11
R260
10K_0402_5%
OPT@
T9
H1
CLK_REQ_VGA#
AD43
AD45
CLK_PCIE_VGA#
CLK_PCIE_VGA
AN4
AN2
CLK_PEG#
CLK_PEG
C
CLK_REQ_VGA# <13>
CLK_PCIE_VGA# <13>
CLK_PCIE_VGA <13> VGA
CLK_PEG# <5>
CLK_PEG <5>
R243
10K_0402_5%
@
+3VALW
PCH_SMLCLK0
PCH_SMLDATA0
PCH_GPIO60
PCH_GPIO74
EC_LID_OUT#
AT1
AT3
PCH_CLK_DMI# <25>
PCH_CLK_DMI <25>
CLKIN_BCLK_N
CLKIN_BCLK_P
AP3
AP1
CLK_BCLK#
CLK_BCLK
CLK_BCLK# <25>
CLK_BCLK <25>
CLKIN_DOT_96N
CLKIN_DOT_96P
F18
E18
CLK_DOT#
CLK_DOT
CLK_DOT# <25>
CLK_DOT <25>
AH13
AH12
CLK_SATA#
CLK_SATA
CLK_SATA# <25>
CLK_SATA <25>
P41
CLK_14M_PCH
CLKIN_PCILOOPBACK
J42
CLK_PCILOOP
CLKOUT_PCIE4N
CLKOUT_PCIE4P
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUTFLEX0 / GPIO64
C277
27P_0402_50V8J
OPT@
XCLK_RCOMP 1
2
R252 90.9_0402_1%
1
2
PCH_X2
25MHZ_20PF_7A25000012
OPT@
2
1
2
C278
27P_0402_50V8J
OPT@
+1.05VS
T42
N50
Note: Stuff 0 ohm if
25MHz crystal un-stuff
C277
0_0402_5%
DIS@
P43
For EMI
CLK_PCILOOP
@
2
R400
CLK_14M_PCH
@
1
R70
@
1
2
1
10_0402_5% C474
22P_0402_50V8J
@
2
2
1
100_0402_5%
C206 100P_0402_50V8J
Deciphered Date
A
Compal Secret Data
200910/9
Issued Date
1
T45
HM55R1@
R237
R238
R239
R240
R241
Y2
CLK_PCILOOP <32>
AF38
1
1
1
1
1
B
R247 2
PCH_X1
PCH_X2
2
2
2
2
2
OPT@
1 1M_0402_5%
CLK_14M_PCH <25>
AH51
AH53
2.2K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
From CLK GEN For: 133/100/96/14.318 MHZ
PCH_X1
PEG_B_CLKRQ# / GPIO56
EC_SMB_CK2 <14,43,44,45>
T13
PCH_CLK_DMI#
PCH_CLK_DMI
REFCLK14IN
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
EC_SMB_DA2 <14,43,44,45>
2N7002DW-T/R7_SOT363-6
AW24
BA24
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
4
2N7002DW-T/R7_SOT363-6
+3VALW
CL_CLK1
A
J14
SML1CLK / GPIO58
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
AK53
AK51
PCH_GPIO56
PERN4
PERP4
PETN4
PETP4
BA34
AW34
BC34
BD34
AJ50
AJ52
PCH_GPIO44
PERN3
PERP3
PETN3
PETP3
2 R234
5
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PRX_JETTX_N4
PCIE_PRX_JETTX_P4
PCIE_PTX_JETRX_N4
PCIE_PTX_JETRX_P4
NEW@
PCH_SMBDATA
SML0ALERT# / GPIO60
+3VALW
Q4B
C8
SMBDATA
EC_LID_OUT# <43>
2
AU30
AT30
AU32
AV32
PCH_SMBCLK
1 2.2K_0402_5%
2
PCIE_PRX_C_CRTX_N5
PCIE_PRX_C_CRTX_P5
PCIE_PTX_C_CRRX_N5
PCIE_PTX_C_CRRX_P5
PCIE_PRX_NEWTX_N3
PCIE_PRX_NEWTX_P3
PCIE_PTX_NEWRX_N3
PCIE_PTX_NEWRX_P3
NEW@
C269 2
1 0.1U_0402_16V7K
C270 2
1 0.1U_0402_16V7K
H14
2 R233
1
For Card Reader
<41>
<41>
<41>
<41>
PERN2
PERP2
PETN2
PETP2
EC_LID_OUT#
1
PCIE_PRX_JETTX_N4
PCIE_PRX_JETTX_P4
PCIE_PTX_C_JETRX_N4
PCIE_PTX_C_JETRX_P4
AW30
BA30
BC30
BD30
SMBCLK
B9
2
For JET
<39>
<39>
<39>
<39>
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
SMBALERT# / GPIO11
Link
PCIE_PRX_NEWTX_N3
PCIE_PRX_NEWTX_P3
PCIE_PTX_C_NEWRX_N3
PCIE_PTX_C_NEWRX_P3
PERN1
PERP1
PETN1
PETP1
Controller
<39>
<39>
<39>
<39>
C274 2
C275 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PEG
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2
C276 2
C273 2
PCI-E*
For NewCard
<39>
<39>
<39>
<39>
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
From CLK BUFFER
For WLAN
<40>
<40>
<40>
<40>
BG30
BJ30
BF29
BH29
Clock Flex
For LAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
2010/01/23
Title
Custom
PCH_CLK/PCIE/SMBUS
Rev
2.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Sheet
1
29
of
59
5
4
3
2
1
D
D
C
1
R316
1
R318
1
R320
PCH_SUSPW RDN
2
10K_0402_5%
PCH_LOW _BAT#
2
10K_0402_5%
IBEX_RI#
2
10K_0402_5%
2
R329
2
R322
2
R323
PM_PW ROK
1
10K_0402_5%
PW ROK
1
10K_0402_5%
LAN_RST#
1
10K_0402_5%
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<6>
<6>
<6>
<6>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<6>
<6>
<6>
<6>
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
<6>
<6>
<6>
<6>
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
1
R311
+1.05VS
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
BC24
BJ22
AW20
BJ20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BD24
BG22
BA20
BG20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
BE22
BF21
BD20
BE18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
BD22
BH21
BC20
BD18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_COMP
2
49.9_0402_1%
BH25
BF25
Close to PCH
DMI_ZCOMP
FDI
+3VALW
<6>
<6>
<6>
<6>
DMI
U11C
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
BJ14
FDI_INT
FDI_FSYNC0
BF13
FDI_FSYNC0
FDI_FSYNC1
BH13
FDI_FSYNC1
FDI_LSYNC0
BJ12
FDI_LSYNC0
FDI_LSYNC1
BG14
FDI_LSYNC1
DMI_IRCOMP
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
FDI_INT
<6>
FDI_FSYNC0
<6>
FDI_FSYNC1
<6>
FDI_LSYNC0
<6>
FDI_LSYNC1
<6>
C
+3VALW
@
1
R256
EC_SW I#
+3VS
2
<43,54> VGATE
XDP_DBRESET#
T6
SYS_RESET#
WAKE#
VGATE
M6
SYS_PWROK
PW ROK
B17
P
U12
IN1
O
4
PWROK
IN2
3
VGATE
<5> XDP_DBRESET#
G
1
<43> PM_PW ROK
5
0.1U_0402_16V4Z
1
2
C230
1
R321
2
0_0402_5%
LAN_RST#
DRAMPW ROK
<5> DRAMPW ROK
PCH_RSMRST#
K5
A10
D9
C16
MEPWROK
LAN_RST#
DRAMPWROK
RSMRST#
B
<43> PCH_SUSPW RDN
<43> PBTN_OUT#
1
R324
+3VALW
2
330K_0402_5%
D26
1
<43,45,47> ACIN
M1
SUS_PWR_DN_ACK / GPIO30
PBTN_OUT#
P5
PWRBTN#
PCH_ACIN
P7
ACPRESENT / GPIO31
PCH_LOW _BAT#
A6
BATLOW# / GPIO72
IBEX_RI#
F14
J12
EC_SW I#
CLKRUN# / GPIO32
Y1
PM_CLKRUN#
SUS_STAT# / GPIO61
P8
SUS_STAT#
PADT38
PADT38
SUSCLK / GPIO62
F3
SUS_CLK
PADT39
PADT39
SLP_S5# / GPIO63
E4
PM_SLP_S5#
SLP_S4#
H7
PM_SLP_S4#
SLP_S3#
P12
PM_SLP_S3#
SLP_M#
K8
TP23
N2
2
1K_0402_5%
0_0402_5%
@
1
C
E
2
MMBT3906_SOT23-3
RSMRST# circuit
1
8.2K_0402_5%
+3VS
PM_SLP_S5# <43>
PM_SLP_S4# <43>
PMSYNCH
RI#
SLP_LAN# / GPIO29
BJ10
PMSYNCH
PM_SLP_S3# <43>
PMSYNCH
<5>
F6
HM55R1@
A
5
4
2
PCH_RSMRST#
1
R326
10K_0402_5%
3
Compal Secret Data
1
2
R328
2.2K_0402_5%
200910/9
Issued Date
Deciphered Date
2010/01/23
5
2
10K_0402_5%
D15B
BAV99DW -7_SOT363
6
2
1
R327
4.7K_0402_5%
D15A
BAV99DW -7_SOT363
1
2
B
+3VALW
A
2
R319
1
R313
2 R325
Q26 1
3
<43> EC_RSMRST#
EC_SW I# <39,40>
B
+3VALW
1
R691
PCH_SUSPW RDN
2
System Power Management
2
0_0402_5%
4
3
2
Title
PCH_DMI/FDI/PWM
Size
B
Date:
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
30
of
59
5
4
3
2
1
U11D
UMA_ENBKL
2
100K_0402_5%
1
R127
<25> LCD_TXCLK<25> LCD_TXCLK+
<25> LCD_TXOUT0<25> LCD_TXOUT1<25> LCD_TXOUT2-
+3VS
LCD_EDID_CLK
1
2.2K_0402_5%
<25> LCD_TXOUT0+
<25> LCD_TXOUT1+
<25> LCD_TXOUT2+
OPT@
LCD_EDID_DATA
1
2.2K_0402_5%
2
R60
<25> LCD_TZCLK<25> LCD_TZCLK+
<25> LCD_TZOUT0<25> LCD_TZOUT1<25> LCD_TZOUT2-
+3VS
OPT@
C
<25> LCD_TZOUT0+
<25> LCD_TZOUT1+
<25> LCD_TZOUT2+
UMA_CRT_CLK
1
2.2K_0402_5%
2
R63
OPT@
<26> UMA_CRT_B
<26> UMA_CRT_G
<26> UMA_CRT_R
OPT@
1
R56
2
150_0402_1%
UMA_CRT_B
2
150_0402_1%
UMA_CRT_G
2
150_0402_1%
UMA_CRT_R
LVD_IBG
LVD_VBG
BF45
BH45
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDSA_CLK#
LVDSA_CLK
LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-
BB47
BA52
AY48
AV47
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+
BB48
BA50
AY49
AV48
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LCD_TZCLKLCD_TZCLK+
AP48
AP47
LVDSB_CLK#
LVDSB_CLK
LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2-
AY53
AT49
AU52
AT53
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LCD_TZOUT0+
LCD_TZOUT1+
LCD_TZOUT2+
AY51
AT48
AU50
AT51
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
UMA_CRT_B
UMA_CRT_G
UMA_CRT_R
AA52
AB53
AD53
CRT_BLUE
CRT_GREEN
CRT_RED
V51
V53
UMA_CRT_HSYNC Y53
UMA_CRT_VSYNC Y51
<26> UMA_CRT_HSYNC
<26> UMA_CRT_VSYNC
1
CRT_IREF
AD48
AB51
1K_0402_1%
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
PCH Strap Pin
@
1 R270
1K_0402_5% 2
@
1 R271
PCI_GNT#0
PCI_GNT#1
PCI_GNT#0 <32>
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
UMA_HDMI_TX2UMA_HDMI_TX2+
UMA_HDMI_TXCUMA_HDMI_TXC+
PCI_GNT#1 <32>
Internal: Pull up 20k
During Reset: High
Initial: High
2
R272
@
1
1K_0402_5%
PCI_GNT#3
PCI_GNT#3 <32>
During Reset: High
Initial: High
A
UMA_HDMI_CLK <27>
UMA_HDMI_DATA <27>
PCH_HDMI_HPD
<27>
UMA_HDMI_TXCUMA_HDMI_TXC+
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
PCH_SPKR Low= Disable
High= Enable
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
BC46
BD46
AT38
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
R86
2
1 100K_0402_5%
HM55R1@
During Reset: Low
Initial: Low
Danbury Technology Enabled
NV_ALE
2
R267
@
1
1K_0402_5%
NV_ALE
NV_ALE <32>
2
R268
@
NV_CLE
1
1K_0402_5%
NV_CLE <32>
Boot BIOS Strap
0
1
0
1
B
High = Enabled
Low = Disabled (Default)
DMI Termination Voltage
NV_CLE
Low= Set to Vss (Default)
High= Set to Vcc
Boot BIOS Loaction
LPC (Default)
Reserved (NAND)
PCI
SPI
A16 Swap Override Strap
PCI_GNT#3
Low= A16 swap override Enable
High= A16 swap override Disable
A
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
5
C
U50
U52
During Reset: Low
Initial: Low
PCI_GNT#1 PCI_GNT#0
HDMI
Add 100K pull down for PCH HPD at PVT
NO REBOOT Strap
0
0
1
1
R130
2.2K_0402_5%
IHDMI@
PCH_HDMI_HPD
PCH_SPKR <28,42>
During Reset: High
Initial: High
1K_0402_5% 2
R128
2.2K_0402_5%
IHDMI@
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
DDPD_CTRLCLK
DDPD_CTRLDATA
+3VS
@
PCH_SPKR
1
2
R269
1K_0402_5%
+3VS
+1.8VS_PCH_NAND
During Reset: HZ
Initial: Low
1 100K_0402_5%
2
BE44
BD44
AV40
B
R83
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
D
Y49
AB49
CRT_DDC_CLK
CRT_DDC_DATA
R266
2
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
CRT
OPT@
1
R58
UMA_CRT_CLK
UMA_CRT_DATA
<26> UMA_CRT_CLK
<26> UMA_CRT_DATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
BG44
BJ44
AU38
DDPC_CTRLCLK
DDPC_CTRLDATA
OPT@
1
R57
T51
T53
Add 100K pull down for PCH HPD at PVT
LVD_VREFH
LVD_VREFL
AV53
AV51
UMA_CRT_DATA
1
2.2K_0402_5%
2
R61
SDVO_INTN
SDVO_INTP
L_CTRL_CLK
L_CTRL_DATA
LCD_TXCLKLCD_TXCLK+
OPT@
2
R82
BJ48
BG48
1
OPT@
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
1
LCTL_CLK
2
AB46
2 10K_0402_5% LCTL_DATA
V48
10K_0402_5%
LVDS_IBG
2
AP39
2.37K_0402_1%
AP41
T40 PAD
AT43
AT42
BJ46
BG46
2
1 OPT@
1 OPT@
1 OPT@
R68
D
L_BKLTCTL
AB48
Y45
SDVO_TVCLKINN
SDVO_TVCLKINP
2
R55
R54
L_BKLTEN
L_VDD_EN
Y48
LCD_EDID_CLK
LCD_EDID_DATA
<25> LCD_EDID_CLK
<25> LCD_EDID_DATA
+3VS
T48
T47
PCH_PW M
Digital Display Interface
<25> PCH_PW M
UMA_ENBKL
UMA_ENVDD
LVDS
<25> UMA_ENBKL
<25> UMA_ENVDD
4
3
2
Title
PCH_CRT/LVDS/HDMI/STRAP
Size
Document Number
Custom
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
1
31
of
59
5
4
3
2
1
@
2
R253
1
0_0402_5%
+3VS
U11E
PCI_PIRQD#
PCI_IRDY#
8.2K_0804_8P4R_5%
RP2
1
2
3
4
C
8
7
6
5
PCI_PIRQH#
PCI_TRDY#
PCI_FRAME#
PCI_PIRQA#
J50
G42
H47
G34
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
G38
H51
B37
A44
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCI_REQ#0
PCI_REQ#1
ODD_EN#
PCI_REQ#3
F51
A46
B45
M53
PCI_GNT#0
PCI_GNT#1
DGPU_RST#
PCI_GNT#3
F48
K45
F36
H53
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
B41
K53
A36
A48
TP_PCI_RST#
K6
8.2K_0804_8P4R_5%
RP3
1
2
3
4
8
7
6
5
PCI_STOP#
PCI_PIRQE#
PCI_PIRQC#
PCI_PIRQG#
8.2K_0804_8P4R_5%
<46> ODD_EN#
<31> PCI_GNT#0
<31> PCI_GNT#1
For Optimus
<31> PCI_GNT#3
+3VS
RP4
1
2
3
4
B
PCI_REQ#3
PCI_PIRQF#
PCI_PIRQB#
PCI_REQ#0
8
7
6
5
T37 PAD
8.2K_0804_8P4R_5%
+3VS
RP5
1
2
3
4
PCI_SERR#
PCI_PERR#
PCI_DEVSEL#
PCI_PLOCK#
8
7
6
5
8.2K_0804_8P4R_5%
PCI_SERR#
PCI_PERR#
E44
E50
PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#
A42
H44
F46
C46
PCI_PLOCK#
D49
PCI_STOP#
PCI_TRDY#
D41
C48
M7
PLT_RST#
<39,40,41,43,44> PLT_RST#
<44> CLK_PCI_DDR
<43> CLK_PCI_EC
<29> CLK_PCILOOP
22_0402_5% 2 R280
22_0402_5% 2 R281
22_0402_5% 2 R279
1
1
1
CLK_SIO
CLK_EC
CLK_PCH
D5
N52
P53
P46
P51
P48
NV_ALE
NV_CLE
BD3
AY6
NV_ALE
NV_CLE
AU2
NV_RCOMP
NV_RB#
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1
IN2
D
P
2
U8
4
O
BUF_PLT_RST# <5>
1
R129
100K_0402_5%
@
2
1
1
3
+3VS
R334
0_0402_5%
@
2
OPT@
IN1
4
O
IN2
2
R399
1
0_0402_5%
OPT@
R390
1K_0402_5%
OPT@
NV_ALE <31>
NV_CLE <31>
PLTRST_VGA# <13>
1
5
1
2
0.1U_0402_16V4Z
P
2
1
R333
0_0402_5%
DGPU_RST#
<28,46,56> VGA_PWROK
1
C477
U20
G
OPT@
2
Add R333 and R334 for
Optimus sequence at pre-MP
R405
100K_0402_5%
OPT@
STOP#
TRDY#
USBRBIAS
PME#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
PLT_RST#
PLTRST_VGA#
1
0_0402_5%
2
R402
AV11
BF5
B25
PLOCK#
C
DIS@
USBRBIAS#
IRDY#
PAR
DEVSEL#
FRAME#
Change R390 to 1K at pre-MP
AY8
AY5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
@
1
2
R276
32.4_0402_1%
AV7
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
SERR#
PERR#
R84
100K_0402_5%
IN1
G
2
NV_RCOMP
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
PCIRST#
5
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
1
2
PCI_REQ#1
NV_DQS0
NV_DQS1
AV9
BG8
PLT_RST#
3
8
7
6
5
AY9
BD1
AP15
BD8
2
1
2
3
4
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
1
RP1
NVRAM
+3VS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
USB
D
PCI
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
For Optimus
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<39>
<39>
<38>
<38>
USB20_N8 <38>
USB20_P8 <38>
USB20_N9 <38>
USB20_P9 <38>
USB20_N10 <39>
USB20_P10 <39>
USB20_N11 <25>
USB20_P11 <25>
USB20_N12 <39>
USB20_P12 <39>
USB20_N13 <39>
USB20_P13 <39>
USB-RIGHT1
USB-RIGHT2
USB-Left1
eSATA-USB
NewCard
BT
Finger Printer
Felica
B
TV Tuner
Int. Camera
3G/ TV tuner
WiMax(WLAN)
+3VALW
Within 500 mils
D25
USBBIAS
N16
J16
F16
L16
E14
G16
F12
T15
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
SLP_CHG_M3
SLP_CHG_M4
EXP_CPPE#
2
R278
RP6
1
22.6_0402_1%
USB_OC#0 <37,43> (USB-Right)
USB_OC#1 <37,43> (USB-Left &
eSATA)
USB_OC#0
SLP_CHG_M3
SLP_CHG_M4
USB_OC#4
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
SLP_CHG_M3 <37>
SLP_CHG_M4 <37>
EXP_CPPE# <39>
RP8
USB_OC#1
USB_OC#2
USB_OC#3
EXP_CPPE#
HM55R1@
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
A
A
200910/9
Issued Date
Compal Secret Data
Deciphered Date
2010/01/23
Title
Custom
PCH_USB/PCI/NAND
Rev
2.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Sheet
1
32
of
59
5
4
3
2
1
U11F
C
<38> BT_RST#
1
R214
1
R218
1
R224
1 DIS@
R221
1
R220
1
R215
1
R217
1
R254
@
1
R255
1
R216
@
1
R257
1
R259
2 PCH_GPIO1
10K_0402_5%
2 PCH_GPIO6
10K_0402_5%
2 EC_SCI#
10K_0402_5%
2 DGPU_PW R_EN
10K_0402_5%
2 RF_OFF#
10K_0402_5%
2 BT_DET#
8.2K_0402_5%
2 PCH_GPIO38
10K_0402_5%
2 CIR_EN#
100K_0402_5%
2 PROJECT_ID0
10K_0402_5%
2 PROJECT_ID1
10K_0402_5%
2 ISDBT_DET
10K_0402_5%
2 THM_ALT#
10K_0402_5%
MISC
LAN_PHY_PWR_CTRL / GPIO12
A20GATE
PCH_GPIO15
T7
GPIO15
<5,11> RST_GATE
<39> ISDBT_DET
<43> THM_ALT#
A
1
2 EC_SMI#
R225
10K_0402_5%
1 DIS@
2 OPTIMUS_EN#
R226
10K_0402_5%
1
2 PCH_GPIO15
R227
1K_0402_5%
1
2 PCH_GPIO28
R242
10K_0402_5%
1
2 LVDS_SEL
R222
10K_0402_5%
1
2 RST_GATE
R223
10K_0402_5%
1
2 PCH_GPIO12
R219
10K_0402_5%
1
2 PROJECT_ID0
R416
10K_0402_5%
@
1
2 PROJECT_ID1
R415
10K_0402_5%
1 OPT@ 2 DGPU_PW R_EN
R59
1K_0402_5%
1
2 ISDBT_DET
R160
47K_0402_5%
@
1
2 BT_RST#
R228
10K_0402_5%
1 OPT@ 2 OPTIMUS_EN#
R258
10K_0402_5%
1 CIR@ 2 CIR_EN#
R461
10K_0402_5%
GATEA20
GATEA20 <43>
AA2
SATA4GP / GPIO16
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AM3
CLK_CPU_BCLK#
F38
TACH0 / GPIO17
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AM1
CLK_CPU_BCLK
BT_DET#
Y7
BG10
PECI
T1
KB_RST#
PROCPWRGD
BE10
H_PW RGOOD
THRMTRIP#
BD10
THRMTRIP_PCH#
TP1
BA22
SATA3GP / GPIO37
TP2
AW22
BT_PW R#
SCLOCK / GPIO22
H10
GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI# / GPIO34
BT_RST#
V6
PROJECT_ID0
AB7
PROJECT_ID1
AB13
PECI
RCIN#
SATA2GP / GPIO36
V3
SLOAD / GPIO38
TP3
BB22
P3
SDATAOUT0 / GPIO39
TP4
AY45
LVDS_SEL
H3
TP5
AY46
RST_GATE
F1
TP6
AV43
ISDBT_DET
AB6
SDATAOUT1 / GPIO48
TP7
AV45
THM_ALT#
AA4
SATA5GP / GPIO49
TP8
AF13
GPIO57
TP9
M18
TP10
N18
TP11
AJ24
TP12
AK41
TP13
AK42
TP14
M32
TP15
N32
TP16
M30
TP17
N30
TP18
H12
TP19
AA23
NC_1
AB45
NC_2
AB38
NC_3
AB42
NC_4
AB41
NC_5
T39
F8
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V#
TP24
Change R59 to 1K at pre-MP
CLK_CPU_BCLK <5>
PECI <5>
KB_RST# <43>
H_PW RGOOD <5>
1
R212
2
56_0402_1%
HM55R1@
H_THERMTRIP# <5>
1
R210
2
+VTT
56_0402_1%
C
CIR_EN#
LVDS_SEL=H
for Single Channel LVDS
CLK_CPU_BCLK# <5>
SATACLKREQ# / GPIO35
PCH_GPIO38
OPTIMUS_EN#
Add R461 for CIR_EN# at DVT
U2
RF_OFF#
+3VALW
B
D
DGPU_PW R_EN
PCH_GPIO27
1
1K_0402_5%
PCH_GPIO28
<38,39> BT_PW R#
AF48
AF47
K9
GPIO8
@
AH45
AH46
PCH_GPIO12
TACH3 / GPIO7
F10
For Optimus
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
J32
EC_SMI#
2
R274
+3VS
TACH2 / GPIO6
EC_SCI#
<38> BT_DET#
PCH_GPIO27
D37
<43> EC_SMI#
<39> RF_OFF#
High = Enabled (Default)
Low = Disabled
PCH_GPIO6
<43> EC_SCI#
<13,46,56> DGPU_PW R_EN
On-Die PLL VR
TACH1 / GPIO1
CPU
During Reset: Low
Initial: Low
C38
RSVD
GPIO15
a Strong pull up may be needed
for GPIO Functionality
BMBUSY# / GPIO0
PCH_GPIO1
GPIO
Not pull down
During Reset: High
Initial: High
Y3
NCTF
<13,27> VGA_HDMI_HPD
GPIO8
D
VGA_HDMI_HPD
P6
C10
PROJECT_ID1 PROJECT_ID0
B
0
0
NDU00/10 (Streamline-M/-S 11.6/13.3")
0
1
NBQAA (Bordeuax 14")
1
0
NWQAA (Marseille 16")
1
1
NALAA (Hamburg 17.3")
Not pull low
internal pull up
During Reset: High
Initial: High
Add OPTIMUS_EN# at DVT
OPTIMUS_EN#
SKU
H
A
L
Discrete Optimus
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
5
2010 Project ID setting
4
3
2
Title
PCH_CPU/GPIO
Size
B
Date:
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
33
of
59
5
4
3
2
1
Add R49 for CRT wave issue at pre-MP
+1.05VS
POWER
1
C499
330U_B2_2.5VM_R15M
M3@
D
+
C295
10U_0805_10V4Z
1
2
1
C294
1U_0402_6.3V4Z
2
2
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
+3VS
2
C310
B
1
0.1U_0402_16V4Z
+PCH_VRM
+1.05VS
VSSA_DAC[1]
AF53
VSSA_DAC[2]
AF51
AN30
AN31
VCCAPLLEXP
VCC3_3[1]
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
VCCIO[1]
VSSA_LVDS
AH39
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
AP43
AP45
AT46
AT45
LVDS
+VCCA_LVDS
2
VCC3_3[2]
AB34
VCC3_3[3]
AB35
VCC3_3[4]
AD35
L12
OPT@
2.2_0603_1%
D
Change L12 to 2.2 ohm
for CRT issue at pre-MP
+3VS
1 OPT@ 2
R137
0_0603_5%
C300
0.01U_0402_25V7K
OPT@
+3VS
L12 DIS@
1
BLM18PG181SN1D_0603
C298
10U_0805_10V4Z
1 0_0402_5%
1 OPT@ 2
R343
0_0402_5%
+VCCTX_LVDS
+3VS
HVCMOS
1
1
C297
0.1U_0402_16V4Z
2
+1.8VS
C299
0.01U_0402_25V7K
OPT@
C299 DIS@
0_0402_5%
2
0.1U_0402_16V4Z
C303
1
close to AB34
C
+PCH_VRM
+1.8VS
2
R336
196mA
3062mA
61mA
375mA
37mA
VCCVRM[2]
AT24
VCCDMI[1]
AT16
VCCDMI[2]
AU16
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
1
0_0402_5%
+PCH_VRM
+VTT
+PCH_VCCDMI
1
2
156mA
VCCIO[54]
VCCIO[55]
AN35
C296
0.01U_0402_25V7K
close to AE50
AH38
375mA
DMI
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]
40mA
2
VCCALVDS
PCI E*
2
10U_0805_10V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
AE52
> 1mA
NAND / SPI
BJ24
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
VCCIO[24]
FDI
AK24
1
C304
1
C305
1
C306
1
C307
1
C308
VCCADAC[2]
R49
1
2
0_0603_5%
+3VS_VCCADAC
R345 2 DIS@
59mA
+1.05VS
AE50
1432mA
+1.05VS
C
VCCADAC[1]
69mA
CRT
Add C499 at DVT
VCC CORE
U11G
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
1
R335
2
0_0603_5%
C309
1U_0402_6.3V4Z
close to AT16
+1.8VS_PCH_NAND
+1.8VS
1
R338
2
2
0_0603_5%
C311
0.1U_0402_16V4Z
1
close to Ak13
B
+3VS
85mA
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
HM55R1@
AM8
AM9
AP11
AP9
2
C313
close to AM8
0.1U_0402_16V4Z
1
A
A
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
5
4
3
2
Title
PCH_POWER-1
Size
B
Date:
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
34
of
59
3
POWER
If two VccME rails can be
combined, only total 2 x 22 µF and
2 x 1 µF caps are necessary
2
VCCME[2]
AD41
VCCME[3]
AF43
Near V39
2
AF41
VCCME[5]
AF42
VCCME[6]
V39
1
C447
22U_0805_6.3V6M
VCCME[4]
1
2
C324
1U_0402_6.3V4Z
V41
VCCME[8]
V42
VCCME[9]
Y39
VCCME[10]
Y41
VCCME[11]
Y42
1
C327
L17 1
2
10UH_LB2012T100MR_20%
1
R347
0_0603_5%
@
2
2
2
C329
1U_0402_6.3V4Z
L18 1
2
10UH_LB2012T100MR_20%
1
2
DCPRTC
196mA
VCCVRM[3]
C332
1U_0402_6.3V4Z
2
+1.05VS
1
C334
1U_0402_6.3V4Z
2
68mA
+1.05VS_PCHDPLL_A
BB51
BB53
+1.05VS_PCHDPLL_B
BD51
BD53
VCCADPLLB[1]
VCCADPLLB[2]
1U_0402_6.3V4Z
1
1
AH23
AJ35
AH35
VCCIO[21]
VCCIO[22]
VCCIO[23]
1
C331 +
220U_B2_2.5VM_R15
V9
AU24
+PCH_VRM
1
C328 +
220U_B2_2.5VM_R15
VCCME[12]
1
+1.05VS
C
+VCCRTCEXT
2
0.1U_0402_16V4Z
1849mA
VCCME[7]
1
C323
22U_0805_6.3V6M
@ 2
163mA
C335
VCCADPLLA[1]
VCCADPLLA[2]
69mA
C336
2
2
1U_0402_6.3V4Z
Short AF34, AH34 and AF32 power
for HDMI Deep Color
AF34
VCCIO[2]
1
C341
2 +V1.1A_INT_VCCSUS Y22
0.1U_0402_16V4Z
1
C343
2
0.1U_0402_16V4Z
> 1mA
V5REF_SUS
> 1mA
V5REF
VCC3_3[8]
375mA
D
C321
0.1U_0402_16V4Z
+1.05VS
+PCH_VCC5REFSUS
VCC3_3[11]
N36
VCC3_3[12]
P36
VCC3_3[13]
U35
VCCIO[4]
V12
31mA
DCPSST
VCCSATAPLL[1]
VCCSATAPLL[2]
1
C325
0.1U_0402_16V4Z
R344
100_0402_1%
+3VS
2
C326
1
1U_0402_6.3V4Z
+5VS
D17
+PCH_VCC5REF
R346
100_0402_1%
C
1
+3VS
J38
M36
1
+PCH_VCC5REF
K49
L38
2
D16
F24
VCC3_3[9]
2
+3VALW +5VALW
V23
VCC3_3[10]
3062mA
+3VALW
2
2
C330
1U_0402_6.3V4Z
C333
0.1U_0402_16V4Z
1
+3VS
AD13
2
C337
VCCIO[3]
AF32
+VCCSST
2
0.1U_0402_16V4Z
U23
VCCIO[56]
VCC3_3[14]
AH34
1
C338
VCCSUS3_3[28]
1U_0402_6.3V4Z
1
AD39
C318
1U_0402_6.3V4Z
C316
2
VCCME[1]
1
2
2
1
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
1
1
1
AD38
C391
C322
22U_0805_6.3V6M 22U_0805_6.3V6M
2
@ 2
320mA
DCPSUSBYP
USB
Near AD38
VCCLAN[2]
Y20
Clock and Miscellaneous
1 +TP_PCH_VCCDSW
0.1U_0402_16V4Z
2
C320
+1.05VS
VCCLAN[1]
AF24
D
3062mA
1
AF23
VccLAN connect to GND if Intel LAN is disabled
52mA
VCCACLK[2]
V24
V26
Y24
Y26
2
AP53
1
+1.05VS
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
2
VCCACLK[1]
1
U11J
AP51
2
4
PCI/GPIO/LPC
5
1
0.1U_0402_16V4Z
AK3
AK1
+1.05VS
163mA
P18
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
+3VS
1
C344
2
0.1U_0402_16V4Z
375mA
V15
VCC3_3[5]
V16
IN
OUT
+VTT
3
+1.5VALW
1
C345
1
C346
1
C347
2
2
APL5301-15DC-TRL_SOT89-3
1
1
1
GND
C485
1U_0603_10V6K
@
C486
4.7U_0805_6.3V6K
@
VCC3_3[6]
Y16
2
4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
VCC3_3[7]
VCCIO[10]
3062mA
AT18
V_CPU_IO[1]
AU18
V_CPU_IO[2]
1849mA
+RTCVCC
1
C351
2
0.1U_0402_16V4Z
1
C348
2
1U_0402_6.3V4Z
1
C349
2
0.1U_0402_16V4Z
A12
VCCRTC
2mA
6mA
AH22
AT20
VCCIO[12]
AF22
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
VCCSUSHDA
+1.05VS
1
AD20
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
+PCH_VRM
AH19
VCCIO[11]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
> 1mA
HDA
2
+3VALW
@
RTC
U54
SATA
VCCSUS3_3[30]
U20
For HDA power rail to +1.5VALW
196mA VCCVRM[4]
VCCSUS3_3[29]
U19
PCI/GPIO/LPC
B
VCCIO[9]
CPU
+3VALW
DCPSUS
B
C342
1U_0402_6.3V4Z
2
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
+1.05VS
AA34
Y34
Y35
AA35
+PCH_VCCME1
+PCH_VCCME2
+PCH_VCCME3
+PCH_VCCME4
L30
+VCC_HDA
HM55R1@
1
2
C350
R351
R352
R353
R354
1
1
1
1
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1
R384
2
0_0402_5%
+3VALW
@
1
R437
2
0_0402_5%
+1.5VALW
Reserve +1.5VALW for HDA
1U_0402_6.3V4Z
A
A
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
Title
Custom
PCH_POWER-2
Rev
2.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Sheet
1
35
of
59
5
4
3
2
1
U11I
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
D
C
B
A
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
U11H
VSS[0]
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
D
C
B
HM55R1@
HM55R1@
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
5
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
A
AB16
4
3
2
Title
PCH_GND
Size
Document Number
Custom
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
1
36
of
59
5
SATA HDD
Conn.
+5VS
3
1
C356
10U_0805_10V4Z
1
C357
0.1U_0402_16V4Z
2
D
1
C358
0.1U_0402_16V4Z
2
JODD
Close to JODD
@
C359
0.1U_0402_16V4Z
2
SSD HDD need 400mA for 3V(PHISON)
+3VS
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
+3VS rail reserve for SSD
1
C363
10U_0805_10V4Z
@
1
C364
0.1U_0402_16V4Z
2
1
C365
0.1U_0402_16V4Z
2
C366
0.1U_0402_16V4Z
15
14
2
GND
GND
SATA_PTX_C_DRX_P4 C378 1
SATA_PTX_C_DRX_N4 C377 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N4
SATA_PRX_DTX_P4
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
C376 1
C375 1
+5VS_ODD
+5VS_ODD
1
1
C353
2
1
C355
0.1U_0402_16V4Z
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
R73
1
USB Board@ Right Side
+3VS
<32> USB20_N0
1
<32> USB20_P0
4
2
C360
0.1U_0402_16V4Z
W=60mils
2.5A
+5VALW
+5VS
+USB_VCCA
4
1
2
3
4
USB_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
2
C361
1
R87
For EMI
U14
R77
1
1
1000P_0402_50V7K
2
2
USB20_N0_R
3
3
USB20_P0_R
@
@
1
2
R149 0_0402_5%
@
1
2
R148 0_0402_5%
+5VL
+5VALW
1
<32> USB20_N1
1
C362
4.7U_0805_10V4Z
2 @
<32> USB20_P1
4
USB20_N0_R
USB20_P0_R
0_0402_5%
2
1
2
2
USB20_N1_R
4
3
3
USB20_P1_R
1
USB20_N3_S
2
1D-
USB20_P3
3
2D+
1D+
VCC
4
2D-
5
GND
C384
0.1U_0402_16V4Z
1
2
10
S
SLP_CHG#
D+
8
USB20_P3_R
D-
7
USB20_N3_R
OE#
6
USB_CHG_EN#
<42> HP_R
<42> HP_L
<42> MIC1_L
<42> MIC1_R
<42> NBA_PLUG
<42> BACK_SENSE
1
R949
75K_0402_1%
C381
2
2
<43> USB_EN#
1
R568
2
100K_0402_5%
USB_EN#
B
eSATA/USB Conn
JESATA
PJDLC05C_SOT23-3
USB20_N3_RL
USB20_P3_RL
1
2
3
4
C385 1
C386 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_C_DRX_P5
SATA_PTX_C_DRX_N5
<28> SATA_PRX_C_DTX_N5
<28> SATA_PRX_C_DTX_P5
C387 1
C388 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N5
SATA_PRX_DTX_P5
5
6
7
8
9
10
11
VBUS
DD+
GND
GND
A+
AGND
BB+
GND
@
C426 1
W=60mils
USB
2
R190
@
1
0_0402_5%
C428 1
2 1000P_0402_50V7K
C389 1
2 0.1U_0402_16V4Z
SHIELD
SHIELD
SHIELD
SHIELD
L15
12
13
14
15
<32> USB20_N2
3
<32> USB20_P2
2
JUSB
3
2
4
4
1
1
USB20_N2_R
USB20_P2_R
WCM-2012-900T_0805
2
R191
@
2 220U_6.3V_M_R15
ESATA
FOX_3Q318111
1
0_0402_5%
2
R189
@
1
2
3
4
VCC
DD+
GND
@
GND
GND
GND
GND
5
6
7
8
ALLTOP C107L8-10405-L
1
0_0402_5%
L16
R950
51K_0402_1%
2
2
1
1
USB20_P3_RL
USB20_N3_R
3
3
4
4
USB20_N3_RL
D23
USB20_N2_R
2
USB20_P2_R
3
1
A
PJDLC05C_SOT23-3
SLP_CHG_M3
SLP_CHG_M4
LOW
D=1D
Mode 3
HIGH
LOW
HIGH
D=2D
Mode 4
LOW
HIGH
@
1
0_0402_5%
Issued Date
Compal Secret Data
200910/9
2010/01/23
Deciphered Date
Title
Size
Date:
4
@
WCM-2012-900T_0805
2
2
USB20_P3_R
2
R192
5
+USB_VCCB
+USB_VCCC
R952
43K_0402_1%
R951
51K_0402_1%
FUNCTION
C380
3
AO3413_SOT23
+5VALW
@
3
USB20_P3_S_O
USB20_N3_S_O
7
SN74CBT3125PWRG4_TSSOP14
C382
0.1U_0402_16V4Z
1
1
2
<28> SATA_PTX_DRX_P5
<28> SATA_PTX_DRX_N5
A
SLP_CHG
C379
1
1
GND
USB20_P3_S_O
3
USB20_N3_S_O
6
8 R131 1
2
11 100_0402_1%
1
+
1
2
VCC
1
C383
4.7U_0805_10V4Z
@
D18
1
14
1B
2B
3B
4B
Q8
0.1U_0402_16V4Z
1
2
1A
2A
3A
4A
2
+USB_VCCB
1OE#
2OE#
3OE#
4OE#
2
5
9
12
1
SLP_CHG# <43>
C
1000P_0402_50V7K
+USB_VCCC
USB_OC#1 <32,43>
@
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
USB Board@ Left Side
W=60mils
220U_6.3V_M_R15
Place U52 close to PCH
within 1200 mils
U53
USB20_P3_S
USB20_N3_S
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
JPIO
ACES_85201-2005N
2
0_0402_5%
+USB_VCCB
W=60mils
8
7
6
5
2
TS3USB221RSER_QFN10_2x1P5
1
4
10
13
<43> USB_CHG_EN#
1
2
3
4
RT9715BGS_SO8
9
2
USB20_N3
<32> SLP_CHG_M4
+USB_VCCB
U15
USB20_P3_S
<32> SLP_CHG_M3
2.5A
+5VALW
@
+5V_IO
USB20_N1_R
USB20_P1_R
2
0_0402_5%
WCM-2012-900T_0805
U52
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Add +5VALW and +5VL at DVT
L54
USB_OC#0 <32,43>
RT9715BGS_SO8
+3VALW
+USB_VCCB
W=60mils
+USB_VCCA
WCM-2012-900T_0805
eSATA/USB Combo
<32> USB20_N3
0_0402_5%
2
1
1
R88
<32> USB20_P3
@
L53
+
C369 1
C367 1
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
S
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
SANTA_191201-1
B
1
C354
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2
10U_0805_10V4Z
D
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
GND
GND
2
1
C352
Close to JHDD
JHDD
24
23
Place components closely ODD CONN.
1.1A
SANTA_206401-1_RV
C
D
2
G
2
1
SATA ODD Conn
2
1
2
Place closely JHDD SATA CONN.
1.2A
1
4
3
2
SATA-HDD/ODD/eSATA/USB
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
37
of
59
5
4
+3VS
2
1
MDC 1.5 Conn.
2
BlueTooth Interface
3
+3VS
3
2
1
+3VALW
Q28
AO3413_SOT23
BT@
+1.5VALW
1 MDC@ 2
R439
0_0603_5%
1
R440
@
+MDC_VCC
1
1
1
1
C392
C393
C394
C395
0.1U_0402_16V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
4.7U_0805_10V4Z
MDC@
MDC@
MDC@
MDC@
2
2
2
2
2
0_0603_5%
Reserve +1.5VALW for MDC
D
+BT_VCC
JMDC
(MAX=200mA)
Reverse JBT Pin Definition at DVT
2
1 BT@
2
R366
0_0402_5%
C397
0.1U_0402_16V4Z
BT@
<33> BT_RST#
USB20_P5
USB20_N5
BT_RESET#
BT_DET#
<32> USB20_P5
<32> USB20_N5
<33> BT_DET#
8
7
GND
GND
6
5
4
3
2
1
6
5
4
3
2
1
1
3
5
7
9
11
<28> AZ_SDOUT_MD
@
<28> AZ_SYNC_MD
<28> AZ_SDIN1_MD
<28> AZ_RST_MD#
2 MDC@ 1 AZ_SDIN1_MD_R
R369
33_0402_5%
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
2
4
6
8
10
12
+MDC_VCC
+3VALW
AZ_BITCLK_MD <28>
2
BT@
C399
0.1U_0402_16V4Z
GND
GND
GND
GND
GND
GND
JBT
1
BT@
C398
4.7U_0805_10V4Z
R368
10_0402_5%
ACES_88018-124G
13
14
15
16
17
18
+BT_VCC
@
1
1
D
1
1 BT@
2
R362
47K_0402_5% 1
C390
0.01U_0402_25V7K
BT@
2
G
<33,39> BT_PW R#
2
D
C396
0.1U_0402_16V7K
BT@
S
R361
100K_0402_5%
1
ACES_87213-0600G_6P
Connector for MDC Rev1.5
C400
10P_0402_50V8J
2
For EMI
2
2
G
Q34
<28> FELICA_PW R
1
1
C758
0.1U_0402_16V4Z
FELICA@
1
2
3
4
5
6
7
8
USB20_N9
USB20_P9
<32> USB20_N9
<32> USB20_P9
2
1
1
CB5
TV@
1U_0402_6.3V4Z
3
2
2
2
R419
FELICA@
C479
100K_0402_5%
FELICA@
0.1U_0402_16V7K
1
FELICA@
1
2
2
R403 47K_0402_5% 2
C403
D
0.01U_0402_25V7K
FELICA@
1
S 2N7002_SOT23-3
FELICA@
FELICA@
C414
0.1U_0402_16V4Z
Q20
AO3413_SOT23
FELICA@
R132
0_0603_5%
FELICA@
@
1
2
3
4
5
6
G1
G2
ACES_87151-06051
2
2
CB3 TV@
4.7U_0603_6.3V6K
+5VS_L_BCAS
LB1 TV@
1
2
1 FBMA-L11-201209-221LMA30T_0805
1
3
1
TV@ RB8
2.2K_0402_5%
2
1
CB4
TV@
0.1U_0402_16V4Z
2
+5VS_L_BCAS
1
TV@ RB7
10K_0402_5%
JFEL
+FLICA_VCC
+5VS_BCAS
1
4
1
5
+3VS
QB1
AO3413_SOT23
TV@
3
1
2
3
G
2
47K_0402_5%
1
TV@
QB2B
TV@
TV@
CB2
2
0.01U_0402_25V7K
2N7002DW -T/R7_SOT363-6
<39> BCPW ON
1
G
2
RB5
2
+3VS
D
TV@RB2
TV@
RB2
C
current = 0A
S
Inrush
1 TV@
CB1
0.1U_0402_16V7K
100K_0402_5%
BCPW ON
Felica
+5VS
+5VALW
D
B-CAS Circuit
S
C
+FLICA_VCC
5
+5VS_L_BCAS
IN1
BCRSTM 2
IN2
O
4
G
<39> BCRSTM
UB1 TV@
P
1
B
B_R_BCRST 1 TV@
RB9
B_BCRST
2
100_0402_5%
B
B_BCRST <39>
3
5
Finger printer
<39> XBCLKM
IN1
2
IN2
UB2 TV@
P
1
O
4
G
XBCLKM
B_R_XBCCLK1 TV@
RB11
B_XBCCLK
2
100_0402_5%
B_XBCCLK <39>
JFP
+3VS
1 R134
2
0_0603_5% 1
FP@
C480
0.1U_0402_16V4Z
FP@
2
+3VS_FP
USB20_N8
USB20_P8
<32> USB20_N8
<32> USB20_P8
+5VS_L_BCAS
A
<39> CPLGP1
CPLGP1
BCIO
BCIO <39>
C
4
VIN
IO1
2
3
IO2 GND
1
CM1293A-02SR SOT143-4
For ESD
A
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
5
P-TW O_161011-04021
2
3
2
B
1
2
RB14
TV@
1.5K_0402_5%
QB2A
TV@
2
2N7002DW -T/R7_SOT363-6
2
1
RB13 TV@
10K_0402_5%
1
10K_0402_5%
6
TV@
2
R133
0_0603_5%
FP@
FP@
@
1
2
3
4
GND
GND
1
RB1
1
+5VS_L_BCAS
D82
1
2
RB12
TV@
E
10K_0402_5%
QB4 TV@
2SB1197K_SOT23-3
1
2
3
4
5
6
1
3
4
3
2
Title
BT/FP/B-CAS/Felica/MDC
Size
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
1
38
of
59
2
1
1
2
2
1
Disable
BT_CRTL
H
L
BT_PWR#
L
H
+1.5VS
PCIE--JET
<29> CLK_JET#
<29> CLK_JET
**If +3V_WLAN is +3VS, please
remove D24
<38> BCRSTM
<38> BCPWON
<29> PCIE_PRX_JETTX_N4
<29> PCIE_PRX_JETTX_P4
D24
CM3
C253
CM7
CM8
47P_0402_50V8J
2
@
4.7U_0805_10V4Z
0.01U_0402_25V7K
2
0.01U_0402_25V7K
2
1
Q36
3
1
1
1
1
<29> PCIE_PTX_C_JETRX_N4
<29> PCIE_PTX_C_JETRX_P4
D
2
G
<33,38> BT_PWR#
0.1U_0402_16V4Z
1
2
CM2
2
BT_CTRL
2
For SED
S 2N7002_SOT23-3
+3VS
CM9
C254
47P_0402_50V8J
@
4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z
CM1
1
+1.5VS
For SED
1
SUSP#
40 mils
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
BCCDET
<29> CLKREQ_JET#
Short PJ27 for Wimax
Short PJ26 for WLAN
1
B-CAS
<38> XBCLKM
1
PJ26@ JUMP_43X79
+3V_WLAN
J3G
+3V_WLAN
PJ27@ JUMP_43X79
+3VS
BT
on module
Enable
2
<43> TMPTU2_SXP
Add BT_CTRL for WLAN & BT
Combo module at DVT
+1.5VS
<29> PCIE_PRX_WLANTX_N2
<29> PCIE_PRX_WLANTX_P2
<29> PCIE_PTX_C_WLANRX_N2
<29> PCIE_PTX_C_WLANRX_P2
WLAN/ WiFi
+3V_WLAN
1
1R16
<43> E51_TXD
<43> E51_RXD
R17
2
0_0402_5%
2
0_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
GND1
Debug card using
GND1
GND2
2
C255
47P_0402_50V8J
@
4.7U_0805_10V4Z
2.75A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
CM6
2
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
COMMON
ISDBT_DET
ISDBT_DET <33>
RF_OFF#
RF_OFF# <33>
PLT_RST#
USB20_P10_TV 1 R126
2 TV@ 0_0402_5%
USB20_N10_TV 1
2 TV@ 0_0402_5%
R135
R72 1 3G@
PM_SMBCLK
2 0_0402_5%
R85 1 3G@
PM_SMBDATA
2 0_0402_5%
USB20_N12 <32>
USB20_P12 <32>
RM3
1 3G@
0_0402_5%
UIM_VPP
2
COMMON
1 TV@
RM7
USB--TV#2
BCIO
2
0_0402_5%
Close to J3G
1 TV@
+5VS_BCAS
USB--3G/TV#1
RM4
1 3G@
+UIM_PWR
LED_WIMAX#
CPLGP1
CPLGP1 <38>
TMPTU1_SXP <43>
RM1
1 3G@
UIM_RESET
RM5
B-CAS
1 TV@
B_BCRST
<38> B_BCRST
RM8
UIM_CLK
1 TV@
1 3G@
RM9
RM10
+UIM_PWR
470_0402_5%
1 TV@
B_XBCCLK
<38> B_XBCCLK
2
R307
1 3G@
UIM_DATA
RM11
BCIO
WL_OFF# <43>
PLT_RST# <32,40,41,43,44>
PLT_RST#
J3GSIM
+VCC_SIM
SIM_RESET
SIM_CLK
PM_SMBCLK <11,12,25,29>
PM_SMBDATA <11,12,25,29>
USB20_N13 <32>
USB20_P13 <32>
LED_WIMAX#
WiMax
2
DM1
RLZ20A_LL34
3G@
LED_WIMAX# <45>
1
RM6
2
100K_0402_5%
WIMAX@
1
2
3
7
1
CM13
0.1U_0402_16V4Z
3G@
1
1
CM15
10P_0402_50V8J
3G@ 2
+VCC_SIM
2
0_0603_5%
2
0_0603_5%
SIM_RESET
2
0_0402_5%
2
0_0402_5%
54
Add BCCDET pull down
BCCDET
BCIO <38>
USB20_P10 <32>
USB20_N10 <32>
FOX_AS0B226-S40N-7F
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
For SED
1
1 TV@
RM12
1
<29> CLK_WLAN#
<29> CLK_WLAN
53
2
GND
VPP
I/O
NC
NC
SIM_CLK
2
0_0402_5%
2
0_0402_5%
SIM_DATA
2
0_0402_5%
2
0_0402_5%
RM2
4.7K_0402_5%
@
@
VCC
RST
CLK
4
5
6
UIM_VPP
SIM_DATA
1
1
BT_CTRL
<29> CLKREQ_WLAN#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CM5
0.01U_0402_25V7K
@
1
+3V_WLAN
@
2
JWLAN
CM4
+3VS
1
2
2
+3VALW
BT
on module
120 mils
0.1U_0402_16V4Z
TV tuner
1
Slot 1 Half PCIe Mini Card-WLAN/ WiMax
+3VS
Slot 2 Full PCIe Mini Card- 3G/ TV Tuner
Add +1.5VS for
Half PCIe Mini Card- JET
MC770A at PVT
2
WLAN&BT Combo module circuits
8
MOLEX_47273-0001~D
2
CM16
10P_0402_50V8J
2 3G@
CM14
22P_0402_50V8J
@
+3VS
54
GND2
FOX_AS0B226-S40N-7F
+3VALW_CARD
+3VS_CARD
Imax = 0.275A
1
+3VALW
NEW@
1
RN4
2
2 CP_USB#
CN1
10U_0805_10V4Z
NEW@
1
2
+1.5VS_CARD
Imax = 1.35A
CN2
0.1U_0402_16V4Z
NEW@
1
2
Imax = 0.75A
1
CN3
10U_0805_10V4Z
NEW@
2
CN4
0.1U_0402_16V4Z
NEW@
1
2
CN5
10U_0805_10V4Z
NEW@
JEXP
1
2
CN6
0.1U_0402_16V4Z
NEW@
USB20_N4_R
USB20_P4_R
CP_USB#
100K_0402_5%
UN1
12
14
+1.5VS
NEW@
1.5Vin
1.5Vin
1.5Vout
1.5Vout
3.3Vin
3.3Vin
3.3Vout
3.3Vout
PM_SMBCLK
PM_SMBDATA
40mils
11
13
+1.5VS_CARD
+1.5VS_CARD
<30,40> EC_SWI#
+3VALW_CARD
60mils
2
4
+3VS
17
+3VALW
PLT_RST#
+3VS
1
RN6
10K_0402_5%
@
1
5
D
3
2
G
S
A
G Vcc
B
3
1
1
RCLKEN
UN2
@
2
2
2
CLKREQ#
SUSP#
1
<43,46,49,52,56>
+3VS
RN7
10K_0402_5%
@
<43,53> SYSON
+3VS
Y
2
4
CN7
0.1U_0402_16V4Z
@
CLKREQ_NEW#
CLKREQ_NEW#
<29>
6
SYSON
20
SUSP#
1
EXP_CPPE#
10
CP_USB#
9
RCLKEN
18
AUX_IN
SYSRST#
SHDN#
AUX_OUT
OC#
PERST#
STBY#
NC
CPPE#
GND
CPUSB#
Thermal_Pad
RCLKEN
TPS2231MRGPR-2 QFN
3
5
+3VS_CARD
15
+3VALW_CARD
<32> EXP_CPPE#
<29> CLK_NEW#
<29> CLK_NEW
19
8
Reserve for EMI request
PERST#
R125
0_0402_5%
7
<32> USB20_P4
1
<32> USB20_N4
4
L56
@
1
2
4
3
CLKREQ#
EXP_CPPE#
<29> PCIE_PRX_NEWTX_N3
<29> PCIE_PRX_NEWTX_P3
1 NEW@ 2
16
21
PERST#
+3VS_CARD
20mils
2
USB20_P4_R
3
USB20_N4_R
<29> PCIE_PTX_C_NEWRX_N3
<29> PCIE_PTX_C_NEWRX_P3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
WCM-2012-900T_0805
@
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
GND
GND
29
30
SANTA_130801-5_NR
NC7SZ32P5X_NL_SC70-5
1 NEW@ 2
Q27
2N7002_SOT23-3
@
R124
1
RN8
2 CLKREQ_NEW#
0_0402_5%
Issued Date
Compal Secret Data
NEW@
CLKREQ#
0_0402_5%
200910/9
Deciphered Date
2010/01/23
Title
Size
Date:
PCIe-WLAN/JET/3G/TV/NewCard
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
39
of
59
A
B
C
UL1
<29> PCIE_PRX_C_LANTX_P1
CL1
1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1
22
HSOP
<29> PCIE_PRX_C_LANTX_N1
CL2
1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1
23
HSON
17
18
<29> PCIE_PTX_C_LANRX_P1
<29> PCIE_PTX_C_LANRX_N1
+3V_LAN
PCIE_PTX_C_LANRX_P1
PCIE_PTX_C_LANRX_N1
D
8111E@
LED3/EEDO
LED1/EESK
LED0
31
37
40
HSIP
HSIN
EECS/SCL
EEDI/SDA
30
32
CLKREQB
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
+LAN_VDD10
+3V_LAN
LAN_SK_LINK#
LAN_ACTIVITY#
RL2 2
RL1 2
LL1,CL13 will be changed to
2.2uH&4.7uF after EVT test
1 10K_0402_5%
1 10K_0402_5%
EC_SWI#
2
100K_0402_5%
RL19
<29> CLKREQ_LAN#
1
<32,39,41,43,44> PLT_RST#
<29> CLK_LAN
<29> CLK_LAN#
0_0402_5% 16
PLT_RST#
25
PERSTB
CLK_LAN
CLK_LAN#
19
20
REFCLK_P
REFCLK_N
LAN_X1
43
CKXTAL1
LAN_X2
44
CKXTAL2
EC_SWI#
28
LANW AKEB
ISOLATEB
26
ISOLATEB
DVDD33
DVDD33
27
39
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
1
+3VS
Pin14
RTL8111E
NC
<30,39> EC_SWI#
NC
Pin15
NC
Pin38
1K ohm Pull-high
2
RTL8105E
RL6
1K_0402_1%
10K ohm PD
RL7
15K_0402_5%
+3V_LAN
RL21 2 8111E@ 1 10K_0402_5%
RL22 1
2 1K_0402_5%
ENSWREG
+LAN_VDDREG
1
RL5
2
2.49K_0402_1%
2
33
ENSW REG
34
35
VDDREG
VDDREG
46
RSET
24
49
+LAN_VDD10
LL1
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
@
1
RL3
E
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-
1
2
2
1
CL9
0.1U_0402_16V4Z
1
2
CL10
2
CL4
1
2
0.1U_0402_16V4Z
CL5
1
2
0.1U_0402_16V4Z
CL6
1
2
0.1U_0402_16V4Z
CL7 8111E@
CL7 close to pin12
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
+LAN_VDD10
+LAN_EVDD10
2
0_0603_5%
CL18
1U_0402_6.3V4Z
+3V_LAN
+3V_AVDDXTAL
1
LL2
1
2
2
CL17
0.1U_0402_16V4Z
1
Close to Pin 3,6,9,13,29,41,45
+LAN_VDD10
Close to Pin 21
1
GND
PGND
+3V_LAN
Close to Pin 27,39,12,47,48
Layout Note: LL1 must be
within 200mil to Pin36,
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
EVDD10
21
+LAN_EVDD10
0.1U_0402_16V4Z
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
0.1U_0402_16V4Z
REGOUT
36
2
CL19
2
CL20
2
CL21
2
CL22
2
CL23
2
CL24
2
CL25
1
1
0.1U_0402_16V4Z
+3V_LAN
1
+LAN_VDDREG
0.1U_0402_16V4Z
+LAN_REGOUT
1
60 mils
2
0_0603_5%
RTL8111E-GR_QFN48_6X6
0.1U_0402_16V4Z
1
LL3
CL28
4.7U_0603_6.3V6K
+3VALW TO +3V_LAN
1
1
2
2
CL29
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
2
8111E@
8111E@
8111E@
CL23,CL24,CL25 close to pin6,9,41, respectively
+3VALW
+3V_AVDDXTAL
RL8
1
RL9
@ 0_0402_5%
C483
0.1U_0402_16V7K
1
2
2
PJ29
JUMP_43X79
@
+3V_LAN
C681
4.7U_0805_10V4Z
@
LAN Conn.
JLAN
LAN_ACTIVITY#
YL1
LAN_X1
2
1
2
RL23
0_0402_5%
@
LAN_X2
25MHZ_20PF_7A25000012
C682
1U_0402_6.3V4Z
1
CL27
27P_0402_50V8J
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
24
23
22
LAN_MDI2LAN_MDI2+
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
LAN_MDI1LAN_MDI1+
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
LAN_MDI0LAN_MDI0+
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
UL1
Place CL34 colse
to LAN chip
2
2
CL39 1000P_0402_50V7K
2
1
1 8111E@ 2
8111E@
RL11
75_0402_1%
CL40 1000P_0402_50V7K
2
1
1 8111E@ 2
8111E@
RL12
75_0402_1%
CL41
2
CL42
2
1000P_0402_50V7K
1
1
2
RL13
75_0402_1%
1000P_0402_50V7K
1
1
2
RL15
75_0402_1%
RJ45_MIDI3RJ45_MIDI3+
LAN_SK_LINK#
2 RL14
1
150_0402_5%
Yellow LED-
2
1
11
RL17 150_0402_5%
RJ45_MIDI38
Yellow LED+
7
PR4+
RJ45_MIDI1-
6
PR2-
RJ45_MIDI2-
5
PR3-
RJ45_MIDI2+
4
PR3+
RJ45_MIDI1+
3
PR2+
RJ45_MIDI0-
2
PR1-
RJ45_MIDI0+
1
PR1+
LAN_SK_LINK#_R
1
10
Green LED-
9
Green LED+
RL18 150_0402_5%
SHLD2
14
SHLD1
13
SUYIN_100073FR012G101ZL
RJ45_GND
1
CL36
LANGND
2 1000P_1808_3KV7K
1
2
1
CL37
0.1U_0402_16V4Z
2
CL38
4.7U_0603_6.3V6K
4
Compal Secret Data
2009/10/05
2010/01/23
Deciphered Date
Title
PCIe-LAN-RTL8105E/8111E
Custom
Date:
B
3
CL34
0.1U_0402_25V4K
Issued Date
A
PR4-
RJ45_MIDI3+
2
+3V_LAN
@
12
SUPERWORLD_SWG150401
10/100M transformer
8105E@
+3V_LAN
LAN_ACTIVITY#_R
RJ45_GND
1
UL4
RL10 1
150_0402_5%
8111E@
1
2
3
8105E 10/100M
8105E@
2
1
CL26
27P_0402_50V8J
2
2
LAN_MDI3LAN_MDI3+
4
RL4
0_0402_5%
ENSWREG
UL4
For P/N and footprint
Please place them to ISPD page
CL11
0.1U_0402_16V4Z
CL11 close to pin42
1
1
3
+3V_LAN
1
1
AO3413_SOT23
C482
0.01U_0402_25V7K
1
G
2
D
2
47K_0402_5%
3
Q51
2
S
2
1
R432
1
+LAN_VDD10
Reserved For 1.05V Crystal
Vgs=-4.5V,Id=3A,Rds<97mohm
2
2
1
R147
100K_0402_5%
<43> WOL_EN#
+3V_LAN
0_0402_5%
+3VALW
C
D
Rev
2.0
NWQAA LA-6062P M/B
Sheet
E
40
of
59
5
4
3
2
1
+1.8VS_OUT CC3 close to pin 5
+3VALW
D3E mode
1
CC2 close to CC3
CC1 is near CC3
D
2
1
CC4
2
RC5
10K_0402_5%
CC4 close to pin 10
+3VS
UC2
CLK_CR#
CLK_CR
<29> CLK_CR#
<29> CLK_CR
PCIE_PTX_C_CRRX_N5
PCIE_PTX_C_CRRX_P5
<29> PCIE_PTX_C_CRRX_N5
<29> PCIE_PTX_C_CRRX_P5
CC8
CC9
<29> PCIE_PRX_C_CRTX_N5
<29> PCIE_PRX_C_CRTX_P5
1
1
2
2
PCIE_PRX_CRTX_N5
PCIE_PRX_CRTX_P5
0.1U_0402_16V7K
0.1U_0402_16V7K
2
RC3
12K_0402_1%
JMB389@
RC3
9.1K_0402_1%
JMB385@
APREXT
1
3
4
APCLKN
APCLKP
9
8
APRXN
APRXP
11
12
APTXN
APTXP
7
12mil
+SEL43
43
39
JMB389@
APVDD
APV18
NC/TAV33
5
10
36
DV33
DV33
DV33
DV18
DV18
19
20
44
18
37
MDIO0
MDIO1
MDIO2
MDIO3
MDIO6/4
MDIO5
G/MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
48
47
46
45
41
42
24
40
29
28
27
26
25
23
22
APREXT
SDDV/MDIO4
TXIN/NC
JMB389
<32,39,40,43,44>
RC4
PLT_RST#
RC4
0_0402_5%
JMB385@
JMB389@
1
2 100_0402_5%
1
CC13
0.1U_0402_16V4Z
JMB389@
2
+3VS
C
1
2
CPPE#
XD_CD#
13
14
MS_CD#
SD_CD#
JMB385@
2
4.7K_0402_5%
JMB385@2
4.7K_0402_5%
2
4.7K_0402_5%
JMB385@
1
RC27
1
RC29
1
RC32
SD_CD#
XRSTN
XTEST
CPPE_N
CR1_CD2N
15
16
CR1_CD1N
CR1_CD0N
17
CR1_PCTLN
40 mils
+VCC_OUT
MS_CD#
XD_CD#
CR_LED
21
RC11
22_0402_5%
JMB389@
NC/SPI_SCK
NC/SPI_CSN
NC/SPI_SO
NC/SPI_SI
30
33
34
35
APGND
NC/GND
NC/GND
NC/GND
6
31
32
38
GND
49
+TVA33
place near
JMB389@
1
RC19 0_0402_5% CC5
1
2
1
CC6
40mil
1
CC7
pin 19,20 and 44
<28> CR_CPPE#
RC31
1
0_0402_5%
CPPE#
2
<28> CR_W AKE#
RC6
1
0_0402_5%
SD_CD#
2
2
1
JMB389@
CC12
0.1U_0402_16V4Z
CC12 close to pin 36
Power On Strapping setting
20mil
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SEL41
SDCLK_MSCLK_XDCE#
SEL24
XD_CLE
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE
2
CC11
1
1
2
10U_0805_10V4Z
Description
Pin name
CC11 close to pin18
For intenal LDO's usage
MDIO7
CC10
0.22U_0402_6.3V4K
MDIO14
CC10 close to pin37
High
low
on-board★
add-in card
CR_LED
high active
CR_LED
low active★
+3VS
XD_CLE
SEL33
MDIO7
XD_ALE
CR1_LEDN
D
+TVA33
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+1.8VS_OUT
2
2
1
CC3
0.1U_0402_16V4Z
JMB389C / JMB385C
1
CC2
1000P_0402_50V7K
2
0.22U_0402_6.3V4K
1
CC1
10U_0805_10V4Z
20mil
MDIO14
1
RC28
1
RC26
2
C
10K_0402_5%
2
@
1
RC25
10K_0402_5%
2
200K_0402_5%
JMB389-QGAZ0C_QFN48_7X7
place 6 GND vias on T-pad
RC12
22_0402_5%
JMB389@
+VCC_OUT
2
RC7
1
RC9
2
RC30
JMB385@
UC2
JMB385-QGAZ0C
JMB385@
JMB385@
RC14
SD_CLK
RC13
22_0402_5%
JMB389@
XDW P#_SDW P#
1
10K_0402_5%
XD_RB#
2
1K_0402_5%
SDCMD_MSBS_XDW E#
1
10K_0402_5%
SDCLK_MSCLK_XDCE#
B
JMB385@
2 FBMA-10-100505-121T_0402
JMB385@
2 FBMA-10-100505-121T_0402
JMB385@
RC13 1
2 FBMA-10-100505-121T_0402
RC11 1
SD_CLK
RC12 1
MS_CLK
1
2
JMB385@
CC19
1
2
SEL33
RC18
0_0402_5%
1
2
JMB385@
100P_0402_50V8J
JMB385@
CC20
1
2
SEL24
RC1
1
MS_CLK
100_0402_5%
JMB385@
RC15
1
2
XD_CE#
100_0402_5%
100P_0402_50V8J
JMB385@
JMB385@
RC16
CC21
1
2
1
2
XD_CE#
100_0402_5%
Reserved for EMI,close to UC1.42
RC21
0_0402_5%
1
2
JMB389@
@ CC22
2
1
CC23
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
XD_CD#
B
+VCC_OUT
40 mils
CC17
10U_0805_10V4Z
CR_LEDCON#
A
2
2
CR_LEDCON#
CC18
0.1U_0402_16V4Z
<45>
33
XD_CD#
34
XD_RB#
1
XD_RE#
2
XD_CE#
3
XD_CLE
4
XD_ALE
5
SDCMD_MSBS_XDW E# 6
XDW P#_SDW P#
7
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
8
9
26
27
28
30
31
32
XD-VCC
XD-CD-SW
XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
MS-VCC
MS-SCLK
MS-INS
MS-BS
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
14
15
17
21
19
20
18
16
MS_CLK
MS_CD#
SDCMD_MSBS_XDW E#
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SD-VCC
SD-CLK
SD-CMD
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-WP-SW
SD-CD-SW
23
24
12
25
29
10
11
35
36
SD_CLK
SDCMD_MSBS_XDW E#
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDW P#_SDW P#
SD_CD#
4in1-GND
4in1-GND
4in1-GND
4in1-GND
13
22
37
38
RC8
1 0_0402_5%
D
+VCC_OUT
+SEL43
RC20
0_0402_5%
1
2
JMB385@
JMB389@
CC16
2.2U_0603_6.3V6K
1
2
+VCC_OUT
CC16 close to pin43
For internal LDO in SD3.0
A
TAITW _R015-211-LM-A_NR
CR_LED
2
2
G
S
3
Confirm sinking 16mA
Compal Secret Data
RC10
4.7K_0402_5%
@
200910/9
Issued Date
1
QC1
2N7002_SOT23-3
@
1
1
2
1
RC22
0_0402_5%
1
2
JMB385@
RC23
0_0402_5%
SDCMD_MSBS_XDW E#
1
2
JMB389@
@
@
2
Reserved for EMI,close to JREAD
5 in 1 Card Reader
JREAD
XDW P#_SDW P#
100P_0402_50V8J
SEL41
SD_CD#
0_0402_5%
2
JMB385@
Deciphered Date
2010/01/23
Title
Custom
Date:
5
Card Reader JMB385/389
4
3
2
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
41
of
59
4
3
+PVDD1
CA57
2
1
CA1
RA1
1
CA19
@ 10U_0805_10V4Z
2
MIC1_LINE1_R_R
CA10 1
0_0402_5%
CA9
1
2
1
0_0603_5%
CA60
@
@
0.1U_0402_16V4Z
+5VALW
1
1
CA59
CA58
@
@
2
10U_0805_10V4Z
2
2
10U_0805_10V4Z
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
+5VALW
0_0603_5%
4.7U_0805_10V4Z
<25> INT_MIC_DATA
<43> EC_MUTE#
For EMI
CA22
CA11
0.01U_0402_25V7K
@
1
CA12
CA20
RA14 @ 10U_0805_10V4Z
2
2
1
0_0603_5%
RA15
2
1
0_0603_5%
1
SPKLSPKR+
CA25
@ 10U_0805_10V4Z
2
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
CA50 1
2 0.1U_0603_50V7K
2
FBMH1608HM601-T
38
AVDD2
45
44
SPKR+
SPKR-
21
22
MIC1_L
MIC1_R
HP_OUT_L
HP_OUT_R
32
33
MIC2_L
MIC2_R
4
PD#
11
12
RESET#
SENSE A
18
SENSE B
36
35
CBP
CBN
CA26
RA16 @ 10U_0805_10V4Z
2
2
1
0_0603_5%
SPKR-
close to chip
75_0402_1%
RA5
75_0402_1%
HP_L <37>
10
AZ_SYNC_HD
BCLK
6
AZ_BITCLK_HD
SDATA_OUT
5
SDATA_IN
8
AZ_SDOUT_HD
AZ_SDIN0_HD_R
AZ_SYNC_HD
<28>
AZ_BITCLK_HD
<28>
47
48
MONO_OUT
20
MIC2_VREFO
29
MIC1_VREFO_R
LDO_CAP
30
28
VREF
27
AC_VREF
1
33_0402_5%
@
AZ_SDIN0_HD
SPK_R1
MIC1_VREFO_L
JDREF
19
PVSS2
PVSS1
DVSS2
DVSS1
CPVEE
34
CPVEE
1
CA14
AVSS1
AVSS2
26
37
3
PESD5V0U2BT_SOT23-3
SPK_R2
CA13
1
2
MONO_IN
C
0.1U_0402_16V4Z
Change to AGND for
high frequency noise issue
Ext.MIC/LINE IN JACK
1 20K_0402_1%
RA33
2 RA31
1
1K_0402_5% 2.2K_0402_5%
2
1
MIC1_LINE1_R_L
1
2
2.2U_0603_6.3V4Z
CA17
2
0.1U_0402_16V4Z
CA18
0.1U_0402_16V4Z
2
2
1
1K_0402_5%
RA32
1
CA16
10U_0805_10V4Z
2 @
+MIC1_VREFO_R
MIC1_R <37>
MIC1_L <37>
RA29 1
2
2.2K_0402_5%
+MIC1_VREFO_L
B
ALC269Q-VB5-GR _QFN48_7X7
MIC_SENSE
place close to chip
DGND
RA42
100K_0402_5%
@
CA27
1U_0402_6.3V4Z
@
1
MIC1_LINE1_R_R
43
42
49
7
ACES_85204-0400N
@
@
2
1
1
2
3
4
1
RA12
10K_0402_5%
CA23 10U_0805_10V4Z
1
2
+MIC1_VREFO_R
31
1
2
3
4
DA6
2
RA8
1
2
47K_0402_5%
<28>
CA29
1
1
2 @
RA17
10P_0402_50V8J
AZ_BITCLK_HD 2
10_0402_5%
AC_JDREF2 RA9
SPK_L1
SPK_L2
SPK_R1
SPK_R2
AZ_SDOUT_HD <28>
2
RA6
For EMI
EAPD
SPDIFO
D
JSPK
SPK_L2
RA7
1
2
47K_0402_5%
PCI Beep
HP_R <37>
3
PESD5V0U2BT_SOT23-3
Beep sound
EC Beep
<43> EC_BEEP#
RA4
SYNC
PCBEEP
13
CA6
<28,31> PCH_SPKR
EC_MUTE#
+5VALW
25
SPK_OUT_R+
SPK_OUT_R-
GPIO1/DMIC_CLK
1
2
INT_MIC_CLK_R
CA15
FBMA-10-100505-301T
2.2U_0603_6.3V4Z
CAM@
1
+MIC1_VREFO_L
CA28
27P_0402_50V8J
@
2
AVDD1
46
39
PVDD2
LINE2_L
LINE2_R
16
17
1
1
AGND
6
CA48 1
1
@
2
CA24
1U_0402_6.3V4Z
@
QA1A
RA28
Add RA42 at DVT
EC_MUTE#
RA22 2
2N7002DW -T/R7_SOT363-6
1 4.7K_0402_5%
100K_0402_5%
2
1
2 0.1U_0603_50V7K
14
15
GPIO0/DMIC_DATA
RA41
<25> INT_MIC_CLK
SPKL+
SPKL-
3
For EMI
CA5
40
41
2
SENSE_A
CA4
1
2
2
2
2
place
10U_0805_10V4Z 0.1U_0402_16V4Z
SPK_OUT_L+
SPK_OUT_L-
INT_MIC_CLK_R
MONO_IN
2
100P_0402_50V8J
CA3
1
LINE1_L
LINE1_R
INT_MIC_DATA
AZ_RST_HD#
<28> AZ_RST_HD#
UA1
1
23
24
2
1U_0402_6.3V4Z
RA37
4.7U_0805_10V4Z
CA21
2
1
0_0402_5% MIC1_LINE1_R_L
@
MIC1_LINE1_R_R
2
1
10/9 Add RA30,RA35~RA39
for AMP gain Test
RA44
100K_0402_5%
@
DA7
2
1
1U_0402_6.3V4Z
1
2
PVDD1
Change CA9 and CA10
to 1U at pre-MP
9
1
RA30
0_0402_5%
@
RA38
0_0402_5%
SPK_L1
1
1
0_0402_5%
RA39
1
RA18
RA13
2
1
0_0603_5%
2
10U_0805_10V4Z
1
68 mA
DVDD
0_0402_5%
B
2
RA35
Ext. Mic/LINE IN
CA47 1
2
CA7
10U_0805_10V4Z
2
2
MIC1_LINE1_R_L
C
2
10U_0805_10V4Z
SPKL+
place close to chip
+PVDD2
1
0.1U_0402_16V4Z
CA61
+AVDD
2
DVDD_IO
RA36
2
placement near Audio Codec
+5VALW
RA11
35 mA
1
CA8
0.1U_0402_16V4Z
1
1
CA44
CA43
+3VS_DVDD
0.1U_0402_16V4Z
2
1
FBMH1608HM601-T
+3VS
1
10U_0805_10V4Z
2
2
place close to chip
D
1
1
1
CA2
JA1
JUMP_43X39
@
0.1U_0402_16V4Z +DVDD_IO
2
1
FBMH1608HM601-T
+3VS
1
CA56
1
RA20
RA2
2
1
0_0603_5%
600 mA0.1U_0402_16V4Z
RA19 @
2
1
0_0603_5%
+1.5VS
2
Speaker Connector
2
5
Add RA43 for S/M battery mode at PVT
Codec Signals
Function
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
MIC_SENSE
SENSE A
A
SENSE B
5.1K
(PIN 48)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
2
RA10
1
20K_0402_1%
5
RA34
+3VALW
100K_0402_5%
@
100K_0402_5%
<43> SM_SENSE#
SENSE_A
QA1B
5
BACK_SENSE <37>
2N7002DW -T/R7_SOT363-6
<37> NBA_PLUG
RA21
39.2K_0402_1%
200910/9
PORT-H (PIN 20)
Deciphered Date
2010/01/23
4
3
A
Compal Secret Data
Issued Date
10K
RA43
+3VL
place close to chip
3
Impedance
4
Sense Pin
2
Title
HDA CODEC ALC269
Size
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
1
42
of
59
5
4
3
2
1
+3VL
+3VL
C438
C440
C441
1000P_0402_50V7K
1
1
1000P_0402_50V7K
U19
C439
2
2
0.1U_0402_16V4Z
2
<33> GATEA20
<33> KB_RST#
<28,44> SERIRQ
<28,44> LPC_FRAME#
<28,44> LPC_AD3
<28,44> LPC_AD2
<28,44> LPC_AD1
<28,44> LPC_AD0
1
2
<32> CLK_PCI_EC
<32,39,40,41,44> PLT_RST#
R378
47K_0402_5%
2
1
2
C444
<33> EC_SCI#
<45> W L_BT_LED#
ECRST#
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
W L_BT_LED#
12
13
37
20
38
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
1
0.1U_0402_16V4Z
+3VL
1
R380
1
R382
2
47K_0402_5%
2
47K_0402_5%
KSO1
KSO2
to avoid EC entry ENE test mode
C
KSI[0..7]
<44,45> KSI[0..7]
KSO[0..17]
<44,45> KSO[0..17]
RP7
1
2
3
4
+3VL
+3VS
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<27,48>
<27,48>
<14,29,44,45>
<14,29,44,45>
2.2K_0804_8P4R_5%
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<33> EC_SMI#
<33> THM_ALT#
<45> ESB_CK
<45> ESB_DAT
<30> PCH_SUSPW RDN
<25> INVT_PW M
<6> FAN_SPEED1
<44> HDPLOCK
<39> E51_TXD
<39> E51_RXD
<45> ON/OFFBTN#
<45> PW R_SUSP_LED#
<44> NUM_LED#
For EMI
@
PLT_RST#
2
180P_0402_50V8J
1
C819
@
B
1
C820
SUSP#
2
180P_0402_50V8J
CRY1
CRY2
63
64
65
66
75
76
BATT_TEMPA
TMPTU1_SXP
ADP_I
ADP_V
TMPTU2_SXP
HDPACT
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
VTTP_EN
EN_DFAN1
IREF
CHGVADJ
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
Interface
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
USB_CHG_EN#
HDPINT
TP_CLK
TP_DATA
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
VGATE
W OL_EN#
PW RME_CTRL#
LID_SW #
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK
SPI_CS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
CIR_IN
CAP_INT#
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW _LED#
PW R_ON_LED#
SYSON
VR_ON
ACIN_D
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
EC_RSMRST#
EC_LID_OUT#
EC_ON
TP_LED
PM_PW ROK
BKOFF#
W L_OFF#
CAP_RST#
LOGO_LED
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
CEC_INT#
EC_ENBKL
USB_OC#1
SLP_CHG#
SUSP#
PBTN_OUT#
USB_OC#0
V18R
124
PS2
IN1
<30> PM_SLP_S4#
2
IN2
SPI Flash ROM
SM Bus
GPI
XCLK1
XCLK0
11
24
35
94
113
U44
4
SLP_S5#
CAP_INT#
1
R172
1
100K_0402_5%
E51_TXD
2
100K_0402_5%
EC_MUTE# <42>
USB_EN# <37>
USB_CHG_EN# <37>
HDPINT <44>
TP_CLK <45>
TP_DATA <45>
TP_CLK
1
R379
TP_DATA
1
R381
LID_SW #
2
47K_0402_5%
EC_SI_SPI_SO <44>
EC_SO_SPI_SI <44>
SPI_CLK <44>
SPI_CS# <44>
SYSON
CAP_INT# <45>
FSTCHG <49>
BATT_FULL_LED# <45>
CAPS_LED# <44>
BATT_CHG_LOW _LED# <45>
PW R_ON_LED# <45>
SYSON <39,53>
VR_ON <54>
EC_RSMRST# <30>
EC_LID_OUT# <29>
EC_ON <45>
TP_LED <45>
PM_PW ROK <30>
BKOFF# <25>
W L_OFF# <39>
CAP_RST# <45> Add
LOGO_LED <45>
2
4.7K_0402_5%
2
4.7K_0402_5%
+3VALW
VGATE <30,54>
W OL_EN# <40>
PW RME_CTRL# <28>
LID_SW # <44>
1
R5
1
R383
C
2
4.7K_0402_5%
R341 330K_0402_5%
1
2
+3VALW
D21
ACIN_D
2
1
ACIN <30,45,47>
+3VALW
SLP_CHG#
2
R1428
1
10K_0402_5%
CAP_RST# at PVT
B
CEC_INT# <27>
EC_ENBKL <25>
USB_OC#1 <32,37>
SLP_CHG# <37>
SUSP# <39,46,49,52,56>
PBTN_OUT# <30>
USB_OC#0 <32,37>
SUSP#
R423 2
1 10K_0402_5%
VR_ON
R462 2
1 10K_0402_5%
Add R462 at PVT
CIR
2
R748
10K_0402_5%
4
C450
Y4
2
LOGO_LED
LOGO_LED
R436
100K_0402_5%
U45
CIR_IN
R435
100K_0402_5%
@
H
L
+5VL
EC ver.
KB926D3
+5VL_CIR
1 CIR@ 2
R750
100_0805_5%
C783
4.7U_0805_10V4Z
CIR@
2
OSC
OSC
NC
NC
2
4.7K_0402_5%
KB926E0
1
Vout
2
VCC
3
GND
4
GND
IRM-V536/TR1_3P
CIR@
A
1
VTTP_EN
2
100K_0402_5%
1
R342
2
1
R337
18P_0402_50V8J
A
2
@
+5VL
1
1
1
18P_0402_50V8J
3
3
2
R53
+3VALW
10M_0402_5%
@
C449
32.768KHZ_12.5PF_Q13MC14610002
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
Title
Size
Date:
5
CEC_INT#
+EC_V18R
G
O
10K_0402_5%
2
VTTP_EN <51>
EN_DFAN1 <6>
IREF <49>
CHGVADJ <49>
C448
4.7U_0805_10V4Z
2CRY2
1
R757
1
D
+3VL
KB926QFE0_LQFP128_14X14
R389
CRY1
TMPTU2_SXP
0.1U_0402_16V4Z
P
<30> PM_SLP_S5#
1
10K_0402_5%
2
2
5
C818
2
1
TMPTU1_SXP
R754
1
BATT_TEMPA <48>
TMPTU1_SXP <39>
ADP_I <49>
ADP_V <49>
TMPTU2_SXP <39>
HDPACT <44>
SPI Device Interface
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
+3VALW
KB_LED <44>
EC_BEEP# <42>
SM_SENSE# <42>
ACOFF <49>
+5VS
GND
GND
GND
GND
GND
Close to EC
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DA Output
PM_SLP_S3#
SLP_S5#
EC_SMI#
THM_ALT#
ESB_CK
ESB_DAT
PCH_SUSPW RDN
INVT_PW M
FAN_SPEED1
HDPLOCK
E51_TXD
E51_RXD
ON/OFFBTN#
PW R_SUSP_LED#
NUM_LED#
<30> PM_SLP_S3#
KB_LED
EC_BEEP#
SM_SENSE#
ACOFF
PWM Output
+3VS
TV tuner
temperature
21
23
26
27
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
AD
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
2
100P_0402_50V8J
2
100P_0402_50V8J
1
+3VL
1
2
3
4
5
7
8
10
1
C443
22P_0402_50V8J
@
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
AVCC
1
R377
10_0402_5%
@
1
C445
1
C446
0.1U_0402_16V4Z
VCC
VCC
VCC
VCC
VCC
VCC
CLK_PCI_EC
D
ACIN_D
67
2
9
22
33
96
111
125
2
C442
1
2
2
AGND
C437
0.1U_0402_16V4Z
For EMI
BATT_TEMPA
0.1U_0402_16V4Z
1
2
69
0.1U_0402_16V4Z
1
1
1
C436
4
3
2
ENE-KB926 RevD2
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
43
of
59
SPI Flash (256KB)
Place the PAD under DDR DIMM.
LPC Debug Port
Lid SW
+3VS
H7
+3VL
5
7
4
PLT_RST# <32,39,40,41,43>
8
3
LPC_AD2 <28,43>
9
2
LPC_AD0 <28,43>
10
1
CLK_PCI_DDR
20mils
1
U22
3
W
7
HOLD
<43> SPI_CS#
SPI_CS#
1
S
SPI_CLK
6
<43> SPI_CLK
<43> EC_SO_SPI_SI
C
EC_SO_SPI_SI
5
D
VSS
+3VALW
2
1
EC_SI_SPI_SO
2
VDD
EC_SI_SPI_SO <43>
MX25L2005CMI-12G SO8
LID_SW # <43>
C453
0.1U_0402_16V4Z
<28,43> LPC_FRAME#
1
C452
10P_0402_50V8J
<32>
DEBUG_PAD
2
R393
22_0402_5%
@
1
2
<28,43> LPC_AD1
3
VOUT
2
0_0402_5%
<28,43> LPC_AD3
U21
APX9132ATI-TRL_SOT23-3
Q
1
R392
<28,43> SERIRQ
4
2
VCC
GND
8
2
1
C451
0.1U_0402_16V4Z
@
6
SPI_CLK
1 R394
2
10_0402_5%
2
1
C454
@
2
10P_0402_50V8J
C457
22P_0402_50V8J
1 @
@
For EMI
For EMI
1
2
3
4
GND
GND
Q38
KBL@
AO3413_SOT23-3
D
S
3
1
+5VS_LED
1
1
RG2 @
1
3
S
2
G
<43> KB_LED
KSO16
KSO17
KSO2
KSO1
KSO0
KSO4
KEYBOARD CONN.
KSO3
KSO5
KSI[0..7]
KSO[0..17]
KSI[0..7]
<43,45>
KSO14
KSO[0..17] <43,45>
KSO6
KSO7
JKB
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88170-3400
@
JKB34
KSO16
1
2
R372 300_0402_5%
+3VS
KSO13
KSO8
KSO17
KSO9
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R376 300_0402_5%
NUM_LED#
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
+3VS
CAPS_LED# <43>
NUM_LED# <43>
+5VS
DG1
1
please close to JKB1
Q52
2N7002_SOT23-3
KBL@
CAPS_LED#
NUM_LED#
1
C401
1
C402
1
C404
1
C405
1
C406
1
C407
1
C408
1
C409
1
C410
1
C411
1
C412
1
C413
1
C415
1
C416
1
C417
1
C418
1
C419
1
C420
1
C421
1
C422
1
C423
1
C424
1
C425
1
C427
1
C429
1
C431
1
C433
1
C435
SELF_TEST
1
+3VS_HDP
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
CG12
1U_0402_6.3V4Z
GSENSOR@
2
UG3
1
GSENSOR@
+3VS_HDP
+3VS_HDP
2
2
GSENSOR@
CG13
1U_0402_6.3V4Z
VOUT 5
1 GSENSOR@
1
VIN
2
GND
3
SHDN#
BP
4
G9191-330T1U_SOT23-5
CG14
2
1
Vdd1
Vdd2
4
6
8
ST
PD
FS
9
Rev
0_0603_5%
For EMI
D
2
+3VS
ACES_85201-0405N
@
C836
0.1U_0402_16V4Z
2 KBL@
2
12
+5VS_LED
2
2
G
R587
10K_0402_5%
KBL@
1
2
3
4
5
6
+3VS_HDP
GSENSOR@
Voutx
Vouty
Voutz
3
5
7
NC1
NC2
NC3
NC4
NC5
10
11
14
15
16
GND1
GND2
1
13
GSENSOR@
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2GSENSOR@
GSENSOR@
VOUTXCG1
VOUTYCG2
VOUTZCG3
Reserve for 2nd Source
+3VS_HDP
CG9 0.1U_0402_16V4Z UG4
@
2
1VOUTX2
CG10 0.1U_0402_16V4Z XOUT
@
2
1VOUTY3
CG11
0.1U_0402_16V4ZYOUT
@
2
1VOUTZ4 ZOUT
TSH35TR_LGA16
Place UG1 and UG4
on TOP Layer
9
+3VS_HDP
@
0.22U_0402_10V4Z
SELF_TEST
7
10
13
@
VDD
0G-DET
SLEEP#
G-SELECT
ST
6
NC
NC
NC
NC
NC
1
8
11
12
14
VSS
5
MMA7360LR2_LGA14
Change UG3 to SA000022I00 at PVT
UG5
1
<14,29,43,45> EC_SMB_CK2
P1_6/CLK0/SSI01
11
P1_5/RXD0/CNTR01/INT11#
12
P1_4/TXD0
13
P1_3/KI3#/AN11/TZOUT
14
P3_5/SSCK/SCL/CMP1_2
HDPACT <43>
2
+5VS
UG1
G-Sensor
JBLG
SELF_TEST
+3VS_HDP
HDPINT
1
4.7K_0402_5%
3
RESET#
RG4 2
GSENSOR@
1GXOUT
4.7K_0402_5%
4
XOUT/P4_7
1GXIN
4.7K_0402_5%
RG6
2
1 4.7K_0402_5%
GSENSOR@
RG7
2
1 1K_0402_5%
GSENSOR@
1
CG7
0.1U_0402_16V4Z
GSENSOR@ 2
5
VSS/AVSS
6
XIN/P4_6
P4_2/VREF
16
VOUTX
VOUTY
VCC/AVCC
17
8
MODE
18
9
P4_5/INT0#/RXD1
P3_3/TCIN/INT3#/SSI00/CMP1_0
19
P3_4/SCS#/SDA/CMP1_1
20
1
P1_7/CNTR00/INT10#
CG8
GSENSOR@
0.1U_0402_16V4Z
R5F211B4D34SP
2
200910/9
Deciphered Date
HDPLOCK <43>
VOUTZ
15
7
10
RG9
47K_0402_5%
GSENSOR@
P1_2/KI2#/AN10/CMP0_2
RG10 47K_0402_5%
2
1
GSENSOR@
+3VS_HDP
1
2
CG6
0.1U_0402_16V4Z
GSENSOR@
EC_SMB_DA2 <14,29,43,45>
GSENSOR@
Compal Secret Data
Issued Date
P3_7/CNTR0#/SSO/TXD1
RG3 2
GSENSOR@
RG5 2
GSENSOR@
<43> HDPINT
2
1
Keyboard LED
2010/01/23
Title
SPI ROM/LID/Debug/KB/G-Sen
Size
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
44
of
59
5
4
3
+3VL
Caps Sensor/Light Sensor Conn.
1
Touchpad & Light Pipe Connector
2
Power Button
2
JCS
2
SW3
C458
0.1U_0402_25V6
@
3
2
4
2
<43> EC_ON
@
1
<43> ESB_DAT
<43> ESB_CK
<43> CAP_INT#
<43> CAP_RST#
Q7A
2N7002DW-T/R7_SOT363-6
<14,29,43,44> EC_SMB_CK2
<14,29,43,44> EC_SMB_DA2
R396
10K_0402_5%
D
Remove J3 at PVT
For EMI request
SW1
1
2
3
4
5
6
7
8
9
10
GND
GND
SW_L
JTPL
+5VS
<43> TP_CLK
<43> TP_DATA
TP_LED#
KSI6
KSO0
2
390_0402_5%
ACES_85201-0405N
@
+5VALW
ESB_DAZ
@
1
100_0402_5%
100P_0402_50V8J
ESB_CKZ
@
1
1
D83
ON/OFFBTN#
2
R428
2
1
R427
2
<43,44> KSI6
<43,44> KSO0
C260 @
2
3
ON/OFFBTN#
1
R22
1
2
3
4
5
6
7
8
9
10
11
12
SW_L
SW_R
For EMI
PWR_ON_LED#
@
D
1
2
3
4
5
6
7
8
9
10
GND
GND
Q7B
SW4
SW_R
1
3
2
4
SMT1-05_4P
P-TWO_161021-10021
5
<43> TP_LED
C261 @
2
4
2N7002DW-T/R7_SOT363-6
4
JPOWER
1 1
2
2
3 3
4 4
G1 5
G2 6
3
SMT1-05_4P
Remove D19 at DVT
6
5
SMT1-05-A_4P
1
2
P-TWO_161021-10021
1
BTM side
1
2
3
4
5
6
7
8
9
10
11
12
6
5
1
ON/OFFBTN# <43>
ESB_DAZ
ESB_CKZ
CAP_INT#
CAP_RST#
1
Remove SW2
at pre-MP
2
TOP side
+5VALW
+3VL
FBMA-11-100505-301T_0402 +3VS
L13 1
2
L14 1
2
FBMA-11-100505-301T_0402
51_ON# <47>
ON/OFFBTN#
6
1
100K_0402_5%
@
6
5
R395
For debug
1
PWR_ON_LED# 3
100_0402_5%
100P_0402_50V8J
PJSOT05C_SOT23-3
Screw Hole
+5VS
C
R819
2
1
10K_0402_5%
WIMAX@
WIMAX_LED_GND#
3
6
1
1
1
H_3P0
@
H_2P7N
@
C
VGA
H3
H4
1
H_2P9x3P9
@
1
1
H_2P9x3P9
@
3
4
H16
H_4P7
@
H17
H_3P3
@
H_3P3
@
1
H_3P3
@
H23
H_4P2x4P7
@
1
LOGO_LED#
H22
H_4P2x4P7
@
1
5
1
H21
H_4P2
@
1
+5VS
H20
1
HT-SV116BP_WHITE
1
2
2
R774
120_0402_5%
1
2
1
Q9A
2N7002DW-T/R7_SOT363-6
H15
CPU
LOGO_LED <43>
4
2N7002DW-T/R7_SOT363-6
Q6B
1
2
2
R776
120_0402_5%
HT-SV116BP_WHITE
1
MDC
D20
MINI CARD -- WLAN
H24
H25
H18
H19
H_3P3
@
1
H_3P3
@
1
H_3P3
@
H_3P3
@
1
2N7002DW-T/R7_SOT363-6
@
1
2
R50
0_0402_5%
1
Q9B
H14
H_3P0
@
Logo LED
D22
5
3
H13
H_3P0
@
H26
H_2P7x3P2N
@
1
PCB Fedical Mark PAD
FD1
JLED
+5VALW
+5VS
<43> WL_BT_LED#
<43> PWR_ON_LED#
<43> PWR_SUSP_LED#
<41> CR_LEDCON#
<43> BATT_FULL_LED#
<43> BATT_CHG_LOW_LED#
WIMAX_LED_GND#
WL_BT_LED#
DC_IN
PWR_ON_LED#
PWR_SUSP_LED#
HDD_LED#
CR_LEDCON#
BATT_FULL_LED#
BATT_CHG_LOW_LED#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1
LED/B Connector
FD2
FD3
@
@
FD4
ISPD
@
UV1
N11PR3@
U11
N11P-GE1-A3
GND
GND
B
@
1
@
1
B
1
HDD_LED#
H12
H_3P0
@
MINI CARD -- 3G
SATA_LED# <28>
6
1
1
1
1
H1
4
H_2P9
@
2 R404
1
10K_0402_5%
H11
H_3P0
@
1
Q156A
2N7002DW-T/R7_SOT363-6
WIMAX@
H2
+5VS
H10
H_3P0
@
@
Q156B 2N7002DW-T/R7_SOT363-6
WIMAX@
HDD LED
H9
H_3P0
@
1
H8
H_3P0
@
1
Q35A
1
6
2N7002DW-T/R7_SOT363-6
H6
H_3P0
@
LED_WIMAX# <39>
1
DC_IN
5
2
R506
WIMAX_LED_GND# 1
2
0_0402_5%
2
WiMAX LED
ACIN <30,43,47>
1
H5
DC-IN LED
13
14
UV1
HM55R3@
PCH
N11ER1@
UV1
N11MGER1@
UV1
N11MOPR1@
ZZZ
PCB LA-6062P
U11
PM55@
PJP1
45@
ACES_85201-1205N
A
N11E-GE1-A3
N11M-GE1-B-A3
N11M-OP1-B-A3
PCH
UV1
UV1
UV1
U11
N11ER3@
N11E-GE1-A3
N11M-GE1-B-A3
200910/9
3
A
PCH
Title
Date:
4
PJP1
HM57@
2010/01/23
Deciphered Date
Size
5
N11MOPR3@
N11M-OP1-B-A3
Compal Secret Data
Issued Date
N11MGER3@
2
PWR/Cap./TP/LED/LP/LS/Screw
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
1
45
of
59
A
B
C
+3VALW TO +3VS
+3VALW
+3VS
D
E
+5VALW TO +5VS
+5VALW
Vgs=10V,Id=9A,Rds=18.5mohm
+1.5V to +1.5VS
Vgs=10V,Id=9A,Rds=18.5mohm
+1.5V
+5VS
+1.5VS
4.7U_0805_10V4Z
C469
470_0805_5%
3 1
Q12A
Q12B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
R421
470_0805_5%
NOPS@
5
1
1
6
Q44B
2N7002DW-T/R7_SOT363-6
PS@
D
Q6A
2N7002DW-T/R7_SOT363-6
2
<39,43,49,52,56> SUSP#
S
3
Q44A
2N7002DW-T/R7_SOT363-6
PS@
SUSP
2
Q13B
2N7002DW-T/R7_SOT363-6
2
Q189
2 SUSP
G
2N7002_SOT23-3
1
5
0.75VR_EN
2
100K_0402_5%
1
3
1
R158
<5,51> VTTPWROK
R421
47_0805_5%
PS@
1
6
1
2 VGA_PWROK#
2N7002DW-T/R7_SOT363-6
SUSP
<9,53> SUSP
PS@
Q13A
1
2
1
1
R429
1 R431
2
+VSB
220K_0402_5%
R430
820K_0402_5%
2
2
0.1U_0402_25V6
1
C481
4.7U_0805_10V4Z
1
C473
C475
4.7U_0805_10V4Z
1U_0402_6.3V4Z
FDS6676AS_SO8
2
+0.75VS
2
2
+5VALW
R422
100K_0402_5%
4
2
6
2
2
1
2
3
4
470_0805_5%
S
S
S
G
R414
820K_0402_5%
0.75VR_EN# <53>
3 1
D
D
D
D
1
2
6
1
1
1
2
R408
1 R411
2
+VSB
220K_0402_5%
4
8
7
6
5
2
1
2
1
@
R425
100K_0402_5%
PS@
Vgs=10V,Id=14.5A,Rds=6mohm
C478
2
1U_0402_6.3V4Z
FDS6676AS_SO8
1
1
+VRAM_1.5VS
Q43
C464
+3VALW
+1.5V to +VRAM_1.5VS
+1.5V
1
2
3
4
4
C821
S
S
S
G
2
Q11B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
@
2
D
D
D
D
1
0.1U_0402_25V6
3 1
Q11A
1
C822
C463
C470
2
R413
200K_0402_5%
@
+VSB
2
8
7
6
5
4.7U_0805_10V4Z
C468
2
R407
For EMI
0.1U_0402_16V4Z
C467
2
1
6
1
470_0805_5%
2
1 R410
2
47K_0402_5%
Vgs=10V,Id=14.5A,Rds=6mohm
Q31
0.1U_0402_16V4Z
Q10B
1
2
SI4800BDY_SO8
Q10A
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1U_0402_6.3V4Z
1
R412
330K_0402_5%
2
+VSB
1
2
3
4
1
6
C466
2
C465
2
1
1
0.022U_0402_25V7K
1
1 R409
2
47K_0402_5%
S
S
S
G
1
2
R406
D
D
D
D
0.01U_0402_25V7K
2
4.7U_0805_10V4Z
2
8
7
6
5
C461
+5VS
4
Q30
1U_0402_6.3V4Z
SI4800BDY_SO8
4.7U_0805_10V4Z
1
4.7U_0805_10V4Z
2
1
2
3
4
S
S
S
G
C460
3 1
1
D
D
D
D
1
4
8
7
6
5
C459
470_0805_5%
Q29
4.7U_0805_10V4Z
1
C462
+5VALW
R146
1
3
1
D
S
Q188
2N7002_SOT23-3
2
G
<28,32,56> VGA_PWROK
2
100K_0402_5%
+3VS to +3VS_DGPU
+5VS TO +5VS_ODD
+3VS
+3VALW
2
2
+5VS_ODD
2
2
2
Q206B
2N7002DW-T/R7_SOT363-6
OPT@
C686
1U_0402_6.3V4Z
OPT@
2
Q55
2
G
2N7002_SOT23-3
OPT@
Issued Date
D
S
2
2
1
1
2
C680
1U_0402_6.3V4Z
2
4
Compal Secret Data
200910/9
2010/01/23
Deciphered Date
Title
Size
Date:
B
1
DGPU_PWR_EN#
A
AO3413_SOT23
C217
0.01U_0402_25V7K
PJ28
JUMP_43X79
@
+5VS_ODD
1
1
5
3
1
5
2N7002DW-T/R7_SOT363-6
OPT@
2
C679
4.7U_0805_10V4Z
@
1
C685
4.7U_0603_6.3V6K
@
1
4
4
1
Q45
2
2
1
3
1
+1.05VS_DGPU
2
Q207B
DGPU_PWR_EN#
2
2N7002DW-T/R7_SOT363-6
OPT@
R397
1
R459
470_0805_5%
OPT@
3 1
1
Q207A
C471
0.1U_0402_16V7K
1
+VGA_CORE
R458
470_0805_5%
OPT@
3
C493
0.01U_0402_25V7K
OPT@
2
R398
10K_0402_5%
47K_0402_5%
+3VS_DGPU
4
3
2
1
C684
1U_0402_6.3V4Z
2 OPT@
2
+5VS
+5VS
<32> ODD_EN#
R460
470_0805_5%
OPT@
1
2
G
S
AO3416_SOT23-3
OPT@
1
1
2
1
2
2
1
D
Q56
ODD_EN#
2
G
2N7002_SOT23-3
+1.05VS_DGPU
R434
47K_0402_5%
OPT@
6
2
R144
0_1206_5%
DIS@
1
1
Vgs=4.5V,Id=3A,Rds<22mohm
Q53
S
1
+5VALW
+1.05VS
+3VS_DGPU
3
D
1
1
<13,33,56> DGPU_PWR_EN
R104
0_0805_5%
DIS@
3
Change +1.05VS_DGPU circuit
to N-channel MOS at PVT
3
1
6
47K_0402_5% 2
AO3413_SOT23
OPT@
OPT@
Q206A
C492
OPT@
OPT@ 0.01U_0402_25V7K
1
2
2N7002DW-T/R7_SOT363-6
C683
4.7U_0805_10V4Z
@
1
2
G
Q54
2
Change PJ32 to
0 ohm at DVT
D
R426
1
R457
470_0805_5%
S
C491
0.1U_0402_16V7K
OPT@
G
DGPU_PWR_EN#
1
D
+1.05VS to +1.05VS_DGPU
3
2
S
R433
100K_0402_5%
OPT@
C
D
DC-DC INTERFACE
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
E
46
of
59
A
B
C
D
VS
VIN
1
PR3
5.6K_0402_5%
-
O
LM393DG_SO8
PACIN <49>
PD1
GLZ4.3B_LL34-2
PR7
10K_0402_1%
2
1
PR8
10K_0402_1%
+CHGRTC
Vin Detector
3.3V
2
VIN
2
2
2
2
PC8
.1U_0402_16V7K
PACIN
1
1
+
2
1
ACIN <30,43,45>
PU1A
1
3
1
1
2
PC7
0.068U_0402_10V6K
PR6
20K_0402_1%
PR4
10K_0402_1%
1
2
2
8
2
PR5
22K_0402_1%
1
2
1
1
@
N1
PR2
84.5K_0402_1%
PC6
100P_0402_50V8J
2
1
2
PC5
680P_0402_50V7K
1
2
1
PC4
1000P_0402_50V7K
2
@ SINGA_2DW -0005-B03
@
PC3
100P_0402_50V8J
4
2
-
1
-
3
2
2
PC2
680P_0402_50V7K
+
1
1
PC1
1000P_0402_50V7K
+
1
P
DC_IN_S2
2
10A_125V_451010MRL
G
1
1
DC_IN_S1
PJP1
4
PF1
DC301001M80
PR1
1M_0402_1%
1
2
VIN
PL1
SMB3025500YA_2P
1
2
High 18.384 17.901 17.430
Low 17.728 17.257 16.976
1
1
PD3
RLS4148_LL34-2
CHGRTCP
2
PR11
200_0603_5%
1
2
PR10
68_1206_5%
N1
3
1
1
VS
1
1
PC10
0.1U_0603_25V7K
PD4
2
PR15
22K_0402_1%
N3
1
1
2
B+
PR14
1K_1206_5%
RLS4148_LL34-2
2
2
2
VIN
2
PC9
0.22U_0603_25V7K
2
PR13
100K_0402_1%
2
2
PR12
1K_1206_5%
1
2
PR9
PQ1
68_1206_5%
TP0610K-T1-E3_SOT23-3
2
2
BATT+
1
1
PD2
RLS4148_LL34-2
1
1
RTC Battery
2
PR16
1K_1206_5%
1
1
<45> 51_ON#
+RTCBATT
PR20
2.2M_0402_5%
2
1
(5A,200mils ,Via NO.= 10)
+1.5VP
PJ5
2
2
1
1
+5VALW
2
2
2
+1.5V
+GFX_COREP
1
1
2
+VSB
2
VL
2
1
1
+GFX_CORE
+3VLP
2
2
2
1
+VGA_COREP
1
1
1
+1.05VS
1
2
2
1
1
1
1
8
1
1
2
2
+VGA_CORE
4
@ JUMP_43X79
Issued Date
Compal Secret Data
+0.75VS
(1.5A,60mils ,Via NO.= 4)
@ JUMP_43X79
2
OCP(min)=29.17A
PJ17
+0.75VSP
PJ16
2
(24A,960mils ,Via NO.=48)
OCP(min)=29.73A
2
1
@ JUMP_43X118
+VTT
@ JUMP_43X118
2
Precharge detector
15.97V/14.84V FOR
ADAPTOR
PQ3
DTC115EUA_SC70-3
PJ15
OCP(min)=26A
+1.05VSP
1
+5VALW P
+3VL
@ JUMP_43X118
PJ13
2
2
PACIN
1
@ JUMP_43X118
+VTTP
1
PJ12
@ JUMP_43X118
2
1
(100mA,40mils ,Via NO.= 2)
1
1
PJ11
4
2
2
@ JUMP_43X39
PJ10
2
3
S
+5VL
@ JUMP_43X39
@ JUMP_43X39
2
2
G
PJ9
2
2
1
1
PR27
47K_0402_1%
2
1
D
PQ2
SSM3K7002FU_SC70-3
@ JUMP_43X118
+1.8VS
PJ6
PJ8
PJ7
1
1
1
1
OCP(min)=21.73A
OCP(min)=7.9A
2
PC14
1000P_0402_50V7K
@ JUMP_43X79
(20A,800mils ,Via NO.= 40)
@ JUMP_43X118
2
2
+1.8VSP
@ JUMP_43X118
+VSBP
1
1
PJ4
OCP(min)=7.7A
+5VALW P
2
@ JUMP_43X118
PR24
499K_0402_1%
PR26
191K_0402_1%
1
2
+3VALW
@ PR25
66.5K_0402_1%
3
1
+CHGRTC
1
1
PC13
1000P_0402_50V7K
1
PR23
10K_0402_1%
3
2
@ JUMP_43X118
2
2
1
2
PC15
1000P_0402_50V7K
6
2
+3VALW P
PJ3
5
-
1
LM393DG_SO8
PJ2
+
O
2
3
7
1
<49> ACON
PU1B
1
1
SP093MX0000
2
3
PJ1
PR18
499K_0402_1%
2
1U_0805_25V6K
<50> EN0
P
PD5
RB715F_SOT323-3
@ MAXEL_ML1220T10
PC12
1
PR19
100K_0402_1%
1
2
VL
G
PC11
10U_0805_10V4Z
PR22
560_0603_5%
1
2
2
N2
2
IN
GND
PR21
560_0603_5%
1
2
2
2
1
OUT
1
4
3
+CHGRTC
+
PBJ1
2
1
3.3V
G920AT24U_SOT89-3
2
-
PR17
200_0603_5%
PU2
2009/01/23
Deciphered Date
2010/01/23
Title
Size
(7.0A,280mils ,Via NO.=14)
OCP(min)=8.4A
Date:
A
B
C
DCIN / DETECTOR
Document Number
Rev
2.0
NWQAA LA-6062P M/B
D
Sheet
47
of
59
A
B
1
C
1
VMB
PF2
15A_65V_451015MRL
1
2
1
2
PR29
47K_0402_1%
PH1 under CPU botten side :
CPU thermal protection at 95 degree C
Recovery at 56 degree C
BATT+
+3VLP
1
2
PR28
1K_0402_1%
@ PC18
0.1U_0402_25V6K
PR30
1K_0402_1%
PC16
1000P_0402_50V7K
2
1
1
BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
1
BATT_S1
2
GND
GND
GND
GND
1
2
3
4
5
6
7
8
9
1
10
11
12
13
1
2
3
4
5
6
7
8
9
PL2
SMB3025500YA_2P
1
2
PH2 near main Battery CONN :
BAT. thermal protection at 95 degree C
Recovery at 48 degree C
PC17
0.01U_0402_25V7K
2
PJP2
D
2
@ SUYIN_200045MR009G171ZR
VL
1
1
PR31
19.6K_0402_1%
1
2
PR33
19.6K_0402_1%
2
+3VLP
2
PC19
0.1U_0603_25V7K
PR32
6.49K_0402_1%
2
1
3
2
PD6
2
PJSOT24C_SOT23-3
3
2
1
PD7
PJSOT24C_SOT23-3
PR34
8.66K_0402_1%
1
1
PU4
VCC TMSNS1
8
2
GND RHYST1
7
3
OT1 TMSNS2
6
4
OT2 RHYST2
5
2
2
PR37
100_0402_1%
PH1
100K_0402_1%_NCP15W F104F03RC
1
BATT_TEMPA <43>
1
1
PR36
100_0402_1%
<50> VS_ON
2
2
2
1
1
1
PR35
1K_0402_1%
2
PR40
7.87K_0402_1%
G718TM1U_SOT23-8
2
EC_SMB_DA1 <27,43>
1
EC_SMB_CK1 <27,43>
2
PH2
100K_0402_1%_NCP15W F104F03RC
PQ4
TP0610K-T1-E3_SOT23-3
3
B+
+VSBP
1
2
PR42
22K_0402_1%
1
2
1
2
2
1
2
@
PC21
0.1U_0603_25V7K
VL
PC20
0.22U_0603_25V7K
3
2
1
PR41
100K_0402_1%
3
@
1
PR44
0_0402_5%
2
D
3
1
S
PQ5
SSM3K7002FU_SC70-3
2
G
2
1
<50> POK
@ PC22
.1U_0402_16V7K
1
PR43
100K_0402_1%
4
4
Issued Date
Compal Secret Data
2009/01/23
Deciphered Date
2010/01/23
Title
Size
Date:
A
B
C
BATTERY CONN / OTP
Document Number
Rev
2.0
NWQAA LA-6062P M/B
D
Sheet
48
of
59
DCIN
ACSET ACPRN
23
3
EN
CSON
22
4
CELLS
CSOP
21
5
ICOMP
CSIN
20
VCOMP
CSIP
19
ICM
PHASE
18
LX_CHG
VREF
UGATE
17
DH_CHG
4.7U_0805_25V6-K
PC26
4
4.7U_0805_25V6-K
2
1
PC25
11
VADJ
LGATE
14
GND
PGND
13
2
1
12
26251VDD
1
2
DL_CHG
2
AM@ PR70
20K_0402_1%
PR71
4.7_0603_5%
PC45
4.7U_0805_6.3V6K
1
1
3
2
1
4
PD12
RB751V-40TE17_SOD323-2
6251VDDP
2
PR63
0.02_1206_1%
4
2
3
BATT+
PC107
10U_1206_25V6M
2
1
15
1
PC42
10U_1206_25V6M
2
1
VDDP
2 PACIN
G
PQ16
SSM3K7002FU_SC70-3
PC41
10U_1206_25V6M
2
1
ACLIM
2
PC40
0.1U_0603_25V7K
BST_CHGA 2
1
S
2
PL3
10U_LF919AS-100M-P3_4.5A_20%
CHG
1
2
3
2
1
PR61
2.2_0603_1%
PR67
0_0603_5%
BST_CHG 1
D
PR65
4.7_1206_5%
10
2
PQ17
AO4466_SO8
1
2
1
4
1
16
1
PC33
0.1U_0603_25V7K
2
BOOT
2
5
6
7
8
2
CSON
PQ19
AO4466_SO8
CHLIM
VIN
PD11
3
PR57
20_0603_5%
1
2
PC32
0.047U_0603_16V7K
1
2
PR58
20_0603_5%
2
1
PR59
PC37
20_0603_5%
0.1U_0603_25V7K
1
2
5
6
7
8
6251aclim
9
ACOFF
2
PR54
200K_0402_1%
1
2
PQ15
DTC115EUA_SC70-3
3
2
1
AM@ PR68
24K_0402_1%
6251VREF 1
2
8
1
1SS355_SOD323-2
1SS355_SOD323-2
1
6251VREF
VIN
1
VDD
2
1
4
4.7U_0805_25V6-K
2
1
PC24
2
3
PC31
0.1U_0603_25V7K
2
1
PQ9 AO4407A_SO8
CP@
PQ9 AO4407A_SO8
CE@
PD9
PC43
680P_0603_50V8J
3
2
PR69
120K_0402_1%
DCIN
24
1
ADP_I
PU5
1
6
@ PC38 100P_0402_50V8J
1
2
PC39
.1U_0402_16V7K
SUSP# <39,43,46,52,56>
RB715F_SOT323-3
PR62 47K_0402_1%
2
7
2
2
PQ20
DTC115EUA_SC70-3
1
1
6.81K_0402_1%
2
PR52
10K_0402_1%
2 1
1
1
PC44
0.01U_0402_25V7K
2
1
PR66
154K_0402_1%<43>
2
1
<43> IREF
2
1
6800P_0402_25V7K
2
1
1
1
ACOFF
PR60
0.01U_0402_25V7K
6251_EN
@ PC34
680P_0402_50V7K
1
2
PC35
1
PC36
1
2
<47> ACON
<43> ACOFF
2
2
2
1
3
<47> PACIN
S
PR64
22K_0402_5%
1
2
CSON
FSTCHG
2
3
PC29
2.2U_0603_6.3V6K
2
1
PC30
.1U_0402_16V7K
PQ18
SSM3K7002FU_SC70-3
D
2
G
PACIN
2
1
1
1
2
PR49
47K_0402_1%
1
2
PD8
6251VDD
PR53
10K_0402_1%
2
1
PR55
150K_0402_1%
PQ14
SSM3K7002FU_SC70-3
PQ12
DTC115EUA_SC70-3
CM@ PQ9 AO4407A_SO8
1
8
2
7
3
6
5
@
<43> FSTCHG
3
1
3
S
CSIN
DCIN
PR51
100K_0402_1%
2
1
PQ6 AO4435_SO8
AM@
8
7
6
5
1
1
1
PR50
100K_0402_1%
PD10
1SS355_SOD323-2
1
2
PQ13
DTC115EUA_SC70-3
2
G
PQ11 TP0610K-T1-E3_SOT23-3
PR47 10_0603_5%
3
1
1
2
P3
2
D
2
@ JUMP_43X118
CSIP
PR46
200K_0402_1%
PQ6
AO4407A_SO8
1
2
3
PJ18
2
3
PR56
100K_0402_1%
1
1
2
2
PR48
47K_0402_1%
PR45 0.015_2512_1%
4
2
PC28
5600P_0402_25V7K
1
2
2
1
2
1
1
1
PQ10
DTA144EUA_SC70-3
PC27
0.1U_0603_25V7K
3
1
8
7
6
5
B+
CHG_B+
0.1U_0402_25V6K
2
1
1
2
3
B+
Arrandale -- non mount,PQ9
Clarksfield --mount PQ9
4
1
2
3
4
8
7
6
5
2
VIN
P3
PQ8
AO4407A_SO8
D
PC23
P2
PQ7
AO4407A_SO8
PR45 0.02_2512_1%
AM@
PC106
10U_1206_25V6M
2
1
PQ7 AO4435_SO8
AM@
C
PC105
10U_1206_25V6M
2
1
B
PC104
10U_1206_25V6M
2
1
A
ISL6251AHAZ-T_QSOP24
1
<43> CHGVADJ
PR72
15.4K_0402_1%
1
2
PR73
31.6K_0402_1%
CP mode
Iada=0~3.947A(75W)
CP= 92%*Iada; CP=3.63A
Vaclim=0.736V(75W)
PR68=24k PR70=20k
Iada=0~4.737A(90W)
3
VIN
2
3
PR68=8.25k PR70=26.7k
PR49=0.015
PR70 26.7K_0402_1%
CP@
PR70 26.7K_0402_1%
CE@
PR70 20K_0402_1%
AP@
PR70 20K_0402_1%
APOP@
PR70 20K_0402_1%
CM@
PR74
309K_0402_1%
PR75
10K_0402_1%
1
2
ADP_V <43>
PR76
47K_0402_1%
1
Vaclim=0.736V(120W)
PR68 8.25K_0402_1%
CP@
PR68 8.25K_0402_1%
CE@
PR68 53.6K_0402_1%
AP@
PR68 53.6K_0402_1%
APOP@
PR68 53.6K_0402_1%
CM@
PR49=0.015
PC46
.1U_0402_16V7K
2
2
2
PR68=53.6k PR70=20k
Iada=0~6.316A(120W)
1
Vaclim=0.736V(90W)
1
PR49=0.02
CC=0.25A~3A
CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge
Vcell
IREF=0.254V~3.048V
4V
CHGVADJ
VCHLIM need over 95mV
4.2V
1.882V
4.35V
3.2935V
0V
4
4
Issued Date
Compal Secret Data
2009/01/23
Deciphered Date
2010/01/23
Title
Size
Date:
A
B
C
CHARGER
Document Number
Rev
2.0
NWQAA LA-6062P M/B
D
Sheet
49
of
59
5
4
3
2
1
PC47
1U_0603_10V6K
2VREF_51125
1
PC54
220U_6.3V_M
1
2
1
2
B
Ipeak=5A
Imax=3.5A
F=245kHZ
Total capacitor
220u
ESR=15m ohm
3
PC60
0.01U_0402_16V7K
2
2
1
PR92
42.2K_0402_1%
A
@
Compal Secret Data
2009/01/23
Issued Date
Deciphered Date
2010/01/23
5
PC56
680P_0603_50V8J
NC
3
2
1
2
PC58
4.7U_0805_10V6K
VL
2
1
2
PR91
100K_0402_1%
A
+
2
PQ27
DTC115EUA_SC70-3
<48> VS_ON
1
1
1
PR90
100K_0402_1%
VS
S
+5VALWP
1
2
3
3
S
4
18
EN
13
2
@ PR89
0_0402_5%
2VREF_51125
PQ26
SSM3K7002FU_SC70-3
PQ24
AO4712_SO8
RT8205EGQW _W QFN24_4X4
1
1
B++
D
2
G
PL5
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2
PR86
4.7_1206_5%
LG_5V
4
5
6
7
8
19
5
6
7
8
2
LGATE1
C
PQ22
AO4466_SO8
3
2
1
1
2
G
1
2
3
LGATE2
2
PC59
0.1U_0603_25V7K
1
1
D
PQ25
SSM3K7002FU_SC70-3
ENTRIP1
FB1
REF
LX_5V
VREG5
20
VIN
PHASE1
2
PR88
100K_0402_5%
4
21
PHASE2
1
ENTRIP2
2
1
ENTRIP1
FB2
22
UGATE1
PR87
499K_0402_1%
1
2
PC57
1U_0402_6.3V6K
B
TONSEL
BOOT1
UGATE2
4
B+
5
BOOT2
PC52
PR84
.1U_0402_16V7K
BST_5V 1
2 1
2
2.2_0603_1%
UG_5V
1
1
2
3
8
7
6
5
POK <48>
23
17
12
24
<47> EN0
1
2
3
2
PR85
4.7_1206_5%
2
1
+
LG_3V
VO1
16
PR83
2 1
2 BST_3V 9
2.2_0603_1%
PC51
UG_3V 10
.1U_0402_16V7K
LX_3V
11
PQ23
AO4712_SO8
PC55
680P_0603_50V8J
2
1
1
PC53
220U_6.3V_M
Ipeak=5A
Imax=3.5A
F=305kHZ
Total capacitor
220u
ESR=15m ohm
VL
PR82
150K_0402_1%
2
PGOOD
GND
VREG3
SKIPSEL
VO2
8
1
+3VALWP
P PAD
7
4
PL4
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2
6
1
25
15
PQ21
AO4466_SO8
PU6
2
PC50
4.7U_0805_10V6K
8
7
6
5
1
2
PC48
10U_1206_25V6M
1
B++
PC49
10U_1206_25V6M
PR81
150K_0402_1%
1
2
JUMP_43X118
C
PR80
19.1K_0402_1%
1
2
ENTRIP1
+3VLP
1
PR79
20K_0402_1%
1
2
ENTRIP2
1
PR78
30K_0402_1%
1
2
14
B+
@ PJ19
2 2
PR77
13K_0402_1%
1
2
ENTRIP2
B++
D
2
D
4
3
2
Title
3VALWP/5VALWP
Size
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Date:
Sheet
1
50
of
59
A
B
C
D
PL6
HCB4532KF-800T90_1812
1
1+VTTP_B+
+5VS
1
VTTPW ROK <5,46>
PR93
3.4K_0402_1%
4
VCC
BST_+VTTP
2
BOOT
PR97
4.7_0603_5%
1
2
+VTTP_VCC
5
DH_+VTTP
1
PR96
0_0402_5%
15
1
2
+5VALW
1
PC64
0.1U_0603_25V7K
PQ28
TPCA8030-H_SOP-ADV8-5
4
14
LG
13
PGND
12
ISEN
11
1
2
PC65
2.2U_0603_6.3V6K
DL_+VTTP
PL7
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
1
PVCC
3
2
1
VIN
PHASE
3
+VTTP_VCC
PGOOD
GND
8
PR141 2.43K_0402_1% PR95 4.53K_0402_1%
PU7
DH_+VTTP
2
16
1
UG
PR181 0_0402_5%
1
2
PC66
2.2U_0603_6.3V6K
6.98K_0402_1%
2
6.98K_0402_1%
2
PC67
390U_2.5V_M
1
PR99
4.7_1206_5%
+
2
1
2
PQ29
4.99K_0402_1%
1
PC69
680P_0603_50V8J
2
1
@ PC70
0.01U_0402_16V7K
4.99K_0402_1%
3
2
1
10
PR98
CP@
PR98
CE@
PR98
AP@
PR98
AM@
PR98
APOP@
4
TPCA8028-H_SOP-ADVANCE8-5
5
2
1
2
PR98
4.99K_0402_1%
CM@
VO
FSET
FB
2
2
.1U_0402_16V7K
@ PC73
3
PMBT2222A_SOT23-3
@ PQ31
2
100K_0402_5%
@ PR113
1
2
@ PR112
10K_0402_5%
2
1
2
0.01U_0402_16V7K
@ PC74
1
S
2
G
1
1
<8> H_VTTSELECT
D
3
@ PR111
4.7K_0402_5%
1
2
2
PR103
3.32K_0402_1%
PR106
4.42K_0402_1%
AM@
1
2+VTTP
PR104
0_0402_5%
1
2
PR108
10_0402_5%
1
@ PQ30
2N7002W-T/R7_SOT323-3
1
2
@ PR105
40.2K_0402_1%
1
1
100K_0402_5%
@ PR109
2
180K_0402_1%
@ PR107
+3VS
+VTTP
Material Note:
330uF/ 6mohm, number are 3,
power x1, HW x2
6.98K_0402_1%
3
1
1
3
+3VS
7
2
1
@ PC72
2200P_0603_50V7K
1
@ PR101
33.2K_0402_1%
2
1
@ PC71
33P_0402_50V8J
2
Clarksfield 1.1V
Arrandale 1.05V
SE_+VTTP 1
+VTTP
FB_+VTTP
6
2
1
PC68
.1U_0402_16V7K
NC
PR100
0_0402_5%
@
H_VTTVID1= Low, 1.1V
H_VTTVID1= High, 1.05V
EN
9
5
1
2
PR102
57.6K_0402_1%
2
1
<43> VTTP_EN
Ipeak=20A
Imax=14A
F=231.5kHZ
Total capacitor 1110u
ESR=3.86m ohm
APW 7138NITRL_SSOP16
2
2
PR94 2.2_0603_1%
1
2
2
2
1
2
VTTPW ROK_CPU <5>
LX_+VTTP
2
1
PC61
4.7U_0805_25V6-K
2
2
1
PC63
4.7U_0805_25V6-K
B+
2
1
PC62
4.7U_0805_25V6-K
1
PR106
AP@
PR106
APOP@
PR106
CM@
PR106
CP@
PR106
CE@
4.42K_0402_1%
2
PR110
10_0402_5%
VTT_SENSE <8>
PJ20
+VTTP
2
2
1
1
+1.05VS
@ JUMP_43X79
VSS_SENSE_VTT <8>
(7.0A,280mils ,Via NO.=14)
Arrandale -- mount,
Clarksfield --non mount @
4.42K_0402_1%
3.92K_0402_1%
3.92K_0402_1%
3.92K_0402_1%
4
4
Compal Secret Data
Issued Date
2009/01/23
Deciphered Date
2010/01/23
A
B
C
Title
+VTTP
Size
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Date:
D
Sheet
51
of
59
A
B
C
D
PJ21
VDDP
10
LGATE
9
LX_1.05V
CP@ PR119 15.8K_0402_1%
+5VALW
1
2
CM@ PR119
15.8K_0402_1%
1
4
1
2
CM@ PC76
4.7U_0805_25V6-K
CP@ PC76
4.7U_0805_25V6-K
CE@ PC76
4.7U_0805_25V6-K
+
2
Ipeak=7A
Imax=4.9A
F=313kHZ
Total capacitor 550u
ESR=5m ohm
2
3
2
1
SY8033BDBC_DFN10_3X3
1
2
1
PC89
22U_0805_6.3V6M
1
7
11
PC86
68P_0402_50V8J
1
2
2
PC83
.1U_0402_16V7K
PR124
51.1K_0402_1%
2
PC90
680P_0603_50V8J
PC88
22U_0805_6.3V6M
6
1
PR126
4.7_1206_5%
FB_SY8033B
1
@ PR125
499K_0402_1%
3
+1.8VSP
1
FB
EN
TP
5
LX
PL9
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2
2
SVIN
3
LX_SY8033B
1
PVIN
8
2
2
EN_SY8033B
2
PR122
68K_0402_1%
1
1
9
LX
NC
PC85
22U_0805_6.3V6M
2
@ JUMP_43X39
<39,43,46,49,56> SUSP#
1
CP@ PC82
4.7U_0805_10V6K
CE@ PC82
4.7U_0805_10V6K
1 2
PVIN
NC
10
1
2
PG
PU9
2
+1.05VSP
2
PJ25
1
CM@ PC82
4.7U_0805_10V6K
CP@ PU8
RT8209BGQW _W QFN14_3P5X3P5
CE@ PU8
3
1
4
2
PR120 8.25K_0402_1%
CP@
PR120 8.25K_0402_1%
CE@
CM@ PR121
20.5K_0402_1%
PR121 20.5K_0402_1%
CP@
PR121 20.5K_0402_1%
CE@
CM@ PQ33
AO4712_SO8
1
PGND
CM@ PR120
8.25K_0402_1%
1
2
+5VALW
DL_1.05V
CE@ PR119 15.8K_0402_1%
2
7
PC80 4.7U_0603_6.3V6K
CP@
PC80 4.7U_0603_6.3V6K
CE@
2
8
PGOOD
2
CM@ PC80
4.7U_0603_6.3V6K
GND
6
Arrandale -- non mount, @
Clarksfield --mount
1
CE@ PC79
220U_6.3V_M
15
1
14
11
B+
@ JUMP_43X118
CP@ PC79
220U_6.3V_M
FB
12
CS
1
1
5
PHASE
2
@ PR117
4.7_1206_5%
VDD
1
DH_1.05V
2
VOUT
4
13
@ PC81
680P_0603_50V8J
3
UGATE
1
1
CP@ PL8 1.8UH_SIL104R-1R8PF_9.5A_30%
CM@ PL8 1.8UH_SIL104R-1R8PF_9.5A_30%
CP@ PQ33
AO4712_SO8
CE@ PQ33
AO4712_SO8
1
2
TON
2
CE@ PL8 1.8UH_SIL104R-1R8PF_9.5A_30%
3
2
1
2
CE@ PC78
0.1U_0603_25V7K
CP@ PC78
0.1U_0603_25V7K
CM@ PC78
0.1U_0603_25V7K
CM@ PR116
0_0603_5%
CP@ PR116
0_0603_5%
BOOT
PC77 .1U_0402_16V7K
CP@
PC77 .1U_0402_16V7K
CE@
NC
2
CM@ PC77
.1U_0402_16V7K
EN/DEM
CM@
PU8
1
PR118 100_0603_1%
CP@
PR118 100_0603_1%
CE@
CM@ PR118
100_0603_1%
1
2
+5VALW
CE@ PR116
0_0603_5%
2
BST_1.05V 1
5
6
7
8
0_0402_5%
2
CM@ PC79
220U_6.3V_M
CM@ PR114
255K_0402_1%
1
2
0_0402_5%
2
PR115
CE@
PR115
CP@
1
SUSP#
CM@ PR115
0_0402_5%
1
2
CM@ PQ32
AO4466_SO8
CP@ PQ32
AO4466_SO8
CE@ PQ32
AO4466_SO8
4
CM@ PC75
4.7U_0805_25V6-K
PR114 255K_0402_1%
CE@
PR114 255K_0402_1%
CP@
5
6
7
8
1
CE@ PC75
4.7U_0805_25V6-K
CP@ PC75
4.7U_0805_25V6-K
2
1
1.05V_B+
2
PR123
25.5K_0402_1%
4
4
Issued Date
Compal Secret Data
2009/01/23
Deciphered Date
2010/01/23
Title
Size
Date:
A
B
C
1.05VSP / +1.8VSP
Document Number
Rev
2.0
NWQAA LA-6062P M/B
D
Sheet
52
of
59
5
4
3
2
1
PJ22
PR132
7.5K_0402_1%
LGATE
9
DL_1.5V
4
2
PC98
4.7U_0805_10V6K
1
+
2
2
PC95
220U_6.3V_M
10
+5VALW
2
1
PGND
8
7
C
GND
2
PC96
4.7U_0603_6.3V6K
3
2
1
VDDP
LX_1.5V
1
15
NC
14
1
PR130
4.7_1206_5%
PGOOD
CS
11
B+
+1.5VP
2
6
12
1
D
1
FB
PHASE
2
VDD
5
13
PQ35
VOUT
4
DH_1.5V
UGATE
1
@ JUMP_43X118
PL10
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
5
3
BOOT
TON
PC94
0.1U_0603_25V7K
1
2
3
2
1
PR131
100_0603_1%
1
2
2
1
PU10
EN/DEM
2
@PC93
@
PC93
.1U_0402_16V7K
2
PR129
2.2_0603_1%
1
+5VALW
4
BST_1.5V 1
1
<39,43> SYSON
PR128
0_0402_5%
1
2
2
PC97
680P_0603_50V8J
PR127
255K_0402_1%
1
2
PQ34
5
D
2
PC92
4.7U_0805_25V6-K
1
PC91
4.7U_0805_25V6-K
2
1
1.5V_B+
Ipeak=20A
Imax=14A
F=313kHZ
Total capacitor
1330u
ESR=2.55m ohm
C
PR134
10K_0402_1%
2
1
PR133
10K_0402_1%
1
2
PJ23
@ JUMP_43X79
2
1
1
+1.5V
B
VIN
VCNTL
6
2
GND
NC
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
+5VALW
1
2
1K_0402_1%
PC99
1U_0603_10V6K
1
+0.75VSP
2
1
PC102
0.1U_0402_10V7K
G2992F1U_SO8
2
1K_0402_1%
PR135
2
1
PR138
2
PQ36
SSM3K7002FU_SC70-3
S
1
1
4.7U_0805_6.3V6K
PC100
2
2
@ PC101
.1U_0402_16V7K
D
2
G
1
<46> 0.75VR_EN#
PR137
0_0402_5%
1
2
1
<9,46> SUSP
@ PR136
0_0402_5%
1
2
PU11
3
1
2
B
PC103
10U_0805_6.3V6M
A
A
Compal Secret Data
Issued Date
2009/01/23
Deciphered Date
2010/01/23
5
4
3
2
Title
+1.5VP/0.75VSP
Size
Document Number
Custom
Date:
NWQAA LA-6062P M/B
Sheet
1
53
of
59
Rev
2.0
2
1
2
1
2
1 @ PR145 1K_0402_1%
2
1 @ PR147 1K_0402_1%
CPU_VID3
2
1@ PR148 1K_0402_1%
CPU_VID3
2
1
PR149 1K_0402_1%
CPU_VID4
2
1@ PR151 1K_0402_1%
CPU_VID4
2
1
CPU_VID5
2
1 PR154 1K_0402_1%
CPU_VID5
2
1 @ PR155 1K_0402_1%
CPU_VID6
2
1@ PR157 1K_0402_1%
CPU_VID6
2
1
H_DPRSLPVR
2
1 PR160 1K_0402_1%
H_DPRSLPVR
2
1 @ PR161 1K_0402_1%
PR152 1K_0402_1%
PR158 1K_0402_1%
PQ37
H_PSI#
2
1
2
1
2
2
H
3
2
1
PL12
0.36UH_PCMC104T-R36MN1R17_30A_20%
UGATE2
PR168 0_0402_5%
G
PHASE2
3
2
1
3
2
1
2
0_0402_5%
2
VCC
BOOT
FCCM UGATE
PWM PHASE
GND
LGATE
UGATE_CPU3
7
PHASE_CPU3
4
LGATE_CPU3
1
2
1
2
4
2
1
1
PR173
10K_0402_5%
V2N
2
D
CP@ PC142
10U_1206_25V6M
CM@ PC142
10U_1206_25V6M
2
1
1
2
PC141
10U_1206_25V6M
2
1
PC140
10U_1206_25V6M
PC139
470P_0603_50V8J
2
1
2
@ PR216
0_0402_5%
1
2
V2N
@ PR218
0_0402_5%
1
2
V3N
VSUM-
B
VSUM+
ISEN1
Deciphered Date
2010/01/23
Title
+CPU_CORE
Size
C
Date:
5
4
3
A
Compal Secret Data
2009/01/23
Issued Date
6
+CPU_CORE
V1N
1
1
3
1
2
PR212
10K_0402_5%
2
PR211
3.65K_0805_1%
2
1
1
4
PR213
1_0402_5%
1
PR210
4.7_1206_5%
5
5
4
3
2
1
10K_0402_1%_ERTJ0EG103FA
CM@ PQ44
PH4
4
3
2
1
LGATE1
CP@ PQ44
PHASE1
7
Arrandale -- non mount,@
Clarksfield --mount
C
A
8
2
1
1
VSUM2
PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
Layout Note:
Place near Phase1 Choke
2
@ PR191
3.65K_0805_1%
2
1
1
PR190
4.7_1206_5%
2
1
2
3
2
1
3
2
1
PC143
0.22U_0603_25V7K
1
2
VSUM-
@ PR220
100_0402_1%
@ PR193
0_0402_5%
1
2V1N
@ PR197
0_0402_5%
1
PC150
680P_0603_50V8J
2 1
@ PR187
1_0402_5%
3
2
1
PR207 2.2_0603_1%
1
2 BOOT1_1
CE@ PQ44
2
PR214
1.37K_0402_1%
1
5
2
4
PC147
0.01U_0402_25V7K
1
@ PC186
1200P_0402_50V7K
PQ43
UGATE1
PR208
2.61K_0402_1%
2
1
PC144
0.047U_0402_16V7K
2
1
1
2
1
@ PR219 10_0402_5%
1
2
PC149
330P_0402_50V7K
1
2
0_0402_5%
2
2
PC148
1000P_0402_50V7K
PR217
1
PR206
82.5_0402_1%
1
2
PC146
330P_0402_50V7K
2
2
2
2
0_0402_5%
PC134
0.22U_0603_25V7K
1
1
@
E
+CPU_CORE
V3N
@ PR192
10K_0402_5%
@
VSSSENSE
VSUM+
VSUM1
PR209
PR204
10K_0402_1%
1
2
@ PR205 10_0402_5%
PC138 0.22U_0402_6.3V6K
1
0_0402_5%
2
PR203
2
+CPU_B+
BOOT1
ISEN1
PC133
1U_0603_10V6K
2
1
1
1
3
ISEN3
2
2
0_0402_5%
1
2
4
VSUM+
1
1
PR215
11K_0402_1%
2
1
ISEN2
1
1_0402_5%
2
+5VALW
PC135
0.22U_0603_25V7K
PR201
0_0402_5%
2
@
PC129
680P_0603_50V8J
@
4
<8> IMVP_IMON
1
0_0402_5%
2
+CPU_B+
PQ42
@ PQ41
4
Arrandale -- 2 phase 1H1L
Clarksfield --2 phase 1H2L
@ PL13
0.36UH_PCMC104T-R36MN1R17_30A_20%
5
5
0_0402_5%
2
@ PC122
10U_1206_25V6M
2
1
BOOST_CPU3
8
@ PC121
10U_1206_25V6M
2
1
1
PQ45
PC128
1U_0603_10V6K
2
1
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
PR186
1
PC145
0.22U_0603_10V7K
2
1
0_0402_5%
2
@ PC120
0.1U_0603_25V7K
2
1
5
6
3
2
1
1
2
@ PC123
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31
2
1
PU14
5
3
PR195
1
1
Layout Note:
PH3 place near
Phase1 L-MOS
<8> VSSSENSE
@ PC124
0.22U_0603_25V7K
PC151
.1U_0402_16V7K
@ PR200
PR202
<8> VCCSENSE
@ PQ40
@ PR184
0_0603_5%
2
PR198
1
PR199
412K_0402_1%
F
@ ISL6208CRZ-T_QFN8
PC130
2
ISEN3
2
+CPU_CORE
AGND
PR183
0_0402_5%
30
29
28
27
26
25
24
23
22
21
PR196
2.87K_0402_1%
1
2
1
C
41
PC137 0.22U_0402_6.3V6K
2
1
PC132
150P_0402_50V8J
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
+5VALW
390P_0402_50V7K
2
PC131
10P_0402_50V8J
2
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
11
12
13
14
15
16
17
18
19
20
PR194
562_0402_1%
1
2
1
1
1
2
PC126
22P_0402_50V8J
PC136 0.22U_0402_6.3V6K
2
1
PR188
8.06K_0402_1%
1
2
PC127
1000P_0402_50V7K
2
1
PR189
249K_0402_1%
1
2
1
D
ISEN2
+CPU_B+
+5VALW
PC119
1U_0603_10V6K
1
2
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
2
3
4
5
6
7
8
9
10
E
@
VSUM-
ISL62883HRZ-T_QFN40_5X5~D
PU13
V3N
2
2
PR180
1
2
147K_0402_1%
V1N
2
@ PR176
0_0402_5%
1
2
1
PR171
1_0402_5%
CE@ PC142
10U_1206_25V6M
PR179
<8> H_PSI#
+CPU_CORE
V2N
2
@ PR175
0_0402_5%
1
VSUM+
@ PR178 1K_0402_1%
1
2
+VTT
F
2
1
PR170
3.65K_0805_1%
2
1
PR174
1.91K_0402_1%
2
<30,43> VGATE
4
1
PR177
0_0402_5%
1
4
PR169
4.7_1206_5%
LGATE2
PC118
680P_0603_50V8J
CLK_ENABLE#
2
1
3
PQ38
CE@ PQ39
2
1
2
1
PR172
1.91K_0402_1%
1
2
+3VS
CP@ PQ39
5
<25> CLK_ENABLE#
4
5
<8> H_DPRSLPVR
CM@ PQ39
G
B
2
+
B+
Arrandale -- non mount,@
Clarksfield --mount
PC117
0.22U_0603_25V7K
1
2
PR166 2.2_0603_1%
BOOT2_2
1
2
BOOT2
1
2
+
1
4
+VTT
PR167 0_0402_5%
<43> VR_ON
+
1
PR163 1K_0402_1%
PR165 0_0402_5%
<8> CPU_VID6
1
PR164 0_0402_5%
<8> CPU_VID5
PL11
HCB4532KF-800T90_1812
1
2
1
2
CPU_VID2
@ PC115
0.1U_0603_25V7K
2
1
2
1
PR162 0_0402_5%
<8> CPU_VID4
CPU_VID1
1 PR146 1K_0402_1%
PC185
68U_25V_M_R0.36
2
1
1 PR144 1K_0402_1%
2
1
PC111
68U_25V_M_R0.36
1
PR159 0_0402_5%
<8> CPU_VID3
2
CPU_VID2
2
+CPU_B+
PC114
68U_25V_M_R0.36
<8> CPU_VID2
CPU_VID1
3
2
2
PR156 0_0402_5%
1 @ PR143 1K_0402_1%
PC113
10U_1206_25V6M
2
1
1
PR153 0_0402_5%
<8> CPU_VID1
2
PC116
10U_1206_25V6M
2
CPU_VID0
PC110
2200P_0402_50V7K
2
1
<8> CPU_VID0
1
1 PR142 1K_0402_1%
PC112
470P_0603_50V8J
2
1
PR150 0_0402_5%
H
4
2
CP@ PC109
10U_1206_25V6M
5
CPU_VID0
CM@ PC109
10U_1206_25V6M
2
1
6
CE@ PC109
10U_1206_25V6M
7
5
8
2
Document Number
Rev
2.0
NWQAA LA-6062P M/B
Sheet
54
1
of
59
A
B
C
D
E
F
G
H
2
APOP@ PC166
1000P_0402_50V7K
2
+GFX_COREP
1
2
APOP@
PR235
4.7_1206_5%
Ipeak=22A
Imax=15.4A
F=350kHZ
Total capacitor
720u
ESR=3.75m ohm
1
APOP@ PC161 +
390U_2.5V_M
APOP@
PC163
680P_0603_50V8J
2
APOP@
PH5
220K_0402_5%_ERTJ0EV224J~D
1
2
Place RTH1 close to inductor
on the same layer
1
1
APOP@
PR246
165K_0402_1%
2
2
APOP@ PC165
560P_0402_50V7K
APOP@ PC164
1000P_0402_50V7K
2
1
3
1
APOP@ PR247
37.4K_0603_1%
1
Connect to input caps
APOP@
PC153
10U_1206_25V6M
1
4
33
APOP@
PC152
10U_1206_25V6M
2
17
B+
1
5
1
12
2
APOP@ PC159
2.2U_0603_10V6K
APOP@ PQ46
5
3
2
1
GFX_DRVL
18
1
APOP@ PL16
0.36UH_PCMC104T-R36MN1R105_30A_20%
1
2
2
19
+5VS
APOP@ PQ47
1
20
3
2
1
CSCOMP
GFX_SW
4
16
CSREF
LLINE
CSFB
15
14
RT
2
25
VID6
27
26
VID5
VID4
VID3
28
13
12
GFX_RAMP
1
2
GFX_DRVH
21
GFX_RAMP-1
2
<9>
<9>
AGND
22
APOP@
APOP@
PR234
PC157
2.2_0603_1%
0.22U_0603_25V7K
2GFX_BOOST-11
2
APOP@ PR242
71.5K_0402_1%
2
1
APOP@ PR245
422K_0402_1%
11
IREF
9
GFX_IREF
GFX_CSCOMP 1
APOP@ PR239
80.6K_0402_1%
1
2
2
1
APOP@ PR240
237K_0402_1%
1
2 GFX_RPM
2
2
1
VCC_AXG_SENSE
VSS_AXG_SENSE
+GFX_B+
AGND
23 GFX_BOOST 1
GFX_CSCOMP
3
APOP@
PR248
1K_0402_1%
2
1
GFX_CSFB
APOP@
PR244
0_0402_5%
GFX_CSCOMP
APOP@
PR243
0_0402_5%
RAMP
ILIM
2
2
APOP@ PR238
10.7K_0402_1%
DRVL
PGND
GPU
APOP@ PR237
20K_0402_1%
Avoid high dV/dt
APOP@ PU15
COMP
GFX_VCC 7
GFX_ILIM 8
APOP@ PC162
470P_0402_50V8J
PVCC
24
1
FB
GFX_COMP 6
2
1
5
ADP3211AMNR2G_QFN32_5X5
GFX_RT
1
APOP@ PR236
1K_0402_1%
29
SW
FBRTN
RPM
2
2GFX_COMP-1
1
VID2
DRVH
CLKEN#
10
1
APOP@ PC160
47P_0402_50V8J
VID1
IMON
APOP@
PC154
1U_0805_25V6K
2
2
APOP@ PR241
340K_0402_1%
1
2
GFX_FB
2
30
BST
4
1
31
32
EN
PWRGD
3
APOP@ PC158
220P_0402_50V7K
VID0
1
GFX_IMON
2
1
VSS_AXG_SENSE
2
2
APOP@
PC156
1000P_0402_50V7K
VCC
1
APOP@
PL15
HCB4532KF-800T90_1812
2
1
PR227
PR226
PR225
PR224
PR223
PR231
GFX_VCC
2
APOP@
PR233
10K_0402_1%
<9>
<9>
<9>
GFXVR_VID_3
<9>
GFXVR_VID_4
<9>
GFXVR_VID_5
<9>
GFXVR_VID_6
<9>
GFXVR_EN
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
+GFX_B+
APOP@
PR228
10_0603_1%
+3VS
APOP@
PR232
6.98K_0402_1%
2
2
1
1
GFX_IMON
APOP@ PC155
0.056U_0402_16V7K
+5VS
GFX_EN 1
APOP@
1
APOP@
1
APOP@
1
APOP@
1
APOP@
1
APOP@
1
APOP@
1
APOP@
@ PR229
300K_0402_5%
PR222
1
PR221
+1.05VS
<9> GFXVR_IMON
GFXVR_VID_1
<9>
GFXVR_VID_2
1
GFXVR_VID_0
1
APOP@ PC167
1000P_0402_50V7K
Switchable -- mount
Non Swithchable--non mount @
Shortest the
net trace
4
4
2009/10/02
Issued Date
Compal Secret Data
Deciphered Date
2010/10/02
Title
+GFX_COREP
Size
B
C
D
E
F
G
Rev
2.0
NWQAA LA-6062P M/B
Date:
A
Document Number
Sheet
55
H
of
59
5
3
2
DH_VCORE
1
PR250 2.2_0603_1%
1
2
1
2
BST_VCORE
PC171
0.1U_0603_25V7K
2
PR139
1.5K_0402_1%
<28,32,46> VGA_PW ROK
1
2
D
+5VALW
1
PR140 3K_0402_1%
2
15
BOOT
1
2 PC172
3
2
1
16
UG
1
2
13
PGND
12
ISEN
11
DL_VCORE
PR260
4.75K_0402_1%
1
@ PC181
2200P_0402_25V7K
1
0.85V
0.85V
1.03V
0.95V
0.9V
PR260 = 4.75K
PR262 =14K
PR261 =56.2K
PR263=16.2K
PR260 = 4.75K
PR262 =14K
PR261 =56.2K
PR263=29.4K
PR260 = 4.75K
PR262 =14K
PR261 =56.2K
PR263=63.4K
1
2
4
Issued Date
2009/01/23
3
1
1
2
GPU_VID1 <13>
3
S
A
Compal Secret Data
@ PR266
22K_0402_1%
2
PR268
10K_0402_1%
1
2
Deciphered Date
2010/01/23
5
1
1
2
1
2
1
0.85V
GPU_VID0 <13>
@ PR269
22K_0402_1%
1
2
G
2
G
2
1
D
1
0
0
0.80V
2
1
0.80V
PQ52
SSM3K7002FU_SC70-3
0
N11E-GE1-LP
B
PR265
10K_0402_1%
1
2
S
PR267
100K_0402_1%
N11P-GE1
PC184
.1U_0402_16V7K
A
0
N11M-GE1/N11M-OP1
D
PC183
.1U_0402_16V7K
PR255=7.15K
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom)
GPU_VID1
PR264
100K_0402_1%
63.4K_0402_1%
+3VS_DGPU
GPU_VID0
2
29.4K_0402_1%
1
14K_0402_1%
PR261
56.2K_0402_1%
29.4K_0402_1%
1
PR262
Imax=16.8A
Ipeak=24A
Iocp=29.17A
29.4K_0402_1%
3
1
N11E-GE1_LP
16.2K_0402_1%
PQ51
SSM3K7002FU_SC70-3
PR255=7.15K
PQ50=unpop
2
+3VS_DGPU
PR263
CM@
PR263
AP@
PR263
APOP@
PR263
CP@
PR263
CE@
1
PR255=5.36K
PQ50=unpop
PC176
10U_1206_25VAK
2
@PC180
@
PC180
0.01U_0402_25V7K
AM@ PR263
16.2K_0402_1%
1
2
Imax=16.8A
Ipeak=24A
Iocp=29.17A
VDD_SENSE <14>
7.15K_0402_1%
2
Imax=16.09A
Ipeak=18.19A
Iocp=20.72A
0_0402_5%
PR256
1
PR257
10_0402_5%
1
2
C
1000P_0402_50V7K
@ PC182
2
1
2
B
N11P-GE1
2
7.15K_0402_1%
FSW=1/(75E-12*57.6K)=231.48KHz
N11M-GE1/OP1
PC174
390U_2.5V_M
1
2
1 2
+
PC175
680P_0603_50V8J
CE@ PQ50
5
7.15K_0402_1%
3
2
1
7.15K_0402_1%
4
1
2
1
2
2
5.36K_0402_1%
3
2
1
VO
PR255
CM@
PR255
APOP@
PR255
AP@
PR255
CP@
PR255
CE@
5.36K_0402_1%
PR254
4.7_1206_5%
1
2
2
4
AM@ PR255
.1U_0402_16V7K
@ PR258
49.9K_0402_1%
1
PQ49
5
ISEN_VCORE
.1U_0402_16V7K
@ PC179
22P_0402_50V8J
+VGA_COREP
0.56U_PCMC104T-R56MN_25A_20%
1
2
@ PC177
10U_1206_25VAK
LG
10
.1U_0402_16V7K
7
.1U_0402_16V7K
FB
.1U_0402_16V7K
FSET
EN
1
68K_0402_1%
2
PC178
AP@
PC178
AM@
PC178
CP@
PC178
CM@
PC178
CE@
1
,33,46> DGPU_PW R_EN
APOP@ PR270
1
PC178
APOP@
.1U_0402_16V7K
1
5
9
20K_0402_1%
2
2
C
14
4
APW 7138NITRL_SSOP16
57.6K_0402_1%
PR259
2
1
20K_0402_1%
AM@ PR253
1
PVCC
VCC
NC
20K_0402_1%
PR252
4.7_0603_5%
Ipeak=24A
Imax=16.8A
F=231.5kHZ
Total capacitor
1050u
ESR=3.1m ohm
PL18
4
6
20K_0402_1%
VIN
26268_VCC
1
2.2U_0603_6.3V6K
PC173
2.2U_0603_6.3V6K
2
1
20K_0402_1%
PHASE
3
6268_VCC
PR253
CE@
PR253
CP@
PR253
CM@
PR253
AP@
PGOOD
GND
PU16
8
PR251
0_0603_5%
PQ48
4.7U_0805_25V6-K
PC170
2
1
6268_VCC
5
D
10U_1206_25VAK
PC169
2
1
LX_VCORE
10U_1206_25VAK
PC168
2
1
PL17
HCB4532KF-800T90_1812
<39,43,46,49,52> SUSP#
1
2 B+_core
1
B+
4
2
Title
+VGA_COREP
Size
Document Number
Custom
Date:
NWQAA LA-6062P M/B
Sheet
1
56
of
59
Rev
2.0
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------EVT
P53-PWR_1.5VP/0.75VSP
Change PR132 18k to 6.19k
Modify 1.5V OCP to 18.09A
EVT
P56-PWR_VGA_COREP
Change PR270 0 to 100 Ohm
Adjust RC for Optimus sequence
(2009/11/25)
(2009/11/25)
Change PC178 0.1U to 0.01U
EVT
P39-PWR_+VTTP
Change PR141 2.26k to 2.43k
Modify VTTPWROK voltage (2009/11/25)
EVT
P39-PWR_+VTTP
Remove PC71 33P, PC72 2200P, PR101 33.2k
APW7138 not use this function
EVT
P38-PWR_3VALWP/5VALWP
Modify VS divider voltage to drive MOS
EVT
P56-PWR_VGA_COREP
Remove PC179 22P, PC181 2200P, PR258 49.9k
APW7138 not use this function
(2009/11/25)
EVT
P56-PWR_VGA_COREP
Modify VGA 11P OCP to 38.03A
(2009/11/25)
EVT
P56-PWR_VGA_COREP
Remove PC177 10U
FAE suggest to remove 1 10U cap for IC on time control
EVT
P42-PWR_CPU_CORE
Change PL12,PL14 SH000005680
EVT
P43-PWR_GM VGA_CORE
Change PH5 SL20000058L to SL200000500
Use Compal PN
DVT
P56-PWR_VGA_COREP
Modify VGA 11P OCP to 29.17A
DVT
P43-PWR_GM VGA_CORE
Change PL16 SH00000HK00
Use same PN choke
DVT
P39-PWR_+VTTP
Modify VTT voltage to 1.1V for Clarkfield
DVT
P42-PWR_CPU_CORE
Cost down
DVT
P43-PWR_GM VGA_CORE
Change PC114, PC111, PC185 from SF000000F80 to
SF000000W00
Change PC161 to SGA00002680
DVT
P56-PWR_VGA_COREP
Change PR253 0 to 20k
For VGA sequence(2009/12/28)
DVT
P56-PWR_VGA_COREP
Change PR270 0 to 20k
DVT
P52-PWR_1.05VSP/1.8VSP
Add PC83 0.1U and change PR122 0 to 68k
DVT
P48-PWR_BATTERY CONN / OTP
Add PD6, PD7 ESD diode
For ESD solution(2009/12/28)
DVT
P49-PWR_CHARGER
Add PC104,PC105,PC106 10U
Reserve for
DVT
Change PR83,PR84 0 to 2.2
Add boost resistor(For EMI solution)(2009/12/28)
Add PR85,PR86 4.7 and PC55,PC56 680P
Add snubber(For EMI solution)(2009/12/28)
DVT
P42-PWR_CPU_CORE
DVT
P55-PWR_GM VGA_CORE
to SH00000IK00
to SH00000IK00
Use 5% DCR choke
(2009/11/25)
(2009/11/25)
(2009/11/25)
(2009/12/28)
(2009/12/28)
(2009/12/28)
(2009/12/28)
For DVT budding(thermal issue), it will change to original type for PVT
Add PR169,PR210 4.7 and PC118,PC150 680P
Change PR234 0 to 2.2
Add PR235 4.7 and PC163 680P
DVT
P56-PWR_VGA_COREP
Add PR254 4.7 and PC175 680P
DVT
P48-PWR_BATTERY CONN / OTP
Change PR33 10k,PR31 21k to 19.6k, PR34 9.53k to
8.66k, PR40 47k to 7.87k
Adjust OTP setting point(2009/12/28)
DVT
P42-PWR_CPU_CORE
Add PQ39,PQ44 TPCA8028-H
Use 1H 2L MOS solution for Clarksfield (2009/12/31)
DVT
P42-PWR_CPU_CORE
Add PC109,PC142 10U input cap
For Clarksfield solution (2009/12/31)
DVT
P42-PWR_CPU_CORE
Adjust CPO_CORE OCP to 65A (2009/12/31)
DVT
P42-PWR_CPU_CORE
Adjust CPU_CORE load line (2009/12/31)
DVT
P42-PWR_CPU_CORE
Change PR204 8.25k to 10k
Adjust resistor for Imon (2009/12/31)
DVT
P39-PWR_+VTTP
Adjust VTT_DIS_Arrandale OCP to 29.73A (2009/12/31)
DVT
P53-PWR_1.5VP/0.75VSP
Adjust 1.5V OCP to 21.73A(2009/12/31)
DVT
Change PQ33 from FDS6670 to AO4712
Change design rating(2009/12/31)
DVT
P39-PWR_+VTTP
Adjust VTT_DIS_Clarksfield OCP to 20.64A (2009/12/31)
DVT
P55-PWR_GM VGA_CORE
Adjust GFX load line (2009/12/31)
DVT
Change PC90 SE025681K80
Use same PN (2009/12/31)
DVT
P56-PWR_VGA_COREP
Change PR270 20k to 68k, PC178 0.01U to 0.1U
Adjust Optimus sequence
PVT
Remove PR136, Add PR137 0 Ohm
For S3 power saving function
PVT
P43-PWR_GM VGA_CORE
Change PC161 to SF000002O00
Change to original type for PVT
PVT
P49-PWR_CHARGER
Change PC24,PC25,PC26 4.7U to 10U
For EMI solution(ISN test)
(2010/02/03)
PVT
P49-PWR_CHARGER
Add PC107 10U
(2010/02/03)
PVT
P49-PWR_CHARGER
Add PC104,PC105,PC106 10U
(2010/02/03)
PVT
Change PQ27 from SSMK7002 to DTC115EUA
Use low Vth Transistor
PVT
Change PR119 10k to 15.8k
Adjust 1.05V OCP to 8.47A
Issued Date
(2010/01/06)
(2010/02/03)
(2010/02/03)
(2010/02/03)
(2010/02/03)
Compal Secret Data
2009/01/23
(2009/12/28)
EMI solution(2009/12/28)
Change PR166,PR207 0 to 2.2
to SE024681J80
(2009/11/25)
(2009/11/25)
Deciphered Date
2010/01/23
Title
Power PIR
Size
Document Number
Rev
2.0
Calpella common
Date:
Sheet
57
of
59
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------Pre MP
Change PR123 316k to 25.5k,PR124 402k to 51.1k
Adjust 1.8V voltage divided resistor
Pre MP
Change PU9 from MP2121 to SY8033
MP2121 ESD fail
Pre MP
Delete PR125 0 Ohm
Change for SY8033 solution(2010/03/07)
(2010/03/07)
(2010/03/07)
Change PC85 from 0.1U to 22U
Delete PC87 10UF, PC84 0.1U
Pre MP
Change PC86 10U to 68P
Improve 1.8V transient under shoot(2010/03/07)
Pre MP
P49-PWR_CHARGER
Change PC24,PC25,PC26 10U to 4.7U
10U 0805 size price too high(2010/03/07)
Pre MP
P47-PWR_DCIN/DECTOR
Change PC12 from SE033105Z80 to SE000001380
Change PN(2010/03/07)
Pre MP
P49-PWR_CHARGER
Change PR68 from 53.6k to 24k, PR45 from
0.015 to 0.02 Ohm
Change CP from 90W to 75W(For cost down )(2010/03/07)
Pre MP
P49-PWR_CHARGER
Change PQ6,PQ7 from AO4407A to AO4435
Change MOS reting for 75W adapter(For cost down )(2010/03/07)
Pre MP
P56-PWR_VGA_COREP
Add PR264,PR267 100k
Use 100k resistor to pull high +3VS_DGPU(Set initial VID to P0 state)(2010/03/07)
Compal Secret Data
Issued Date
2009/01/23
Deciphered Date
2010/01/23
Title
Power PIR
Size
Document Number
Rev
2.0
Calpella common
Date:
Sheet
58
of
59
5
4
3
2
1
HW PIR (Product Improve Record)
D
C
B
A
NWQAA LA-6062P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2009/12/30
NO
DATE
PAGE MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
12/7
37
Add +5VALW and +5VL for JPIO pin5
For BACK_SENSE detect
2
12/7
46
Change PJ32 to R104 and PJ33 to R144
For discrete BOM structure
3
12/7
25
Remove JLVDS pin10 and pin12 for +LCDVDD_R
3D Panel max. current is 1.5A
4
12/8
45
Combine JTOUCH and JLP to JTPL and remove C648
For ME cost down
5
12/8
13
Add QV2, RV110, RV123 and RV124
For CLK_REQ_VGA# level shifter
6
12/14
25
Add C495 and C496
For RF request
7
12/15
33
Add R258
For OPTIMUS_EN#
8
12/15
34
Add C499
For power team request
9
12/17
45
Remove D19
Move D19 to LS-6061P
10
12/18
38
Reverse JBT pin definition
Due to pin reverse
11
12/18
42
Add RA42
For codec EC_MUTE# issue
12
12/21
41
Change JREAD to Push-push type (R015-211-LM-A)
For PRD update
13
12/21
25
Move LED_PWM and BKOFF#_R to JLVDS pin10 and pin12
For avoiding +LCD_INV short issue
14
12/22
44
Change H7 footprint to "DEBUG_PAD-MB-S"
For debug use
15
12/23
39
Add D24 and Q36 for BT_CTRL
For WLAN & BT combo module
16
12/23
33
Add R461
For CIR_EN#
17
12/24
25
Mount C236 and C268
For ESD request
18
12/24
37
Change JPIO footprint and reverse its pin definition
For ME request
19
12/24
27
Add R145
For U9 ESD damage issue
20
12/24
41
Add F3
For connector short issue
21
12/28
42
Change RA41 to SM01000CY00 (FBMA-10-100505-301T)
For EMI request
22
12/28
25
Remove L1
For 3D panel
23
12/29
42
Change RA1, RA18 and RA20 to SM01000B200
For RF request
24
12/29
25
Change C484 to 100P
For RF request
25
1/6
37
Change C426 to SF000001500
For cost down
26
1/12
38
Change R132 BOM from FLICA@ to FELICA@
For Felica issue
27
1/12
11
Change C218 to SF000002O00
For cost down
28
1/12
8
Change C144 to SF000002Z00
For thermal interfere issue
--------------------------------------------------------------------------------------------------------------------NWQAA LA-6062P SCHEMATIC CHANGE LIST
D
C
NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
1/15
42
Add RA43
For sleep & music on battery mode
2
1/15
46
Change +1.05VS_DGPU to N-MOS
For +1.05VS_DGPU drop issue
3
1/21
43
Add R462
Avoid VR_ON floating
4
1/25
44
Change UG3 to SA000022I00
For LDO issue
5
1/25
45
Change SW2 to @
For ME interfere issue
6
1/27
9
Change CV57, CV58 abd C271 to OS-CON
For cost down
7
2/1
25
Add +LCD_VDD to JLVDS pin18
For CMO 3D Panel
8
2/1
27
Add R208
For AOC monitor issue
9
2/1
43
Change U19 to SA00001J5A0
For KB926 E0 version
10
2/1
39
Add +1.5VS for J3G
For TV tuner MC770A
11
2/1
41
Remove F3
For UC1 ES2 sample
12
2/2
43
Add CAP_RST# to EC
For ESD issue
13
2/3
41
Change RC7 to 33 ohm
For EMI request
14
2/4
42
Remove RA40, add RA44 and RA22
For audio issue
15
2/4
14
Reserve VBIOS ROM
For SW request
16
2/5
32
Swap USB port4 and port8
For customer request
17
2/5
13
Reserve 27MHz crystal
For HDMI issue
18
2/9
40
Change LL1 to 2.2U and Cl13 to 4.7U
For Realtek request
19
2/10
41
Change RC7~RC14 to 22 ohm
For O2 request
20
2/10
27
Remove HDMI common mode choke
For cost down
B
NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
3/6
32
Change R390 to 1K
For Optimus sequence
2
3/6
33
Change R59 to 1K
3
3/6
27
Change Q18 and Q19 power to +3VS_DGPU
For GPU power rail
4
3/6
41
Add QC2 and RC16
For O2 B0 workaround
5
3/7
28
Change D13.2 power to +CHGRTC
For RTC issue
6
3/8
32
Add R333 and R334
7
3/8
25
Add BOM structure 3D@ and NO3D@
For 3D SKU PWM
8
3/8
13
Change YV1 to SJ100006R00
For cost down
9
3/11
46
Change C685 to 0603 size
For ME height limit
10
3/11
45
Change H15~H19 to H_3P3
For ME request
11
3/15
45
Remove SW2
For ESD request
12
3/15
42
Change CA9 and CA10 to 1U
For cut-off frequency
13
3/16
42
Change MONO_IN to AGND
For high frequency noise issue
NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
3/17
41
Change cardreader to JMB385/389
For customer request
2
3/18
34
Add R49
For CRT wave issue
3
3/19
13
Change LV3 to always stuff
For NVIDIA request
4
3/19
34
Change L12 to 2.2 ohm for Optimus SKU
For CRT wave issue
5
3/22
27
Add D54
For HDMI CEC issue
6
3/24
25
Chane C214 to 1U
For NALAA ESATA performance low issue
---------------------------------------------------------------------------------------------------------------------
A
Compal Secret Data
200910/9
Issued Date
Deciphered Date
2010/01/23
Title
Size
Document Number
Custom
HW-PIR
Rev
1.0
NWQAA LA-6062P M/B
Date:
5
4
3
2
Sheet
1
59
of
59

Compal LA-6062P - Schematics. www.s

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