PDF - InformaticaNapoli

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PDF - InformaticaNapoli
A
B
C
D
E
1
1
Compal Confidential
2
2
KAL90/KALH0 M/B Schematics Document
Intel Penryn Processor with Cantiga + DDRII + ICH9M
2008-12-17
3
3
REV:1.0
4
4
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Cover Page
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Wednesday, December 17, 2008
Sheet
E
1
of
52
A
B
C
Compal Confidential
Intel Penryn Processor
Fan Control
Model Name : KAL90/KALH0
D
page 40
uPGA-478 Package
(Socket P) page
1
HDMI Conn.
LCD Conn.
page 24
EMC 1402
ICS9LPRS387
page 16
4,5,6
1
667/800/1066MHz
H_D#(0..63)
page 23
Memory BUS(DDRII)
Intel Cantiga
LVDS
LVDS
Dual Channel
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
page 7,8,9,10,11,12,13
16X
VGA
DMI
page 30
USB conn x3
C-Link
page 17,18,19,20,21
PCI-Express
2
Intel ICH9-M
USB port 0, 2, 5
Bluetooth
Conn
CMOS
Camera
page 33
page 34
page 22
3.3V 48MHz
MINI Card x2
ATHEROS AR8121
WLAN, Robson2
page 33
page 31
2
HD Audio
page 25,26,27,28
GMCH HDA
page 34
port 2
port 1
ESATA
Conn.
page 34
page 32
AES1610
BGA-676
New Card
Socket
RJ45
LS-4494P
Finger Print
USB
3.3V 24.576MHz/48Mhz
S-ATA
LAN(GbE)
page 14,15
1.8V DDRII 533/667
uFCBGA-1329
PCI-Express
Card Reader
JMB385
Clock Generator
CRT Conn.
page 22
TMDS
Thermal Sensor
page 4
FSB
H_A#(3..35)
E
CDROM
Conn.
page 29
MDC 1.5
Conn
page 37
page 08
port 0
HDA Codec
VGA HDA
ALC888S-VC
page 38
SATA HDD
Conn.
page 29
page 18
Audio AMP
page 39
LPC BUS
3
3
RTC CKT.
Phone Jack x3
page 35
page 39
KAL90
page 37
page 37
LS-4498P
FUN Conn.
DC/DC Interface CKT.
page 44
Power Circuit DC/DC
page 44,45,46,47,48 ,49,50,51
Int.KBD
Touch Pad
LS-4493P
Media/B Conn.
Power On/Off CKT.
4
ENE KB926
KALH0
page 36
LS-4495P
EC I/O Buffer
USB/B Conn.
USB port 1
LS-4492P
page 36
BIOS
page 36
page 36
LS-5042P
E_KEY/B Conn.
LED/B Conn.
LS-4495P
CIR
page 37
LS-5041P
USB/B Conn.
4
Media/B Conn.
USB port 1
POWER SW
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Page 42
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Block Diagrams
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
E
2
of
52
A
B
C
Full ON
Power Plane
2
Description
S1
S3
HIGH
HIGH
ON
ON
ON
ON
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
N/A
N/A
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
OFF
+1.05VS
1.05V switched power rail
ON
OFF
OFF
+1.25VS
1.25V switched power rail
ON
OFF
OFF
+1.5V
1.5V power rail for HDA
ON
ON
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
Vcc
Ra/Rc/Re
+1.8VS
1.8V switched power rail
ON
OFF
OFF
Board ID
+1.1VS
1.1V switched power rail
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V
3.3V power rail for SB
ON
ON
X
+3V_LAN
3.3V power rail for LAN
ON
ON
X
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
0
1
2
3
4
5
6
7
+RTCVCC
RTC power
ON
ON
ON
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
Address
0001 011X b
MEDIA CONSOLE
1010 000X b
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
2
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
Interrupts
BTO Option Table
PCB Revision
0.1
0.2
0.3
1.0
1A
BTO Item
KAL90
UMA
PM@
ALC888VC
ALC888VB
AR8121
AR8112
ALC268
GL40
GM45
EC SM Bus2 address
Device
1
Board ID / SKU ID Table for AD channel
External PCI Devices
Smart Battery
Clock
HIGH
N/A
Device
+VS
HIGH
AC or battery power rail for power circuit.
EC SM Bus1 address
+V
LOW
Adapter power supply (19V)
REQ#/GNT#
+VALW
HIGH
B+
IDSEL#
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
S1(Power On Suspend)
VIN
Device
E
S5
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3
SIGNAL
STATE
Voltage Rails
1
D
BOM Structure
JAL90@
GM@
PM@
888VC@
888VB@
8121@
8112@
268@
GL40@
GM45@
3
Address
ADI ADT7421
1001 100X b
NB9M THERMAL SENSOR
BOM Configuration Table
Project
KAL90-UMA
KAL90-Dis
KAL90-GM45
KAL90-GL40
KAL90-PM45
ICH9M SM Bus address
Device
Address
Clock Generator
(ICS9LPRS387, SLG8SP556V)
1101 001Xb
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
BOM Configuration
XXXXXXXXXX:KAL90@/GM@/888VC@/8121@/GM45@
XXXXXXXXXX:KAL90@/PM@/888VC@/8121@
XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GM45@
XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GL40@
XXXXXXXXXX:KALH0@/PM@/888VC@/8121@
4
4
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Notes List
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
E
3
of
52
5
<7>
4
3
2
1
H_A#[3..35]
H_A#[3..35]
H_REQ#[0..4]
<7> H_REQ#[0..4]
H_RS#[0..2]
<7> H_RS#[0..2]
JCPU1A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
K3
H2
K2
J3
L1
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
H_A20M#
H_FERR#
H_IGNNE#
A6
A5
C4
<26> H_STPCLK#
<26>
H_INTR
<26>
H_NMI
<26>
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
<7>
B
CONTROL
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
H1
E2
G5
H_ADS#
H_BNR#
H_BPRI#
H5
F21
E1
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
F1
IERR#
INIT#
D20
B3
LOCK#
H4
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
HIT#
HITM#
G6
E4
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
<7>
<7>
<7>
H_BR0#
<7>
H_INIT#
<26>
D
H_IERR#
H_LOCK# <7>
H_RESET#
H_RS#0
H_RS#1
H_RS#2
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
H_RESET# <7>
H_TRDY#
<7>
H_HIT#
H_HITM#
<7>
<7>
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#
C
XDP_DBRESET#
<27>
+1.05VS
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
<26>
<26>
<26>
BR0#
ADDR GROUP_1
C
DEFER#
DRDY#
DBSY#
XDP/ITP SIGNALS
H_ADSTB#0
ADS#
BNR#
BPRI#
THERMTRIP#
H_PROCHOT#
H_THERMDA
H_THERMDC
D21
A24
B25
C7
H_THERMTRIP#
BCLK[0]
BCLK[1]
A22
A21
XDP_TDI
R2
1
2
54.9_0402_1%
XDP_TMS
R3
1
2
54.9_0402_1%
XDP_BPM#5
R5
1
2
54.9_0402_1%
H_PROCHOT#
R13
2
1
56_0402_5%
H_IERR#
R18
2
1
56_0402_5%
XDP_TRST#
R7
2
1
54.9_0402_1%
XDP_TCK
R8
1
2
54.9_0402_1%
left NC if no ITP
<8,26>
H CLK
@
39Ohm
CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>
Layout Note:
H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RESERVED
<7>
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP_0
D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
B
Penryn
CONN@
+3VS
C2
0.1U_0402_16V4Z
1
2
BSEL1
BSEL0
BCLK
0
0
0
266
1
0
U1
H_THERMDA
R17 @
56_0402_5%
200
2200P_0402_50V7K
2
1
1
166
VDD
SMCLK
8
EC_SMB_CK2
<18,35,36>
2
DP
SMDATA
7
EC_SMB_DA2
<18,35,36>
3
DN
ALERT#
6
4
THERM#
GND
5
H_THERMDC
1
2
R1133
10K_0402_5%
+3VS
B
2
0
1
1
C3
2
0
+1.05VS
1
BSEL2
E
H_PROCHOT#
3
1
C
A
OCP#
EMC1402-1-ACZL-TR_MSOP8
<27>
A
Q1
MMBT3904_SOT23-3
@
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Penryn (1/3)
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
4
of
52
5
4
3
H_D#[0..63]
2
H_D#[0..63]
<7>
<7>
<7>
H_DSTBN#0
H_DSTBP#0
H_DINV#0
C
2
+1.05VS
1
R27
1K_0402_1%
R29
2K_0402_1%
1
Width=4 mil ,
Spacing: 15mil
(55Ohm)
2
Trace Close CPU < 0.5'
<7>
<7>
<7>
R21
R22
H_DSTBN#1
H_DSTBP#1
H_DINV#1
GTL_REF0
1K_0402_5%
TEST1
1K_0402_5%
TEST2
TEST3
PAD
C1477 1
0.1U_0402_16V4Z TEST4
2
TEST5
PAD @
T2
TEST6
PAD
T3
@
<16> CPU_BSEL0@
<16> CPU_BSEL1
<16> CPU_BSEL2
2
2
@
@
@
1
1
T1
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Penryn
MISC
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
DATA GRP 2
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
DATA GRP 1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 3
D
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
JCPU1C
<7>
+CPU_CORE
JCPU1B
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
AA1
Y1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>
COMP0
COMP1
COMP2
COMP3
R26
R25
R24
R23
1
1
1
1
H_PWRGOOD
H_CPUSLP#
2
2
2
2
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
H_DPRSTP# <8,26,49>
H_DPSLP# <26>
H_DPWR# <7>
H_PWRGOOD <26>
H_CPUSLP# <7>
PSI#
<49>
CONN@
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)
B
1
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[01]
VCCA[02]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VCCSENSE
VCCSENSE
VSSSENSE
AE7
VSSSENSE
VSSSENSE <49>
+CPU_CORE
D
C
+1.05VS
20mils
+1.5VS
1
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
1
R28
CONN@
C7
C8
<49>
<49>
0.01U_0402_16V7K
<49>
2
2
<49>
<49>
10U_0805_10V4Z
<49>
<49>
1
2
100_0402_1%
B
+CPU_CORE
<49>
2
100_0402_1%
R30
.
1
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Penryn (2/3)
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
5
of
52
5
4
3
2
1
JCPU1D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
D
C
B
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
Penryn
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
+CPU_CORE
D
1 2
+
C55
900P_PFAF250E128MNTTE_2.5VM
3 4
+CPU_CORE
C
1
1
C416
1
C425
C426
1
C427
1
1
C428
C429
1
1
C430
C431
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
B
+CPU-CORE
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
C,uF
ESR, mohm
ESL,nH
4X330uF
6m ohm/4
1.8nH/6
32X22uF
3m ohm/32
0.6nH/32
32X10uF
3m ohm/32
0.6nH/32
+1.05VS
CONN@
1
.
+ C1478
1
C45
1
C46
1
C47
1
C48
1
C49
1
C50
330U_D2E_2.5VM_R15
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Penryn (3/3)
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
6
of
52
4
3
<5>
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1
+1.05VS
R47
2
221_0402_1%
2
H_SWING
1
R55
1
100_0402_1%
2
width=10mil
C59
0.1U_0402_16V4Z
H_RCOMP
1
width=10mil
R54
2
24.9_0402_1%
B
H_SWING
H_RCOMP
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C5
E3
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
J8
L3
Y13
Y1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
2
+1.05VS
H_A#[3..35]
U2A
H_D#[0..63]
D
C
2
HOST
5
R46
<4>
<5>
H_RESET#
H_CPUSLP#
1
1K_0402_1%
C12
E11
H_AVREF
A11
B11
1
width:spacing=10mil:20mil (<0.5")
H_RESET#
H_CPUSLP#
1
2
R52
2K_0402_1%
2
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA ES_FCBGA1329
C58 @
1
<4>
D
H_ADS#
<4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR#
<4>
H_BPRI# <4>
H_BR0#
<4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT#
<4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
C
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
B
H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>
H_REQ#[0..4]
H_RS#[0..2]
<4>
<4>
GM45@
0.1U_0402_16V4Z
within 100mil to Ball A11,B11
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Cantiga GMCH(1/7)-GTL
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
7
of
52
5
4
3
2
1
+1.8V
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_9
MCH_CFG_10
Use VGATE for GMCH_PWROK
VGATE
@
1
R1139
ICH_PWROK 1
R1140
<16,27,49> VGATE
<27> ICH_PWROK
GMCH_PWROK
2
0_0402_5%
2
0_0402_5%
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
CFG
2 PM_EXTTS#0
10K_0402_5%
2 PM_EXTTS#1
10K_0402_5%
2 MCH_CLKREQ#
10K_0402_5%
1
R38
1
R39
1
R40
+3VS
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
DDRA_CLK0#
DDRA_CLK1#
DDRB_CLK0#
DDRB_CLK1#
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
BC28
AY28
AY36
BB36
DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1
BA17
AY16
AV16
AR13
DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#
BD17
AY17
BF15
AY13
DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
BG22
BH21
SMRCOMP
SMRCOMP#
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
AV42
AR36
BF17
BC36
SM_PWROK
SM_REXT
R34
R35
1
2
1
<14>
<14>
<15>
<15>
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AE41
AE37
AE47
AH39
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AE40
AE38
AE48
AH40
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
AE35
AE43
AE46
AH42
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
AD35
AE44
AF46
AH43
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
<14>
<14>
<15>
<15>
+1.8V
2
B
E
2
E
Q75
MMBT3904_SOT23-3
Q76
MMBT3904_SOT23-3
3
2
330_0402_5%
2
B
3
2
C
1
C
2
1
R1152
MCH_TSATN#
MCH_TSATN_EC# <35>
1
1
R1148
1K_0402_5%
R1150
54.9_0402_1%
A
1
1
SM_VREF
2 0_0402_5%
2 499_0402_1%
2.2U_0603_6.3V6K
2
1
2
R1135
0_0402_5%
R48
1K_0402_1%
@
CLK_DREF_96M <16>
CLK_DREF_96M# <16>
CLK_DREF_SSC <16>
CLK_DREF_SSC# <16>
1
0.1U_0402_16V4Z
2
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
<27>
<27>
<27>
<27>
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
<27>
<27>
<27>
<27>
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
<27>
<27>
<27>
<27>
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
<27>
<27>
<27>
<27>
+DIMM_VREF
N28
M28
G36
E36
K36
H36
TSATN#
B12
CLK_DREF_SSC
CLK_DREF_SSC#
R1137 1 PM@
R1138 1 PM@
2
2
0_0402_5%
0_0402_5%
CL_RST#0 <27>
C
011 = FSB667
010 = FSB800
000 = FSB1067
CFG[2:0]
0 = DMI x 2
1 = DMI x 4
CFG5
* (Default)
0 = iTPM Host Interface is enabled
CFG6
CFG9
1 = iTPM Host Interface is Disabled
0 = Lane Reversal Enable
1 = Normal Operation * (Default)
CFG10
0 = PCIe Loopback Enable
1 = Disable * (Default)
00
01
10
11
CFG[13:12]
= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation *
*(Default)
(Default)
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled * (Default)
0 = Normal Operation
*(Default)
1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
* (Default)
1 = PCIE/SDVO are operating simu.
B
L_DDC_DATA
0 = No SDVO Card Present
* (Default)
1 = SDVO Card Present
0 = LFP Disable
* (Default)
1 = LFP Card Present; PCIE disable
DDPC_CTRLDATA
0 = Digital DisplayPort Disable
* (Default)
1 = Digital DisplayPort Device Present
R43
1K_0402_1%
C56
1
CL_VREF
MCH_CFG_5
MCH_CFG_6
R44
511_0402_1%
1
PAD T34 @
0.1U_0402_16V4Z
PAD T35 @
2
MCH_CLKREQ# <16>
MCH_ICH_SYNC# <27>
MCH_CFG_7
MCH_CFG_9
MCH_CFG_10
MCH_CFG_12
MCH_TSATN#
MCH_CFG_13
B28
B30
B29
C29
A28
2
R1146
2
R79
2
R81
2
R84
2
R86
2
R77
2
R78
2
R1149
@
@
@
@
@
@
@
@
1
2.21K_0402_1%
1
4.02K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
A
MCH_CFG_19
2 @
R73
MCH_CFG_20
2 @
R75
Notice: Please check HDA power rail to select HDA controller.
1
4.02K_0402_1%
1
4.02K_0402_1%
+3VS
GM45@
Compal Electronics, Inc.
Compal Secret Data
2008/11/10
Issued Date
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
0_0402_5%
0_0402_5%
2
ICH_PWROK
CL_CLK0 <27>
CL_DATA0 <27>
Security Classification
5
2
2
MCH_CFG_16
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
0.01U_0402_16V7K
R1134 1 PM@
R1136 1 PM@
CFG20
(PCIE/SDVO select)
MCH_CLKREQ#
C53
CLK_DREF_96M
CLK_DREF_96M#
C34
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
2
Strap Pin Table
B33
B32
G33
F33
E33
AH37
AH36
AN36
AJ35
AH34
D
as close as possible to the related balls
CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>
+1.05VS
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
0.01U_0402_16V7K
2
C54
1K_0402_1%
1
ME
CANTIGA ES_FCBGA1329
MISC
R1147
1K_0402_5%
1
+1.05VS
HDA
1
+3VS
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC
+3VS
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
1
R33
+1.8V
2 80.6_0402_1%
2 80.6_0402_1%
1
SDVO_CTRLDATA
GFX_VR_EN
C51
1
80 Ohm
CFG19
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
2
SM_RCOMP_VOL
For Cantiga
C57
F43
E43
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
2.2U_0603_6.3V6K
2
3.01K_0402_1%
SM_DRAMRST# would be
needed for DDR3 only
20mil
R36
R37
CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#
PEG_CLK
PEG_CLK#
1
R45 @
1K_0402_1%
B38
A38
E41
F41
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
1
1
SM_RCOMP_VOH
1
C52
R32
<14>
<14>
<15>
<15>
2
SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1
1K_0402_1%
<14>
<14>
<15>
<15>
2
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
R31
2
<17,25,27,30,31,35> PLT_RST#
<4,26> H_THERMTRIP#
<27,49> PM_DPRSLPVR
R1143 1
R1144 1
R1145 1
R29
B7
N33
P32
AT40
AT11
T20
R32
PM
<27> PM_SYNC#
<5,26,49> H_DPRSTP#
<14> PM_EXTTS#0
<15> PM_EXTTS#1
PM_SYNC#_R
PM_DPRSTP#_R
PM_EXTTS#0
PM_EXTTS#1
GMCH_PWROK
2 100_0402_5% MCH_RSTIN#
THERMTRIP#_R
2 0_0402_5%
DPRSLPVR_R
0_0402_5%
2
2 0_0402_5%
2 0_0402_5%
AR24
AR21
AU24
AV20
<14>
<14>
<15>
<15>
CFG16
B
R1141 1
R1142 1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GRAPHICS VID
<16> MCH_CLKSEL0
<16> MCH_CLKSEL1
<16> MCH_CLKSEL2
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
DMI
C
DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1
1
RSVD22
RSVD23
RSVD24
RSVD25
CLK
BG23
BF23
BH18
BF18
RSVD20
AP24
AT21
AV24
AU20
2
AY21
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
1
RSVD15
RSVD16
RSVD17
RSVD
B31
B2
M1
All RSVD balls on GMCH should be left No
Connect.
DDR CLK/ CONTROL/
D
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
COMPENSATION
U2B
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
3
2
Title
Cantiga GMCH(2/7)-DMI/DDR
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
8
of
52
5
4
DDRA_SDQ[0..63]
<15> DDRB_SDM[0..7]
DDRA_SMA[0..14]
<15> DDRB_SMA[0..14]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..14]
D
B
U2E
SA_BS_0
SA_BS_1
SA_BS_2
BD21
BG18
AT25
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
SA_RAS#
SA_CAS#
SA_WE#
BB20
BD20
AY20
DDRA_SRAS# <14>
DDRA_SCAS# <14>
DDRA_SWE# <14>
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
<14>
<14>
<14>
A
MEMORY
SYSTEM
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
DDR
C
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
CANTIGA ES_FCBGA1329
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
GM45@
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
BC16
BB17
BB33
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
SB_RAS#
SB_CAS#
SB_WE#
AU17
BG16
BF14
DDRB_SRAS# <15>
DDRB_SCAS# <15>
DDRB_SWE# <15>
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
B
U2D
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
MEMORY
<14> DDRA_SMA[0..14]
1
SYSTEM
D
<15> DDRB_SDQ[0..63]
DDRA_SDM[0..7]
<14> DDRA_SDM[0..7]
2
DDR
<14> DDRA_SDQ[0..63]
3
CANTIGA ES_FCBGA1329
<15>
<15>
<15>
C
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
B
GM45@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Cantiga GMCH(3/7)-DDR
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
9
of
52
5
4
3
2
1
U2C
<22> GMCH_LCD_CLK
<22> GMCH_LCD_DATA
<22> GMCH_ENVDD
D
1
R1155
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
C44
B43
E37
E38
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
GMCH_TXCLKGMCH_TXCLK+
C41
C40
B37
A37
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
H47
E46
G40
A40
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
<22> GMCH_TXCLK<22> GMCH_TXCLK+
<22> GMCH_TXOUT0<22> GMCH_TXOUT1<22> GMCH_TXOUT2<22> GMCH_TXOUT0+
<22> GMCH_TXOUT1+
<22> GMCH_TXOUT2+
C
LVDS
LVDS_IBG
2.37K_0402_1%
2
1
R1153 GM@ 0_0402_5%
2
GM@
L32
G32
M32
M33
K33
J33
M29
GRAPHICS
ENBKL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA
Change to 0Ohm when use PM chip
GMCH_TV_COMPS
GMCH_TV_LUMA
H24
TV_RTN
2
2
R93
75_0402_1%
GM@
TV_DCONSEL_0
TV_DCONSEL_1
1
1
R108
75_0402_1%
GM@
1
R107
75_0402_1%
GM@
TVA_DAC
TVB_DAC
TVC_DAC
C31
E32
Change to 0Ohm when use PM chip
<23> GMCH_CRT_R
B
150_0402_1%
+3VS
R1164 1 GM@
2 2.2K_0402_5%
GMCH_LCD_CLK
R1166 1 GM@
2 2.2K_0402_5%
GMCH_LCD_DATA
R1167 1 GM@
2 10K_0402_5%
LCTLB_DATA
R1168 1 GM@
2 10K_0402_5%
LCTLA_CLK
R1169 1 GM@
2 2.2K_0402_5%
GMCH_CRT_CLK
R1170 1 GM@
2 2.2K_0402_5%
GMCH_CRT_DATA
G28
CRT_GREEN
1
150_0402_1%
J28
CRT_RED
150_0402_1%
G29
CRT_IRTN
H32
J32
J29
E29
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
L29
CRT_VSYNC
1
GMCH_CRT_CLK
GMCH_CRT_DATA
2
R1162 PM@
1
2
R1163 PM@
1
CRT_IREF
0_0402_5%
0_0402_5%
T37
T36
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
10mils
1
R57
2
49.9_0402_1%
+1.05VS
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
<17>
PCIE_MTX_C_GRX_P[0..15]
<17>
PCIE_GTX_C_MRX_N[0..15]
<17>
PCIE_GTX_C_MRX_P[0..15]
<17>
D
C
C1290 1
C1292 1
C1294 1
C1296 1
C1298 1
C1300 1
C1302 1
C1304 1
C1306 1
C1308 1
C1310 1
C1312 1
C1314 1
C1316 1
C1318 1
C1320 1
C1289 1
2 PM@ 0.1U_0402_16V7K
C1291 1
2 PM@ 0.1U_0402_16V7K
C1293 1
0.1U_0402_16V7K
2
PM@
C1295 1
2 PM@ 0.1U_0402_16V7K
C1297 1
2 PM@ 0.1U_0402_16V7K
C1299 1
2 PM@ 0.1U_0402_16V7K
C1301 1
2 PM@ 0.1U_0402_16V7K
C1303 1
2 PM@ 0.1U_0402_16V7K
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PM@
0.1U_0402_16V7K
PCIE_MTX_C_GRX_N4
2
PCIE_MTX_C_GRX_N5
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PM@
0.1U_0402_16V7K
PCIE_MTX_C_GRX_N8
2
PCIE_MTX_C_GRX_N9
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PM@
0.1U_0402_16V7K
PCIE_MTX_C_GRX_N12
2
PCIE_MTX_C_GRX_N13
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
C1305 1
2 PM@ 0.1U_0402_16V7K
C1307 1
PM@
0.1U_0402_16V7K
2
C1309 1
2 PM@ 0.1U_0402_16V7K
C1311 1
PM@
0.1U_0402_16V7K
2
C1313 1
2 PM@ 0.1U_0402_16V7K
C1315 1
2 PM@ 0.1U_0402_16V7K
C1317 1
2 PM@ 0.1U_0402_16V7K
C1319 1
2 PM@ 0.1U_0402_16V7K
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PM@
0.1U_0402_16V7K
PCIE_MTX_C_GRX_P14
2
PCIE_MTX_C_GRX_P15
B
R1165
1.02K_0402_1%
GM@
CANTIGA ES_FCBGA1329
GM45@
1
<23> GMCH_CRT_VSYNC
CRT_BLUE
1
<23> GMCH_CRT_CLK
<23> GMCH_CRT_DATA
<23> GMCH_CRT_HSYNC
E28
VGA
2 GM@
R1159
2 GM@
R1160
2 GM@
R1161
<23> GMCH_CRT_G
TV_DCONSEL_0
TV_DCONSEL_1
PEG_COMP
PEG_COMPI
PEG_COMPO
2
<23> GMCH_CRT_B
TV
2
GMCH_TV_CRMA
F25
H25
K25
PCI-EXPRESS
<18,35>
<22> DPST_PWM
1
2
R1154 GM@ 0_0402_5%
A
A
R1173 1
2 100K_0402_5%
Compal Electronics, Inc.
Compal Secret Data
Security Classification
LBKLT_EN
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Cantiga GMCH(4/7)-VGA/LVDS/TV
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
10
of
52
5
4
U2F
3
2
1
+VGFX_CORE
+1.8V
B
PAD
PAD
VCC_AXG_SENSE
VSS_AXG_SENSE
AJ14
AH14
VCC_AXG_SENSE
VSS_AXG_SENSE
A
CANTIGA ES_FCBGA1329
+1.05VS
1
+ C131
C124
C132
1
C133
U2G
C125
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
220U_D2_4VM_R15
0.22U_0402_6.3V6K
0.1U_0402_16V4Z
2
2
2
10U_0805_10V4Z
0.22U_0402_6.3V6K
Cavity Capacitors
J1 @
JUMP_43X79
1
+1.05VS
1
VCC_AXG: 6326.84mA
(330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
+VGFX_CORE
2
2
C1479
GM@
1
2
R1174 GM@
0_0805_5%
1
1
1
C1482
GM@ 1
10U_0805_10V4Z
0.47U_0603_16V4Z
2
2
J2 @
JUMP_43X79
C1481
GM@ 2
1U_0402_6.3V6K
R1175
0_0402_5%
PM@
1
C1484
GM@ 1
0.1U_0402_16V4Z
C1483
GM@ 2
10U_0805_10V4Z
2
2
1
C1480
GM@ 2
0.1U_0402_16V4Z
Cavity Capacitors
1
+
C1485
GM@
330U_D2E_2.5VM_R15
2
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
+1.8V
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
C
+1.05VS
VCC_SM: 2600mA
(330UF*1, 22UF*2, 0.1UF*1)
1
C126
330U_D2E_2.5VM_R15 +
2
1
1
1
C130
10U_0805_10V4Z
2
C122 2
10U_0805_10V4Z
C123
0.1U_0402_16V4Z
2
Place on the edge
Reference PILLAR_ROCK CRB Rev1.0
VCC_SM_BA36
VCC_SM_BB24
VCC_SM_BD16
VCC_SM_AW16
VCC_SM_AT13
C1486
@
0.1U_0402_16V7K
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
AV44
BA37
AM40
AV21
AY5
AM10
BB13
C1488
@
1 0.1U_0402_16V7K
1
1
2
C1487
@ 2
0.1U_0402_16V7K
2
1
C1490
@
1
0.1U_0402_16V7K
C1489
2
@
0.1U_0402_16V7K
2
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C139
1
CANTIGA ES_FCBGA1329
C140
1
C141
1
C142
1
C143
1
C144
1
C145
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
B
GM45@
1
A
0.1U_0402_16V7K
0.22U_0402_6.3V6K
0.47U_0603_16V4Z
1U_0402_6.3V6K
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.22U_0402_6.3V6K
1U_0402_6.3V6K
GM45@
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
Place close to the GMCH
GFX
@
T4
@
T5
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
D
1
VCC
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
VCC: 1930.4mA (GMCH), 1210.34mA (MCH)
(270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
+1.05VS
NCTF
+VGFX_CORE
Place close to the GMCH
VCC
VCC_SM_AT13
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC
VCC_SM_AW16
BA36
BB24
BD16
BB21
AW16
AW13
AT13
POWER
VCC_SM_BA36
VCC_SM_BB24
VCC_SM_BD16
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
POWER
GFX NCTF
C
VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC CORE
SM
Pins BA36, BB24, BD16,
BB21, AW16, AW13, AT13
could be left NC for DDR2
board.
VCC
Reference PILLAR_ROCK CRB Rev1.0
2600mA
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC SM LF
D
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
4
3
2
Title
Cantiga GMCH(5/7)-VCC
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
11
of
52
5
4
3
2
1
+1.05VS_HPLL
+1.05VS_DPLLA
1
L18 GM@
0_1210_5%
2
0.1U_0402_16V4Z
2
1
C1497
GM@
1
F47
+1.05VS_DPLLB
L48
VCCA_DPLLB
+1.05VS_HPLL
AD1
VCCA_HPLL
+1.05VS_MPLL
AE1
VCCA_MPLL
VCCA_LVDS: 13.2mA
(1000PF*1)
J48
VCCA_PEG_BG: 0.414mA
(0.1UF*1)
C89
0.1U_0402_16V4Z
2
No CIS Symbol
L21 1
2
MBK1608221YZF_0603
2
1
1
2
C1503
R1181
10U_0805_6.3V6M 1_0402_1%
+1.05VS
AA48
C95
+
C94
@
220U_D2_4VM_R15
2
+1.05VS_A_SM_CK
+3VS_DACBG
1
2
R103
0_0603_5%
1
1
R1184
0_0402_5%
PM@
VCCA_SM_CK: 24mA
(22UF*1, 2.2UF*1, 0.1UF*1)
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
1
1
1
C102
C103
C105
@
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
2
2
2
22U_0805_6.3V6M
2
L23
GM@
MBK1608221YZF_0603 1
1
1
C1509
C1510
C1511
GM@
GM@
@
0.1U_0402_16V4Z
10U_0805_6.3V6M
2
2
2
0.01U_0402_16V7K
1
2
C96
C97
4.7U_0805_10V4Z
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V6K
+1.05VS
NO_STUFF
Close to Ball A25
VCCA_TV_DAC: 40mA (0.1UF*1,
0.01UF*1 for each DAC)
1
C1518 Close
GM@
0.1U_0402_16V4Z
2
A32
L28
+1.5VS_QDAC
+1.05VS_HPLL
C1520
1
C1521
1
+1.8V
180Ohm@100MHz
C1524
1
C1525
1
0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K
48.363mA
VCCD_QDAC
VCCD_HPLL
50mA
VCCD_PEG_PLL
1
2
R1191 GM@
0_0603_5%
VCCD_LVDS_1
VCCD_LVDS_2
BF21
BH20
BG20
BF20
R1195
0_0402_5%
@
VCC_HV: 105.3mA
C35
B35
A35
+3VS
1
2
+1.8V_TX_LVDS
0.1uH 20%
1
2
R1183 GM@
1
C1512
C1513
0_0603_5%
GM@
GM@
1000P_0402_50V7K
2
2 10U_0805_10V4Z
Please check Power
source if want
support IAMT
0.1U_0402_16V4Z
+1.05VS_PEG: 1782mA +1.05VS_PEG
(220UF*1, 22UF*1, 4.7UF*1)
V48
U48
V47
U47
U46
+1.8V
1
C107
1
1
+ C1515
C1514
10U_0805_10V4Z
2
2
1
2
R1186
0_0805_5%
+1.05VS
B
220U_D2_4VM_R15
+1.05VS
AH48
AF48
AH47
AG47
+1.05VS_DMI
VCC_DMI: 456mA
(0.1UF*1)
1
2
VTTLF1
VTTLF2
VTTLF3
1
2
1
2
R1182
C1508
1_0402_1% 10U_0805_6.3V6M
0.1U_0402_16V4Z
R1185
PM@
0_0402_5%
TV
CANTIGA ES_FCBGA1329
C1507
1
2
R1190
0_0805_5%
C1519
0.1U_0402_16V4Z
VTTLF_CAP1
A8
VTTLF_CAP2
L1
AB2 VTTLF_CAP3
C110
1
C111
1
C112
1
0.47U_0603_16V4Z
0.47U_0603_16V4Z
2
2
2
0.47U_0603_16V4Z
GM45@
+1.8V_LVDS
1
1
C1523
R1192
GM@
0_0402_5%
1U_0402_6.3V6K PM@
2
2
2008/11/10
Issued Date
3
A
R1194
D8
+1.05VS
1
1
2
+3VS
10_0603_5%
CH751H-40PT_SOD323-2
Compal Electronics, Inc.
Compal Secret Data
Security Classification
4
+1.05VS
1
2
+1.8V
L22
MBK1608121YZF_0603
K47
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Please check Power
source if want
support IAMT
1
2
R1180
0_0603_5%
+1.8V_TX_LVDS: 118.8mA
(22UF*1, 1000PF*1)
VCCD_LVDS: 60.311111mA
(1UF*1)
1
1
2
R1193
100_0603_1%
2
+1.5VS
M38
L37
C1522
GM@
10U_0805_6.3V6M
2
VCCD_QDAC: 48.363mA +1.5VS_QDAC
(0.1UF*1, 0.01UF*1)
VCCD_TVDAC
2
1782mA
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
456mA
60.31mA
VCCD_PEG_PLL: 50mA
(0.1UF*1)
Also power for internal
Thermal Sensor
0.1U_0402_16V4Z
2
2
0.022U_0402_16V7K
A
AA47
D
1
1
2
L25
MBK1608221YZF_0603
+1.05VS_PEGPLL
Please check Power
source if want
support IAMT
0.47U_0603_16V4Z
1uH 30%
1
2
+1.5VS
+1.5VS_TVDAC
C81
1U_0402_6.3V6K
2
B22
B21
A21
105.3mA
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
157.2mA
AF1
VCC_TX_LVDS
50mA
58.696mA
M25
1
C1506
2
VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)
118.8mA
VCC_HDA
to A32
+1.5VS_TVDAC
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
DMI
1
2
R1188 @
0_0402_5%
R1189
0_0402_5%
VCCD_HPLL: 157.2mA (0.1UF*1)
VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)
24mA
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
VCCA_TV_DAC_1
VCCA_TV_DAC_2
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VTTLF
+1.5VS
1
R1187
0_0402_5%
PM@
2
1
1
C1517
C1516
GM@
GM@
0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K
1
C82
C
HDA
VCCD_HDA: 50mA
(0.1UF*1)
+1.5VS_HDA
1
L24 1
2
MBK1608221YZF_0603
2
+3VS
1
C80
+1.8V_SM_CK
87.79mA
B24
A24
+3VS_TVDAC
+3VS_TVDAC
180Ohm@100MHz GM@
1
C1505
@
10U_0805_6.3V6M
2
POWER
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
D TV/CRT
VCCA_DAC_BG: 2.6833333mA
(0.1UF*1, 0.01UF*1)
1
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
AXF
1
2
R100
0_0805_5%
Please check Power
source if want
support IAMT
PLL
480mA
VCCA_SM:
(22UF*2, 4.7UF*1, 1UF*1)
1
C72
VCC_AXF: 321.35mA
(10UF*1, 1UF*1)
(0.1UF*1)
0.1U_0402_16V4Z
1
+
220U_D2_4VM_R15
4.7U_0805_10V4Z
2
2
2
2
4.7U_0805_10V4Z
2.2U_0603_6.3V6K
+1.05VS_AXF
HV
Please check Power
source if want
support IAMT
VCCA_PEG_PLL
50mA
+1.05VS_A_SM
1
VCCA_PEG_BG
50mA
+1.05VS_PEGPLL
VCCA_PEG_PLL:
1
C1504
2
C
+1.05VS
VSSA_LVDS
0.414mA
AD48
PEG
Close to Ball A26, B27
VCCA_LVDS
A PEG A LVDS
1
1
139.2mA
13.2mA
J47
Please check Power
source if want
support IAMT
2
1
C1502
R1179
GM@
0_0402_5%
0.01U_0402_16V7K PM@
2
+VCCA_PEG_BG
24mA
SM CK
R97
0_0402_5%
1
2
1
C1499
GM@
1000P_0402_50V7K
2
A CK
+1.5VS
+1.8V_TX_LVDS
A SM
+3VS_CRTDAC
+3VS
R96 @
0_0402_5%
1
2
+3VS
B
64.8mA
VCCA_DPLLA
LVDS
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)
+3VS
VSSA_DAC_BG
2
C1498
22U_0805_6.3V6M
2
1
VCCA_DAC_BG
B25
R1178
0_0402_5%
PM@ +1.05VS_DPLLA
C1496
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
GM@
1
1
2
L20 GM@
MBK1608301YZF_0603 1
C1500
1
GM@
+
C1501
0.1U_0402_16V4Z
2
GM@
220U_D2_4VM_R15
2
A25
1
C71
1
2
R1177
0.5_0603_1%
+3VS_DACBG
1
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
2
1
C1495
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
2.69mA
+1.05VS_DPLLB
L19 1
2
MBK1608121YZF_0603
VCCA_MPLL: 139.2mA
(22UF*1, 0.1UF*1)
B27
A26
VTT: 852mA
(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
+1.05VS
852mA
73mA
VTT
120Ohm@100MHz
D
VCCA_DPLLA
VCCA_DPLLB: 64.8mA
(220UF*1, 0.1UF*1)
Please check Power
source if want
support IAMT
+1.05VS_MPLL
U2H
1
1
C1494
R1176
+
C1493
GM@
0_0402_5%
GM@
PM@
2
220U_D2_4VM_R15
+3VS_CRTDAC
2
0.1U_0402_16V4Z
CRT
4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z
Please check Power
source if want
support IAMT
2
1
C1492
1
L17 GM@
0_1210_5%
+1.05VS
1
(4.7UF*1, 0.1UF*1)
1
2
L16 1
2
MBK1608121YZF_0603
1
C1491
VCCA_HPLL: 24mA
+1.05VS
2
Title
Crestline GMCH (6/7)-VCC
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 27, 2008
Sheet
1
12
of
52
5
4
3
B
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
BA16
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS_351
VSS_352
VSS_353
VSS_354
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS NCTF
C
1
U2J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS SCB
D
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
NC
U2I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
2
CANTIGA ES_FCBGA1329
GM45@
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
D
C
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
B
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
CANTIGA ES_FCBGA1329
GM45@
A
A
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Cantiga GMCH(1/7)-GTL
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
13
of
52
5
4
+1.8V
3
2
+1.8V
+1.8V
JDIMM1
<9> DDRA_SDQS0#
<9> DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
D
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
<9> DDRA_SDQS1#
<9> DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
<9> DDRA_SDQS2#
<9> DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
C
DDRA_CKE0
<8> DDRA_CKE0
DDRA_SBS2#
<9> DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
<9> DDRA_SBS0#
<9> DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
<9> DDRA_SCAS#
<8> DDRA_SCS1#
DDRA_ODT1
<8> DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
<9> DDRA_SDQS4#
<9> DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
B
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
<9> DDRA_SDQS6#
<9> DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
D_CK_SDATA
D_CK_SCLK
<15,16> D_CK_SDATA
<15,16> D_CK_SCLK
+3VS
A
1
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
+DIMM_VREF
DDRA_SDQ4
DDRA_SDQ5
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
20mils
R1196
DDRA_SDM0
1
DDRA_SDQ6
DDRA_SDQ7
2
DDRA_SDQ12
DDRA_SDQ13
1K_0402_1%
C151
20mils
To SODIMM and GMCH
+DIMM_VREF
0.1U_0402_16V4Z
D
R1197
DDRA_SDM1
1K_0402_1%
DDRA_CLK0 <8>
DDRA_CLK0# <8>
DDRA_SDQ14
DDRA_SDQ15
DDRA_SMA[0..14]
<9> DDRA_SMA[0..14]
DDRA_SDQ[0..63]
<9> DDRA_SDQ[0..63]
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDM[0..7]
<9> DDRA_SDM[0..7]
+1.8V
PM_EXTTS#0 <8>
DDRA_SDQ22
DDRA_SDQ23
C152
1
C153
1
C154
1
C155
1
DDRA_SDQS3# <9>
DDRA_SDQS3 <9>
+1.8V
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1
C147
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
2
2
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
1
+0.9VS
DDRA_CKE0
1
DDRA_SBS2#
2
RP1
DDRA_CKE1 <8>
4
3
56_0404_4P2R_5%
C156
1
C148
1
C149
1
C157
C
1
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13
DDRA_SMA12
1
DDRA_SMA9
2
RP2
4
3
56_0404_4P2R_5%
DDRA_SMA8
DDRA_SMA5
1
2
4
3
56_0404_4P2R_5%
1
2
4
3
56_0404_4P2R_5%
DDRA_SMA10
1
DDRA_SBS0#
2
RP5
4
3
56_0404_4P2R_5%
DDRA_SWE#
1
DDRA_SCAS#
2
RP6
4
3
56_0404_4P2R_5%
DDRA_SCS1#
1
DDRA_ODT1
2
RP7
4
3
56_0404_4P2R_5%
DDRA_SMA14
1
DDRA_SMA11
2
RP8
4
3
56_0404_4P2R_5%
RP3
DDRA_SMA3
DDRA_SMA1
DDRA_SBS1# <9>
DDRA_SRAS# <9>
DDRA_SCS0# <8>
RP4
DDRA_ODT0 <8>
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
C158
1
C159
1
C160
1
C161
1
C162
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
DDRA_SDQS5# <9>
DDRA_SDQS5 <9>
DDRA_SMA7
DDRA_SMA6
1
C164
C165
1
C166
RP9
4
3
56_0404_4P2R_5%
1
2
RP10
4
3
56_0404_4P2R_5%
DDRA_SMA0
1
DDRA_SBS1#
2
RP11
4
3
56_0404_4P2R_5%
C168
DDRA_SRAS#
1
DDRA_SCS0#
2
RP12
4
3
56_0404_4P2R_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
DDRA_SMA13
1
DDRA_ODT0
2
RP13
4
3
56_0404_4P2R_5%
DDRA_CKE1
2
56_0402_5%
DDRA_SMA4
DDRA_SMA2
DDRA_CLK1 <8>
DDRA_CLK1# <8>
1
1
C167
1
B
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
C163
+0.9VS
1
C169
1
C170
1
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQS7# <9>
DDRA_SDQS7 <9>
1
R1198
DDRA_SDQ62
DDRA_SDQ63
R116 1
R115 1
2 10K_0402_5%
2 10K_0402_5%
FOX_ASOA426-M4R-TR
CONN@
+3VS
C171
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
DDRA_SDQS0#
DDRA_SDQS0
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
1
DDRA_SDQ0
DDRA_SDQ1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
+DIMM_VREF
1
A
C172
1
DIMM0 REV H:10.1mm (BOT)
0.1U_0402_16V4Z
2
2
2.2U_0603_6.3V6K
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
DDRII-SODIMM0
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
14
of
52
A
B
C
D
+DIMM_VREF
+1.8V
DDRB_SDQ0
DDRB_SDQ5
1
<9> DDRB_SDQS0#
<9> DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
<9> DDRB_SDQS1#
<9> DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
<9> DDRB_SDQS2#
<9> DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
2
DDRB_SDQ26
DDRB_SDQ27
<8> DDRB_CKE0
<9> DDRB_SBS2#
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
<9> DDRB_SBS0#
<9> DDRB_SWE#
<9> DDRB_SCAS#
<8> DDRB_SCS1#
<8> DDRB_ODT1
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
<9> DDRB_SDQS4#
<9> DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
3
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
<9> DDRB_SDQS6#
<9> DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
<14,16> D_CK_SDATA
<14,16> D_CK_SCLK
4
D_CK_SDATA
D_CK_SCLK
+3VS
+1.8V
+1.8V
1
JDIMM2
+DIMM_VREF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
C173
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
E
DDRB_SDQ4
DDRB_SDQ1
1
C182
1
+
2.2U_0603_6.3V6K
2
2
0.1U_0402_16V4Z
1
+
C1526
2
DDRB_SDM0
2
C1527
@
330U_D2E_2.5VM_R15
330U_D2E_2.5VM_R15
1
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_CLK0 <8>
DDRB_CLK0# <8>
DDRB_SDQ14
DDRB_SDQ15
<9> DDRB_SMA[0..14]
<9> DDRB_SDQ[0..63]
<9> DDRB_SDM[0..7]
DDRB_SMA[0..14]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
PM_EXTTS#1 <8>
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
+1.8V
DDRB_SDQS3# <9>
DDRB_SDQS3 <9>
+0.9VS
2
DDRB_SDQ30
DDRB_SDQ31
DDRB_SBS2#
DDRB_CKE0
1
2
RP14
4
3
56_0404_4P2R_5%
DDRB_SMA14
DDRB_SMA12
DDRB_SMA9
1
2
RP15
4
3
56_0404_4P2R_5%
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA5
DDRB_SMA8
1
2
RP16
4
3
56_0404_4P2R_5%
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SMA3
DDRB_SMA1
1
2
RP17
4
3
56_0404_4P2R_5%
DDRB_SMA10
DDRB_SBS0#
1
2
RP18
4
3
56_0404_4P2R_5%
DDRB_SWE#
DDRB_SCAS#
1
2
RP19
4
3
56_0404_4P2R_5%
DDRB_SCS1#
DDRB_ODT1
1
2
RP20
4
3
56_0404_4P2R_5%
DDRB_SMA11
DDRB_SMA14
1
2
RP21
4
3
56_0404_4P2R_5%
DDRB_SMA6
DDRB_SMA7
1
2
RP22
4
3
56_0404_4P2R_5%
DDRB_SMA2
DDRB_SMA4
1
2
RP23
4
3
56_0404_4P2R_5%
DDRB_SBS1#
DDRB_SMA0
1
2
RP24
4
3
56_0404_4P2R_5%
DDRB_CKE1
DDRB_CKE1 <8>
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13
DDRB_SBS1# <9>
DDRB_SRAS# <9>
DDRB_SCS0# <8>
DDRB_ODT0 <8>
DDRB_SDQ36
DDRB_SDQ37
C174
1
C175
1
C176
1
C183
1
C177
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
2
2
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+1.8V
C178
1
C179
1
C180
1
C181
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQS5# <9>
DDRB_SDQS5 <9>
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_CLK1 <8>
DDRB_CLK1# <8>
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SCS0#
DDRB_SRAS#
1
2
RP25
4
3
56_0404_4P2R_5%
DDRB_SMA13
DDRB_ODT0
1
2
RP26
4
3
56_0404_4P2R_5%
DDRB_CKE1
1
R1199
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQS7# <9>
DDRB_SDQS7 <9>
2
56_0402_5%
2 10K_0402_5%
2 10K_0402_5%
1
C185
1
C186
1
C187
1
C188
1
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
C189
1
C190
1
C191
1
C192
1
C193
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
C194
1
C195
1
C196
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
DDRB_SDQ62
DDRB_SDQ63
R119 1
R118 1
C184
+3VS
4
FOX_AS0A426-N8RN-7F
CONN@
DIMM1 REV H:5.6mm (BOT)
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
DDRII-SODIMM1
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
E
15
of
52
A
FSLC
B
FSLB
FSLA
CLKSEL2 CLKSEL1 CLKSEL0
C
CPU
MHz
SRC
MHz
PCI
MHz
0
0
0
266
100
33.3
0
1
0
200
100
33.3
0
1
1
166
100
33.3
D
Control
CR#_6(MCH)
PCIEX6
CR#_4(NEW CARD)
PCIEX4
CR#_9(MINI CARDII)
PCIEX9
+3VS
U43
CLK_DREF_SSC_1
CLK_DREF_SSC
R1756 0_0402_5%
PM@ 1
2
PCIEX0
2 GM@
1CLK_DREF_SSC#
R1827
0_0402_5%
PCIEX1
<8>
1
6
2
10K_0402_5%
1
GM@ 2
CLK_PCI4
1
R1587
10K_0402_5%
CPUT0_LPR_F
VDDPCI
CPUC0_LPR_F
70
CLK_CPU_BCLK#
27
VDDPLL3
55
VDDSRC
27M_SSC <18>
52
2
10K_0402_5%
<27> H_STP_PCI#
68
CLK_MCH_BCLK
67
CLK_MCH_BCLK#
SRCT0_LPR/DOTT_96_LPR
24
CLK_DREF_96M
SRCC0_LPR/DOTC_96_LPR
25
CLK_DREF_96M#
3
S
CK_PWRGD
CLK_ENABLE#
38
VDDSRC_IO
62
VDDSRC_IO
CLK_PCI_ICH
<25> CLK_PCI_ICH
10P_0402_50V8J CLK_PCI_ICH
For EMI 10/9
R1589 2
54
PCI_STOP#
1
2
R1597 @
1K_0402_5%
1 33_0402_5%
0_0402_5%
0_0402_5%
2
2
@
1 R1591
1 R1592
C1900
1
2
27P_0402_50V8J
R1593 @
56_0402_5%
R1595
1K_0402_5%
1
2
1
R1598
0_0402_5%
2
C1901
27P_0402_50V8J
1
2
MCH_CLKSEL0
R1596 2
1 33_0402_5%
CLK_ICH_14M
R1599 2
1 33_0402_5%
2
CPU_BSEL1
<8>
<27,31,33,34>
ICH_SMBDATA
1
3
S
2
G
MCH_CLKSEL1
A
2
1
CK505_PWRGD 1
5
4
2
G
3
2
S
CLK_MCH_3GPLL#
SRCT7_LPR
61
CLK_PCIE_VGA
SRCC7_LPR
60
CLK_PCIE_VGA#
<8>
<8>
<17>
CLK_PCIE_VGA#
CLK_PCIE_READER#
NC
SRCT9_LPR
44
CLK_PCIE_MINI2
SRCC9_LPR
45
CLK_PCIE_MINI2#
<17>
UMA: disable this pair by BIOS
CLK_PCIE_READER
CLK_PCIE_MINI2
SRCT10_LPR
50
CLK_PCIE_MINI1
SRCC10_LPR
51
CLK_PCIE_MINI1#
SRCT11_LPR
48
CLK_PCIE_LAN
SRCC11_LPR
47
CLK_PCIE_LAN#
<30>
CLK_PCIE_READER#
<30>
<33>
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
3
<33>
<33>
CLK_PCIE_MINI1#
<33>
FSLC/TEST_SEL/REF0
REF1
GNDCPU
3
GNDREF
CR#3
37
18
GNDPCI
CR#4
41
22
GND48
CR#6
58
GND
CR7#
65
GND
CR#9
43
CLK_PCIE_LAN
CLK_PCIE_LAN#
1
R1603
2
10K_0402_5%
GNDSRC
CR10#
49
59
GNDSRC
CR#11
46
42
73
GNDSRC
GND_THERMAL_PAD
CR#A
21
1
R1606
1
R1607
2
10K_0402_5%
2
10K_0402_5%
<31>
<31>
+3VS
EXP_CLKREQ# <34>
MCH_CLKREQ#
(Pull High to +3VS at GMCH side)
34
D_CK_SCLK
<34>
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CPUC2_ITP_LPR/SRCC8_LPR 63
69
30
<34>
CLK_PCIE_CARD#
CLK_MCH_3GPLL
X2
FSLB/TEST_MODE
+3VS
56
X1
USB_48MHz/FSLA
Q108
2N7002_SOT23
R1611
1K_0402_5%
1
2
1
R1613
0_0402_5%
1
57
CLK_PCIE_READER
2
+3VS
SRCT6_LPR
CPUT2_ITP_LPR/SRCT8_LPR 64
20
7
<27>
CLK_PCIE_CARD
SRCC6_LPR
CK_PWRGD/PD#
CLKSEL1
CLKSEL2
<27>
CLK_PCIE_ICH#
CLK_MCH_3GPLL
2
<26>
PCI_F5/ITP_EN
CLKSEL0
26
D
2
1
R1612 @
0_0402_5%
R1609 @
1K_0402_5%
ICH_SMBCLK
CLK_PCIE_CARD
CLK_PCIE_ICH
PCI3
+3VS
<27,31,33,34>
CLK_PCIE_ICH#
15
D_CK_SDATA
R1608
4.7K_0402_5%
1
2
CLK_PCIE_ICH
36
CLK_PCI3
Q107
2N7002_SOT23
<5>
+1.05VS
R1610
10K_0402_5%
CLKSEL2 1
2
R1602
4.7K_0402_5%
1
2
35
CLK_PCIE_CARD#
+3VS
D
1
2
R1600 @
1K_0402_5%
SRCT3_LPR
SRCC3_LPR
<26>
CLK_PCIE_SATA#
40
11
CLK_ICH_48M
CLK_PCIE_SATA
SRCT4_LPR
8
1
R1605
0_0402_5%
SRCC2_LPR/SATAC_LPR
CLK_PCIE_SATA#
SRCC4_LPR
CLK_XTALOUT
Y1
14.31818MHz_20P_FSX8L14.318181M20FDB
<5>
<27> CLK_ICH_14M
2
CLK_PCIE_SATA
33
PCI2/TME
+1.05VS
R1601
1K_0402_5%
1
2
32
<8>
<27> CLK_ICH_48M
CPU_BSEL0
VGA: disable this pair by BIOS
SRCT2_LPR/SATAT_LPR
PCI4/27_SELECT
<8>
VGA: disable this pair by BIOS
CLK_DREF_SSC#_1
PCI1
17
<8>
CLK_DREF_96M#
CLK_DREF_SSC_1
14
16
<7>
CLK_DREF_96M
CLK_PCI2
CLK_PCI5
<7>
CLK_MCH_BCLK#
39
CLK_PCI4
<4>
CLK_MCH_BCLK
13
CLK_XTALIN
1
2
1
R1594
2.2K_0402_5%
CLKSEL0 1
2
4
27MHz_SS/SRCC1_LPR/SE2 29
VDD96_IO
H_STP_PCI#
1 33_0402_5%
R1590 2
<27> CK_PWRGD
<8,27,49> VGATE
+1.05VS
1
R1604 @
0_0402_5%
VDDCPU_IO
23
CPU_STOP#
2
2
CLKSEL1
66
10P_0402_50V8J CLK_PCI_LPC
2
@
3
VDDPLL3_IO
27MHz_NonSS/SRCT1_LPR/SE1 28
53
@
C1899 1
31
H_STP_CPU#
<49>
CLK_PCI_LPC
<35> CLK_PCI_LPC
C1898 1
VDDSRC_IO
<4>
CLK_CPU_BCLK#
CPUT1_LPR_F
1
2
G
Q106 @
2N7002_SOT23
<14,15>
CLK_CPU_BCLK
CPUC1_LPR_F
D
CLK_PCI4=0, Pin28, 29 is SRC_CLK
Pin24, 25 is DOT96_CLK
@
1
R1588
<27> H_STP_CPU#
CK505_PWRGD
D_CK_SCLK
VDDCPU
+3VS
CLK_PCI5=0, Pin63,64 is SRC_CLK
CLK_PCI5=1, Pin63,64 is ITP_CLK
CLK_CPU_BCLK
12
<8>
mount to Enable ITP_CLK
R1583 @
10K_0402_5%
D_CK_SCLK
<14,15>
VDD48
2
1
R1586
10
CLK_DREF_SSC#
CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed)
2
SCLK
D_CK_SDATA
71
Must Close to CLKGEN PIN 28,29
CLK_PCI5
D_CK_SDATA
72
+CLK_VDDSRC
PM@ 2
CLK_PCI4
1
R1829
10K_0402_5%
CLK_PCI2
1
2
R1584
10K_0402_5%
9
SDATA
19
CLK_DREF_SSC#_1
2 PM@
1
R1828
0_0402_5%
VDDREF
ICS9LPRS387, PN:SA000020H10
SLG8SP556V, PN:SA000020K00
27M_CLK <18>
SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable]
2
10K_0402_5%
Clock Generator
L57
2
1
KC FBM-L11-201209-221LMAT_0805
1
1
1
1
1
1
1
1
C1891
C1892
C1893
C1894
C1895
C1896
C1897
C1890
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
@
1
R1585
H
+CLK_VDD
+CLK_VDD
R1755 0_0402_5%
2 GM@
1 CLK_DREF_SSC
Free-Run
PCIEX10
G
+CLK_VDDSRC
Table : ICS9LPRS387
CLK_REQ#
F
L56
2
1
KC FBM-L11-201209-221LMAT_0805
1
1
1
1
1
1
1
1
C1883
C1884
C1885
C1886
C1887
C1888
C1889
C1882
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VS
1
CR#_10(WLAN)
E
<8>
+3VS
MINI2_CLKREQ#
<33>
MINI1_CLKREQ#
<33>
SATA_CLKREQ#
<27>
+3VS
4
(Pull High to +3VS at ICH side)
ICS9LPRS387BKLFT_MLF72_10x10
MCH_CLKSEL2
Issued Date
CPU_BSEL2
Compal Electronics, Inc.
Compal Secret Data
Security Classification
<8>
2008/11/10
Deciphered Date
<5>
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
C
D
E
F
Title
Clock Generator (CK505)
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
G
Sheet
16
of
H
52
A
B
C
D
LVDS & DAC Interface
E
PEG Interface
U17F
NB9M-GS_BGA_533P
COMMON
#SI Change to +VDDMEM18
Y4
W4
VGA_TXOUT2- <22>
VGA_TXOUT2+ <22>
IFPA_TXD3
IFPA_TXD3
AB5
AB4
IFPB_TXD4
IFPB_TXD4
V1
W1
1/13 PCI_EXPRESS
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
R205
@
1K_0402_1%
AE9
#SI Change to +VDDMEM18
+VDD_MEM18
IFPB_TXD5
IFPB_TXD5
W2
W3
IFPB_TXD6
IFPB_TXD6
AA3
AA2
B
100 mA
2
1
L8 PM@
BLM18PG181SN1D_0603
IFPA_IOVDD
1
1
C251
PM@
2 4.7U_0603_6.3V6M 2
IFPB_IOVDD
C267
PM@
470P_0402_50V7K
2
C266
PM@
4700P_0402_25V7K
1
V3
IFPA_IOVDD
V2
IFPB_IOVDD
IFPB_TXD7
IFPB_TXD7
A
<8,25,27,30,31,35>
IFPA_TXC
IFPA_TXC
AD4
AC4
IFPB_TXC
IFPB_TXC
AB2
AB3
B
2 C280
PM@
470P_0402_50V7K
C279
PM@
4700P_0402_25V7K
2
R204 PM@
0_0402_5%
1
PLT_RST#
<16> CLK_PCIE_VGA
<16> CLK_PCIE_VGA#
AA1
AB1
VGA_TXCLK- <22>
VGA_TXCLK+ <22>
CLOCK
1
<10> PCIE_GTX_C_MRX_P0
<10> PCIE_GTX_C_MRX_N0
PM@
2
PEX_RST#
AD9
PEX_REFCLKP
PEX_REFCLKN
AB10
AC10
AE12
AF12
PEX_RX0
PEX_RX0
PM@C270
PM@
C270 1
PM@C271 1
PM@C271
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP1 AD12
PEX_TXN1 AC12
PEX_TX1
PEX_TX1
AG12
AG13
PEX_RX1
PEX_RX1
PEX_TXP2 AB11
PEX_TXN2 AB12
PEX_TX2
PEX_TX2
AF13
AE13
PEX_RX2
PEX_RX2
PEX_TXP3 AD13
PEX_TXN3 AD14
PEX_TX3
PEX_TX3
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
<10> PCIE_GTX_C_MRX_P3
<10> PCIE_GTX_C_MRX_N3
PM@C283 1
PM@C283
PM@C284
PM@
C284 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
AE15
AF15
PEX_RX3
PEX_RX3
PM@C291 1
PM@C291
PM@C292
PM@
C292 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP4 AD15
PEX_TXN4 AC15
PEX_TX4
PEX_TX4
AG15
AG16
PEX_RX4
PEX_RX4
PM@C293 1
PM@C293
PM@C294
PM@
C294 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP5 AB14
PEX_TXN5 AB15
PEX_TX5
PEX_TX5
AF16
AE16
PEX_RX5
PEX_RX5
<10> PCIE_MTX_C_GRX_P3
<10> PCIE_MTX_C_GRX_N3
<10> PCIE_GTX_C_MRX_P4
<10> PCIE_GTX_C_MRX_N4
<10> PCIE_MTX_C_GRX_P4
<10> PCIE_MTX_C_GRX_N4
<10> PCIE_GTX_C_MRX_P5
<10> PCIE_GTX_C_MRX_N5
<10> PCIE_MTX_C_GRX_P5
<10> PCIE_MTX_C_GRX_N5
U17D
NB9M-GS_BGA_533P
COMMON
1 R206
<10> PCIE_GTX_C_MRX_P6
<10> PCIE_GTX_C_MRX_N6
5/13 DACC
DACC_VDD
2
W5
10K_0402_5%
R6
DACC_VREF
V6
DACC_RSET
PM@C301 1
PM@C301
PM@C302
PM@
C302 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP6 AC16
PEX_TXN6 AD16
PEX_TX6
PEX_TX6
AE18
AF18
PEX_RX6
PEX_RX6
PM@C303 1
PM@C303
PM@C304
PM@
C304 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP7 AD17
PEX_TXN7 AD18
PEX_TX7
PEX_TX7
AG18
AG19
PEX_RX7
PEX_RX7
PM@C305 1
PM@C305
PM@C306
PM@
C306 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP8 AC18
PEX_TXN8 AB18
PEX_TX8
PEX_TX8
AF19
AE19
PEX_RX8
PEX_RX8
AB19
AB20
PEX_TX9
PEX_TX9
AE21
AF21
PEX_RX9
PEX_RX9
<10> PCIE_MTX_C_GRX_P6
<10> PCIE_MTX_C_GRX_N6
DACC_HSYNC U6
DACC_VSYNC U4
DAC C
<10> PCIE_GTX_C_MRX_P7
<10> PCIE_GTX_C_MRX_N7
<10> PCIE_MTX_C_GRX_P7
<10> PCIE_MTX_C_GRX_N7
DACC_RED T5
DACC_GREEN T4
<10> PCIE_GTX_C_MRX_P8
<10> PCIE_GTX_C_MRX_N8
DACC_BLUE R4
<10> PCIE_MTX_C_GRX_P8
<10> PCIE_MTX_C_GRX_N8
<10> PCIE_GTX_C_MRX_P9
<10> PCIE_GTX_C_MRX_N9
PM@
3
PM@C307 1
PM@C307
PM@C308
PM@
C308 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP9
PEX_TXN9
PM@C309 1
PM@C309
PM@C310
PM@
C310 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP10 AD19
PEX_TXN10 AD20
PEX_TX10
PEX_TX10
AG21
AG22
PEX_RX10
PEX_RX10
<10> PCIE_MTX_C_GRX_P9
<10> PCIE_MTX_C_GRX_N9
U17C
BLM18PG181SN1D_0603
NB9M-GS_BGA_533P
COMMON
150 mA
+3VS
2
DACA_VDD
1
L9 PM@
AG2
C319
PM@
2
C320
PM@
1
2
C321
PM@
124_0402_1%
2
1
2
1
0.1U_0402_16V4Z
C317
PM@
1
470P_0402_50V7K
2
4700P_0402_25V7K
1U_0402_6.3V6K
DACA_VREF
1
CRT
<10> PCIE_GTX_C_MRX_P10
<10> PCIE_GTX_C_MRX_N10
<10> PCIE_MTX_C_GRX_P10
<10> PCIE_MTX_C_GRX_N10
3/13 DACA
DACA_VDD
AF1
DACA_VREF
AE1
DACA_RSET
<10> PCIE_GTX_C_MRX_P11
<10> PCIE_GTX_C_MRX_N11
DAC A
R207
PM@
DACA_HSYNC
DACA_VSYNC
AD2
AD1
VGA_CRT_HSYNC
VGA_CRT_VSYNC
DACA_RED
AE2
VGA_CRT_R
<23>
DACA_GREEN
AE3
VGA_CRT_G
<23>
DACA_BLUE
AD3
VGA_CRT_B
<23>
2
PM@
DACB_VDD
10K_0402_5%
D7
1
1
1
R196
PM@
<10> PCIE_GTX_C_MRX_P12
<10> PCIE_GTX_C_MRX_N12
DACB_VREF
F8
DACB_RSET
PEX_TX11
PEX_TX11
AF22
AE22
PEX_RX11
PEX_RX11
PM@C322 1
PM@C322
PM@C323
PM@
C323 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEX_TXP12 AB21
PEX_TXN12 AB22
PEX_TX12
PEX_TX12
AE24
AF24
PEX_RX12
PEX_RX12
PEX_TXP13 AC22
PEX_TXN13 AD22
PEX_TX13
PEX_TX13
AG24
AF25
PEX_RX13
PEX_RX13
PEX_TXP14 AD23
PEX_TXN14 AD24
PEX_TX14
PEX_TX14
AG25
AG26
PEX_RX14
PEX_RX14
PEX_TXP15AE25
PEX_TXN15AE26
PEX_TX15
PEX_TX15
AF27
AE27
PEX_RX15
PEX_RX15
<10> PCIE_MTX_C_GRX_P12
<10> PCIE_MTX_C_GRX_N12
PM@C324 1
PM@C324
PM@C326
PM@
C326 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
<10> PCIE_MTX_C_GRX_P13
<10> PCIE_MTX_C_GRX_N13
<10> PCIE_GTX_C_MRX_P14
<10> PCIE_GTX_C_MRX_N14
R197
PM@
4/13 DACB
DACB_VDD
G6
PEX_TXP11 AD21
PEX_TXN11 AC21
PM@C328 1
PM@C328
PM@C329
PM@
C329 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
<10> PCIE_MTX_C_GRX_P14
<10> PCIE_MTX_C_GRX_N14
<10> PCIE_GTX_C_MRX_P15
<10> PCIE_GTX_C_MRX_N15
PM@C330 1
PM@C330
PM@C331
PM@
C331 1
<10> PCIE_MTX_C_GRX_P15
<10> PCIE_MTX_C_GRX_N15
4
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2
2
1
1 C254
PM@
4.7U_0603_6.3V6M
C253
PM@
1U_0603_10V4Z
1
C245
PM@
0.47U_0402_6.3V6K
2
2
1 C255
PM@
0.47U_0402_6.3V6K
1
2
+1.1VS
1
0.47U_0402_6.3V6K
C258
C249
PM@
PM@
2
2
0.1U_0402_16V4Z
C262
PM@
1
2
1
1
C259
PM@
1U_0603_10V4Z
1.920 Amps
1
C263
PM@
2
4.7U_0603_6.3V6M
C264
PM@
2 10U_0805_6.3V6M
1U_0603_10V4Z
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J10
J12
J13
J9
L9
M11
M17
M9
N11
N12
N13
N14
N15
N16
N17
N19
N9
P11
P12
P13
P14
P15
P16
P17
R11
R12
R13
R14
R15
R16
R17
R9
T11
T17
T9
U19
U9
W10
W12
W13
W18
W19
W9
VDD_SENSE
GND_SENSE
W15
W16
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
A12
B12
C12
D12
E12
F12
PEX_PLLVDD
AF9
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C273
PM@
2
2
1
C274
PM@
2
0.1U_0402_16V4Z
1
C275
PM@
0.1U_0402_16V4Z
2
+VGA_CORE
1
C276
PM@
2
1
C277
PM@
2
0.1U_0402_16V4Z
C278
PM@
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
2
1
C285
PM@
2
22U_0805_6.3V6M
1
1
C286
PM@
C287
PM@
2
22U_0805_6.3V6M
2
C288
PM@
22u X 3
1
0.47u X 7
C289
PM@
0.1u X 7
2
22U_0805_6.3V6M
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
1
2
0.47U_0402_6.3V6K
1
C295
PM@
2
PM@
1
R392
0.47U_0402_6.3V6K
1
C296
PM@
2
1
C297
PM@
0.47U_0402_6.3V6K
2
1
C298
PM@
2
1
C299
PM@
2
0.47U_0402_6.3V6K
0_0402_5%
2
C300
PM@
0.47U_0402_6.3V6K
+NVVDD_SENSE
3
+3VS
110 mA
VDD33
1
2
C1476
PM@
1
2
C314
PM@
1
2
C311
PM@
120mA
PEX_PLLDVDD
1
2
C327
PM@
@ R208
2
2
2
R195
PM@
150_0402_1%
R210
1
TV-OUT
150_0402_1%
NB9M-GS_BGA_533P
COMMON
150_0402_1%
U17E
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
<23> <10> PCIE_MTX_C_GRX_P11
<23> <10> PCIE_MTX_C_GRX_N11
<10> PCIE_GTX_C_MRX_P13
<10> PCIE_GTX_C_MRX_N13
PM@
PM@C315 1
PM@C315
PM@C316
PM@
C316 1
1 C252
PM@
0.1U_0402_16V4Z
1
2
PEX_TX0
PEX_TX0
PM@C281 1
PM@C281
PM@C282
PM@
C282 1
AB13
AB16
AB17
AB7
AB8
AB9
AC13
AC7
AD6
AE6
AF6
AG6
PEX_REFCLK
PEX_REFCLK
PEX_TXP0 AD10
PEX_TXN0 AD11
<10> PCIE_MTX_C_GRX_P2
<10> PCIE_MTX_C_GRX_N2
2
PEX_RST
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
<10> PCIE_MTX_C_GRX_P1
<10> PCIE_MTX_C_GRX_N1
<10> PCIE_GTX_C_MRX_P2
<10> PCIE_GTX_C_MRX_N2
RFU
PM@C265 1
PM@C265
PM@C268
PM@
C268 1
<10> PCIE_MTX_C_GRX_P0
<10> PCIE_MTX_C_GRX_N0
<10> PCIE_GTX_C_MRX_P1
<10> PCIE_GTX_C_MRX_N1
1
PM@
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
DATA
1
C244
PM@
0.1U_0402_16V4Z
2
AC9
AD7
AD8
AE7
AF7
AG7
1U_0603_10V4Z
IFPA_TXD2
IFPA_TXD2
600 mA
NB9M-GS_BGA_533P
COMMON
A
1
C248
1 PM@
470P_0402_50V7K
2
4.7U_0603_6.3V6M
IFPAB_PLLVDD
IFPAB_RSET
+1.1VS
U17A
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
RFU
PEX_TERMP
AF10
AE10
1
2
1
2
C325
PM@
1
2
C446
PM@
1U_0402_6.3V6K
2
C246
PM@
4.7U_0603_6.3V6M
AD5
AB6
VGA_TXOUT1- <22>
VGA_TXOUT1+ <22>
0.1U_0402_16V4Z
C257
PM@
1 C247
2
PM@
4700P_0402_25V7K
VGA_TXOUT0- <22>
VGA_TXOUT0+ <22>
AA4
AA5
0.01U_0402_25V7K
2
1
2
1
V4
V5
IFPA_TXD1
IFPA_TXD1
0.1U_0402_16V4Z
IFPAB_PLLVDD
IFPAB_RSET
2
1
L7 PM@
BLM18PG181SN1D_0603
1
IFPA_TXD0
IFPA_TXD0
4.7U_0603_6.3V6M
100mA
0.1U_0402_16V4Z
+VDD_MEM18
6/13 IFPAB
1
2
1
L10 PM@
BLM18PG181SN1D_0603
+1.1VS
C447
PM@
200_0402_1%
2
AG9
AG10
1
2
R209 PM@
2.49K_0402_1%
4
PM@
#SI Remove TV out
DACB_CSYNC D6
DAC B
DACB_RED F7
DACB_GREEN E7
DACB_BLUE E6
#SI Remove TV out
Compal Secret Data
Security Classification
Classification
Issued Date
PM@
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Compal Electronics, Inc.
Size
Document Number
Custom kAL90KALH0
Date:
PEG & LVDS & DAC
Thursday, November 20, 2008
E
Sheet
17
of
Rev
0.2
52
4
3
2
1
2
AC6
J4 HDMI_C_CLKH4 HDMI_C_CLK+
PM@
PM@
C1474 1
C1475 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
VGA_HDMI_TXCVGA_HDMI_TXC+
TXD1
TXD1
TXD2
TXD2
IFPC_L2
IFPC_L2
K4 HDMI_C_TX0L4 HDMI_C_TX0+
PM@
PM@
C1468 1
C1469 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
VGA_HDMI_TXD0VGA_HDMI_TXD0+
<24>
<24>
TXD2
TXD2
TXD1
TXD1
IFPC_L1
IFPC_L1
M4 HDMI_C_TX1M5 HDMI_C_TX1+
PM@
PM@
C1470 1
C1471 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
VGA_HDMI_TXD1VGA_HDMI_TXD1+
<24>
<24>
TXC
TXC
TXC
TXC
IFPC_L0
IFPC_L0
N4 HDMI_C_TX2P4 HDMI_C_TX2+
PM@
PM@
C1472 1
C1473 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
VGA_HDMI_TXD2VGA_HDMI_TXD2+
<24>
<24>
1
1K_0402_1%
C341
470P_0402_50V7K
PM@ R212
2
2
IFPC_IOVDD
G5
G4
Must near connector for eye pattern
<24>
<24>
D
PM@
U17G
2
VGA_THERMDC
3
THERM#_VGA
4
2200P_0402_50V7K
2
10K_0402_5%
R224
@
+3VS
R222
1
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
8
H6
7
VGA_SM_DA
6
THERM_SCI#
THERM_SCI#
5
@
IFPE_IOVDD
ADM1032ARMZ REEL_MSOP8
@
2
DVI
DP
IFPE_AUX
IFPE_AUX
D4
D3
TXD0
TXD0
TXD0
TXD0
IFPE_L3
IFPE_L3
B4
B3
TXD1
TXD1
TXD2
TXD2
IFPE_L2
IFPE_L2
C4
C3
TXD2
TXD2
TXD1
TXD1
IFPE_L1
IFPE_L1
D5
E4
TXC
TXC
TXC
TXC
IFPE_L0
IFPE_L0
F4
F5
1K_0402_5%
R234
1
VGA_SM_CLK
1K_0402_5%
VGA_THERMDA
VDD
PM@
2
1
10K_0402_5%
R223
PM@
AT24C16BN
PM@
C350 @
2
HDCP_SCL
1
HDCP_WP
1
E
2
1
U6
1
MXM
IFPE_PLLVDD
IFPE_RSET
R219
PM@
10K_0402_5%
1
10K_0402_5%
R221
@
HDCP_WP
HDCP_SCL
HDCP_SDA
PM@
2
Closed to VGA
N6
M6
2
#SI2 change to pull hi
C
PM@
10K_0402_5%
2
U7
C348
@
0.1U_0402_16V4Z
2
C351
PM@1
8
7
6
5
IFPC_L3
IFPC_L3
8/13 IFPE
+3VS
0.1U_0402_16V4Z
2
VCC
WP
SCL
SDA
1
VGA Thermal Sensor
ADM1032ARMZ
2
+3VS
HDCP
ROM
A0
A1
A2
GND
TXD0
TXD0
NB9M-GS_BGA_533P
COMMON
+3VS
1
2
3
4
2
R236
1
PM@
C
1
J6
10K_0402_5%
R218
PM@
SPDIF_IN
1
2
R220
PM@
2
TXD0
TXD0
1
RFU_GND
2
@
2
0.01U_0402_25V7K
1
DP
AD25
RFU
RFU
36K_0402_5%
C349
1
TESTMODE
C15
D15
IFPC_IOVDD
1
10K_0402_5%
R217
@
C
385 mA
1
DVI
IFPC_AUX
IFPC_AUX
C347
#PV2 change R213,R215 form 10K to 2.2K.
L13 PM@
PM@
C340
PM@
BLM18PG181SN1D_0603
2
2
MXM
IFPC_PLLVDD
IFPC_RSET
PM@
+1.1VS
+3VS
4700P_0402_25V7K
C338
PM@
C337
+3VS
1
470P_0402_50V7K
F6
2
C346
RFU
1
PM@
J5
2
4700P_0402_25V7K
N5
RFU
1
C343
BUFRST
SPDIF
2
PM@
F9
1
1
SPDIF
<38> SPDIF_HDMI
STRAP_REF_MIOB
A10 ROM_SI
C10 ROM_SO
C9 ROM_SCLK
R213 2.2K_0402_5%
PM@ 1
2
HDCP_SCL
A3
HDCP_SDA
A4
2
1
2.2K_0402_5% R215
PM@
4.7U_0603_6.3V6M
STRAP_REF_3V3
1
2
F10
40.2K_0402_1%
R216 PM@
+3VS
I2CH_SCL
I2CH_SDA
B10 ROM_CS#
IFPC_PLLVDD P6
IFPC_RSET R5
C342
R214 PM@
40.2K_0402_1%
1
2
F11
D
ROM_SI
ROM_SO
ROM_SCLK
160 mA
1
PM@
STRAP0
STRAP1
STRAP2
PM@
ROM_CS
C7
B9
A9
BLM18PG181SN1D_0603
L12 PM@
1U_0402_6.3V6K
2
2
11/13 MISC
STRAP0
STRAP1
STRAP2
7/13 IFPC
+VDD_MEM18
R211 @
10K_0402_5%
NB9M-GS_BGA_533P
COMMON
NB9M-GS_BGA_533P
COMMON
4.7U_0603_6.3V6M
1
U17L
1
U17H
#SI Change to +VDDMEM18
+3VS
1U_0402_6.3V6K
5
+3VS
U17K
NB9M-GS_BGA_533P
COMMON
36 mA
BLM18PG181SN1D_0603
2
1
PM@ L14
2
1
C353
PM@
2
1
2
C354
PM@
0.1U_0402_16V4Z
1
C352
PM@
0.1U_0402_16V4Z
2
1
2
C355
PM@
K5
PLLVDD
K6
VID_PLLVDD
L6
SP_PLLVDD
D11
<4,35,36>
XTAL_OUTBUFF
I/O
ACTIVE
GPIO0
IN
N/A
Primary DVI Hot-plug
GPIO1
IN
N/A
2nd DVI Hot-plug
GPIO2
OUT
H
Panel Back-Light PWM
R229
GPIO3
10K_0402_5%
PM@
OUT
H
Panel Power Enable
GPIO4
OUT
H
Panel Back-Light Enable
GPIO5
OUT
N/A
NVVDD VID0
GPIO6
OUT
N/A
NVVDD VID1
GPIO7
OUT
N/A
FBVDD VID0
GPIO8
IN
L
Thermal Alert
GPIO9
OUT
L
FAN PWM
GPIO10
OUT
N/A
FBVref Select
GPIO11
OUT
N/A
SLI SYNCO
E9
XTALIN D10
1
XTAL_IN
XTAL_OUT
E10XTALOUT
1
PM@
C356
18P_0402_50V8J
2 @
C357 @
18P_0402_50V8J
2
R228
10K_0402_5%
PM@
GPIO
XTALIN
1
27M_CLK
<4,35,36>
Straps
MULTI LEVEL STRAPS
9/13 I2C_GPIO_THERM_JTAG
@
T6
@
T7
@
T8
@
T9
@
T10
THERMDP
R225
1
1
R226
@
@
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST
T1
T2
PS Control or HDMI_CEC
0
0
OUT
H
PS Control
0
1
1.17V
1
0
unused
I2CA_SCL
I2CA_SDA
R1
T3
VGA_DDC_CLK
VGA_DDC_DATA
I2CB_SCL
I2CB_SDA
R2
R3
I2CB_SCL
I2CB_SDA
PAD
PAD
I2CC_SCL
I2CC_SDA
A2
B1
DDC2_CLK
DDC2_DATA
I2CC_SCL <22>
I2CC_SDA <22>
I2CD_SCL
I2CD_SDA
N2
N3
I2CE_SCL
I2CE_SDA
Y6
W6
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
I2CS_SCL
I2CS_SDA
+VGA_CORE
GPIO14
VGA_HDMI_TXCVGA_HDMI_TXC+
VGA_HDMI_TXD0VGA_HDMI_TXD0+
VGA_HDMI_TXD1VGA_HDMI_TXD1+
VGA_HDMI_TXD2VGA_HDMI_TXD2+
AF3
AF4
AG4
AE4
AG3
VGA_SM_CLK
VGA_SM_DA
AC Detect
0.9V
VGA_DDC_CLK
VGA_DDC_DATA
LVDS
VGA_HDMI_SCLK
VGA_HDMI_SDATA
PAD
PAD
I2CE_SCL
I2CE_SDA
N1
G1
C1
M2 ENVDD
M3
K3
K2
J2
C2 THERMAL ALERT
M1 SINN_GPIO9
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2
CRT
<23>
<23>
T36 @
T37 @
<24>
<24>
HDMI
B
T43 @
T44 @
HDMI_DET
<24>
ENVDD
<22>
ENBKL
<10,35>
GPU_VID0 <50>
GPU_VID1 <50>
1 PM@
1 PM@
2 R396
2 R395
0_0402_5% THERM#_VGA
0_0402_5% THERM_SCI#
#SI Add GPU_VID1
PM@
U17I
NB9M-GS_BGA_533P
COMMON
HD AUDIO
499_0402_1%
PM@ R967
2
1
PM@ 2
1
R247 10K_0402_5%
499_0402_1%
PM@ R966
2
1
10/13 HDAUDIO
1 PM@
2
45.3K_0402_1%
@ 2
1
5.1K_0402_5%
499_0402_1%
PM@ R965
2
1
@
1
2
R246 5.1K_0402_5%
D9
L
A
R245
VGA_THERMDA
N/A
499_0402_1%
PM@ R964
2
1
R248
20 Kohms
10 Kohms
45 Kohms
30 Kohms
10 Kohms
5.1 Kohms
THERMDN
OUT
499_0402_1%
PM@ R963
2
1
R243
Locating
16MX16 Hynix
16MX16 Samsung
32MX16 Hynix
32MX16 Samsung
64MX16 Samsung
64MX16 Hynix
0_0402_5%
DDC2_CLK
2
DDC2_DATA
2
0_0402_5%
GPU_VID0
D8
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST
PAD
PAD
PAD
PAD
PAD
GPU_VID1
VGA_THERMDC
IN
499_0402_1%
PM@ R962
2
1
1 PM@
2
10K_0402_1%
Resistor Value
2 R231
2 R232
U17M
NB9M-GS_BGA_533P
COMMON
GPIO13
499_0402_1%
PM@ R961
2
1
@
1
2
5.1K_0402_5%
R244
DDR2
2K_0402_5% 1 PM@
DDC2_CLK
DDC2_DATA 2K_0402_5% 1 PM@
VGA_SM_CLK
GPIO12
499_0402_1%
PM@ R960
2
1
R242
+3VS
VGA_SM_DA
R239 0_0402_5%
1
2
PM@
EC_SMB_CK2
2
R235
10K_0402_5%
@
STRAP0
STRAP1
STRAP2
ROM_SI
ROM_SO
ROM_SCLK
R238 0_0402_5%
1
2
PM@
EC_SMB_DA2
2
B
<16>
2 R227
2 R230
USAGE
1
XTAL_SSIN
1
<16> 27M_SSC
2
2
C497
4.7U_0603_6.3V6M
PM@
0.1U_0402_16V4Z
C1528
PM@
22U_0805_6.3V6M
1
1
12/13 XTAL_PLL
GPU_PLLVDD
1U_0402_6.3V6K
+1.1VS
2K_0402_5% 1 PM@
2K_0402_5% 1 PM@
VGA_DDC_CLK
VGA_DDC_DATA
HDA_BCLK
A7
HDA_SYNC
HDA_SDI
HDA_SDO
HDA_RST
B7
A6
B6
C6
HDA_BITCLK_VGA
R399
HDA_SDIN2_R
33_0402_5%
1 PM@
2
<26>
A
HDA_SYNC_VGA
<26>
HDA_SDIN3 <26>
HDA_SDOUT_VGA <26>
HDA_RST_VGA# <26>
9/21 R329 near GPU
@
1
2
R250 5.1K_0402_5%
R252
1 PM@
2
15K_0402_5%
R249
@
1
2
5.1K_0402_5%
#SI2 add 2N7002 to GND
PM@ 2
1
R251 5.1K_0402_5%
R253
9/21 R237, R238, R240, R241 near ICH
1
1 PM512M@
2
5.1K_0402_5%
+3VS
@ 2
1
5.1K_0402_5%
D
PM@
Q74
2N7002_SOT23-3
2
G
3
R248
Compal Secret Data
Security Classification
S
Issued Date
1 R237
2
@
10K_0402_5%
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
Straps & HDMI
Size
Document Number
Custom kAL90KALH0
Date:
Thursday, November 20, 2008
1
Rev
0.2
Sheet
18
of
52
A
VRAM Interface
PJP1
1
+VDD_MEM18
2
+1.8VS
PAD-OPEN 3x3m
#SI2 change to short pad
@
1
<20> DQMA[3..0]
<21> DQMA[7..4]
<20> QSA[3..0]
<21> QSA[7..4]
<20> QSA#[3..0]
<21> QSA#[7..4]
CMDA[30..0]
C368
PM@
4.7U_0603_6.3V6M
C365
PM@
2
13/13 GND_NC
0.1U_0402_16V4Z
1
C375
2
PM@
2
1
1
2
0.022U_0402_16V7K
C367
PM@
C374
1
4.7U_0603_6.3V6M
C364
PM@
2
0.1U_0402_16V4Z
1
PM@
2
2
1U_0402_6.3V6K
C360
PM@
C373
1
0.1U_0402_16V4Z
C363
PM@
2
0.022U_0402_16V7K
1
1
<20,21>
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
9/18 add R for nvidia
CLKA0
CLKA0#
CLKA1
CLKA1#
R254
PM@ 2
1
2
PM@
2
1
1U_0402_6.3V6K
1
C359
M22
PM@
FBA_DEBUG
1
0.022U_0402_16V7K
@ 2 R256
C362
1
PM@
B16
2
4700P_0402_25V7K
FB_CAL_TERM_GND
1
C372
PM@ 2 R255
2
PM@
1
2
1
0.1U_0402_16V4Z
A15
C366
B15
FB_CAL_PU_GND
PM@
FB_CAL_PD_VDDQ
1
0.022U_0402_16V7K
F24
F23
N24
N23
C369
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
PM@
F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
J22
L22
2
4700P_0402_25V7K
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
RFU
RFU
1
C371
2
2
PM@
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
1
A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22
1
4700P_0402_25V7K
B24
D25
E18
A18
R22
R27
Y24
AA27
C358
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
PM@
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
2
0.022U_0402_16V7K
A24
C25
E19
A19
T22
T27
AA24
AA26
C361
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
1
PM@
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
2
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
4700P_0402_25V7K
D23
C26
D19
B19
T24
T26
AA23
AB27
1
C370
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
NB9M-GS_BGA_533P
COMMON
PM@
D21
C22
B22
A22
C24
B25
A25
A26
D22
E22
E24
D24
D26
D27
C27
B27
D16
E16
D17
F18
D20
F20
E21
F21
C16
B18
C18
D18
C19
C21
B21
A21
P22
P24
R23
R24
T23
U24
V23
V24
N25
N26
R25
R26
T25
V26
V25
V27
V22
W22
W23
W24
AA22
AB23
AB24
AC24
W25
W26
W27
AA25
AB25
AB26
AD26
AD27
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
+VDD_MEM18
4700P_0402_25V7K
MDA[63..48]
2/13 FRAME_BUFFER
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
R257
@
2
CMDA12
R1131 10K_0402_5%
1
2
PM@
CMDA11
R1132 10K_0402_5%
1
2
PM@
<20>
<20>
<21>
<21>
30_0402_1%
+VDD_MEM18
30_0402_1%
40.2_0402_1%
AC11
AC14
AC17
AC2
AC20
AC23
AC26
AC5
AC8
AF11
AF14
AF17
AF2
AF20
AF23
AF26
AF5
AF8
B11
B14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B17
B2
B20
B23
B26
B5
B8
E11
E14
E17
E2
E20
E23
E26
E5
E8
H2
H5
J11
J14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J17
K19
K9
L11
L12
L13
L14
L15
L16
L17
L2
L5
M12
M13
M14
M15
M16
P19
P2
P23
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P26
P5
P9
T12
T13
T14
T15
T16
U11
U12
U13
U14
U15
U16
U17
U2
U23
U26
U5
V19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V9
W11
W14
W17
Y2
Y23
Y26
Y5
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
AA6
AC19
E15
T6
1
+VDD_MEM18
10K_0402_5%
PM@
+VDD_MEM18
R19
T19
FB_PLLAVDD
2
2
R259 @
1K_0402_1%
Rb
2
C378
@
2
2
2
1
L15 PM@
BLM18PG181SN1D_0603
+1.1VS
C394
C379
1
PM@
2
PM@
FB_VREF
1
A16
1
1
4.7U_0603_6.3V6M
Rt
1
PM@ C377
0.01U_0402_25V7K
@
2
R258
1K_0402_1%
1
C376
1
FB_PLLAVDD
FB_DLLAVDD
PM@
<21> MDA[63..48]
U17J
NB9M-GS_BGA_533P
COMMON
MDA[47..32]
1U_0402_6.3V6K
<21> MDA[47..32]
U17B
MDA[31..16]
0.1U_0402_16V4Z
<20> MDA[31..16]
MDA[15..0]
0.1U_0402_16V4Z
<20> MDA[15..0]
PM@
Compal Secret Data
Security Classification
Issued Date
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Compal Electronics, Inc.
Size
Document Number
Custom kAL90KALH0
Date:
VRAM / GND
Thursday, November 20, 2008
Sheet
Rev
0.2
19
of
52
5
4
3
2
1
DATA Bus
VRAM DDR2 chips (256MB & 512MB)
Address
32Mx16 DDR2 400MHz *4==>256MB
64Mx16 DDR2 400MHz*4==>512MB
D
CMD0
A3
CMD1
A0
CMD2
A2
CMD3
A1
A0
A1
CMD4
A3
QSA[7..0]
CMD5
A4
QSA#[7..0]
CMD6
A5
DQMA[7..0]
CMD7
<19,21> QSA[7..0]
<19,21> QSA#[7..0]
<19,21> DQMA[7..0]
32..63
0..31
MDA[63..0]
CMD8
CS#
CS#
CMDA[30..0]
CMD9
WE#
WE#
CMD10
BA0
BA0
CMD11
CKE
CKE
CMD12
ODT
ODT
<19,21> MDA[63..0]
<19,21> CMDA[30..0]
D
CMD13
BA0
BA1
CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA22
CMDA24
CMDA0
CMDA2
CMDA3
CMDA1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
K8
J8
CK
CK
CLKA0#
CLKA0
CMDA11
K2
CMDA8
L8
CMDA9
K3
CMDA15
K7
RAS
L7
CAS
CMDA25
DQMA2
DQMA0
F3
B3
CMDA12
K9
QSA2
QSA#2
+VDD_MEM18
CKE
F7
E8
WE
1
2
R260
1K_0402_1%
R262
1K_0402_1%
VREF
A2
E2
L1
R3
R7
R8
NC
NC
NC
NC
NC
NC
2
0.1U_0402_16V4Z
PM@
A1
E1
J9
M9
R1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
UDQS
UDQS
VSS
VSS
VSS
VSS
VSS
BA0
BA1
CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA22
CMDA24
CMDA0
CMDA2
CMDA3
CMDA1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
K8
J8
CK
CK
K2
0.1U_0402_16V4Z
1
J1
J7
1
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
2
CKE
CMDA8
L8
CMDA9
K3
CMDA15
K7
RAS
L7
CAS
CMDA25
DQMA1
DQMA3
F3
B3
CMDA12
K9
CS
WE
VDD
VDD
VDD
VDD
VDD
A1
E1
J9
M9
R1
+VDD_MEM18
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MEM_VREF0
J2
VREF
A2
E2
L1
R3
R7
R8
NC
NC
NC
NC
NC
NC
UDQS
UDQS
VSS
VSS
VSS
VSS
VSS
CMD16
A11
A11
CMD17
A10
A10
CMD18
BA1
BA1
CMD19
A8
A8
CMD20
A9
A9
CMD21
A6
A6
CMD22
A5
CMD23
A7
CMD24
A4
CMD25
CAS#
CAS#
CMD26
A13
A13
CMD27
BA2
BA2
C
A7
CMD28
CMD29
CMD30
0.1U_0402_16V4Z
1
J1
J7
1
C381
LDQS
LDQS
B7
A8
CMDA27
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
MDA27
MDA28
MDA24
MDA31
MDA30
MDA25
MDA29
MDA26
MDA15
MDA9
MDA12
MDA8
MDA11
MDA13
MDA10
MDA14
2
F7
E8
QSA3
QSA#3
A3
E3
J3
N1
P9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VSSDL
PM@
#PV reserve CMD27 to suport 64M x 16
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
ODT
C384
4.7U_0603_6.3V6M
QSA1
QSA#1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
LDM
UDM
PM@
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
C382
4.7U_0603_6.3V6M
2
B
PM@
PM@
<19>
CLKA0
CLKA0
R261
475_0402_1%
A3
E3
J3
N1
P9
<19>
CLKA0#
CLKA0#
PM@
(SSTL-1.8) VREF = .5*VDDQ
PM@
HY5PS1G1631CFR-25 FBGA 84P
HY5PS1G1631CFR-25 FBGA 84P
PM512M@
PM512M@
DDR BGA MEMORY
DDR2 BGA MEMORY
+VDD_MEM18
+VDD_MEM18
0.01U_0402_16V7K
1
A
L2
L3
CMDA11
2
J2
2
VDD
VDD
VDD
VDD
VDD
CMDA10
CMDA18
CLKA0#
CLKA0
+VDD_MEM18
C383
LDQS
LDQS
MEM_VREF0
CMDA27
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
MDA7
MDA0
MDA5
MDA2
MDA3
MDA4
MDA1
MDA6
MDA23
MDA18
MDA20
MDA16
MDA17
MDA21
MDA19
MDA22
ODT
B7
A8
C385
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VSSDL
QSA0
QSA#0
PM@
1
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
LDM
UDM
1
B
CS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A12
RAS#
1
C
U9
L2
L3
A12
RAS#
2
U8
CMDA10
CMDA18
CMD14
CMD15
C395
1000P_0402_50V7K
1
C396
2
1
C397
2
1
C398
2
PM@ 0.01U_0402_16V7K
PM@
4.7U_0603_6.3V6M
1
C399
2
PM@
1
C400
2
0.1U_0402_16V4Z
PM@
0.1U_0402_16V4Z
1
C401
2
C402
2
2
0.1U_0402_16V4Z
PM@
PM@
0.01U_0402_16V7K
1
0.01U_0402_16V7K
PM@
1
C386
1000P_0402_50V7K
1
C387
1
C388
4.7U_0603_6.3V6M
1
1
C389
C390
0.01U_0402_16V7K
1
C391
1
1
C392
C393
A
2
2
2
PM@ 0.01U_0402_16V7K
PM@
PM@
2
0.1U_0402_16V4Z
PM@
PM@
2
2
2
0.1U_0402_16V4Z
PM@
0.01U_0402_16V7K
PM@
PM@
PM@
Compal Secret Data
Security Classification
Issued Date
2
2008/11/10
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
VRAM 1
Size
Document Number
Rev
0.1
KAL90
Date:
Thursday, November 20, 2008
Sheet
1
7
of
16
5
4
3
2
1
DATA Bus
VRAM DDR2 chips (256MB & 512MB)
32Mx16 DDR2 400MHz *4==>256MB
64Mx16 DDR2 400MHz*4==>512MB
D
<19,20> CMDA[30..0]
<19,20> QSA#[7..0]
<19,20> QSA[7..0]
<19,20> MDA[63..0]
CMD0
A3
CMD1
A0
CMD2
A2
CMD3
A1
32..63
A0
A1
CMD4
A3
CMD5
A4
CMDA[30..0]
CMD6
A5
QSA#[7..0]
CMD7
QSA[7..0]
CMD8
CS#
CS#
MDA[63..0]
CMD9
WE#
WE#
CMD10
BA0
BA0
CMD11
CKE
CKE
CMD12
ODT
ODT
DQMA[7..0]
<19,20> DQMA[7..0]
0..31
Address
D
CMD13
BA0
BA1
CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA6
CMDA5
CMDA4
CMDA13
CMDA3
CMDA1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CLKA1#
CLKA1
K8
J8
CMDA11
K2
CMDA8
L8
CMDA9
K3
WE
CMDA15
K7
RAS
CMDA25
B
CS
CMDA12
LDM
UDM
K9
0.1U_0402_16V4Z
1
J1
J7
VDDL
VSSDL
ODT
+VDD_MEM18
QSA5
QSA#5
2
F7
E8
LDQS
LDQS
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC
NC
NC
NC
NC
NC
2
QSA4
QSA#4
1
MEM_VREF1
R268
1K_0402_1%
PM@
1
CMDA27
2
C407
2
0.1U_0402_16V4Z
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
R266
1K_0402_1%
1
C405
L2
L3
BA0
BA1
CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA6
CMDA5
CMDA4
CMDA13
CMDA3
CMDA1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
K8
J8
K2
CMDA8
L8
CMDA9
K3
WE
CMDA15
K7
RAS
CMDA25
L7
CAS
DQMA6
DQMA7
F3
B3
CMDA12
K9
2
QSA6
QSA#6
F7
E8
PM@
CS
LDM
UDM
#PV reserve CMD27 to suport 64M x 16
CMDA27
J1
J7
VDDL
VSSDL
0.1U_0402_16V4Z
1
J2
VREF
A2
E2
L1
R3
R7
R8
NC
NC
NC
NC
NC
NC
A10
CMD18
BA1
BA1
CMD19
A8
A8
CMD20
A9
A9
CMD21
A6
A6
CMD22
A5
CMD23
A7
CMD24
A4
CMD25
CAS#
CAS#
CMD26
A13
A13
CMD27
BA2
BA2
C
A7
CMD28
1
B
C403
UDQS
UDQS
A11
A10
CMD30
2
LDQS
LDQS
A11
CMD17
CMD29
ODT
B7
A8
MEM_VREF1
+VDD_MEM18
CMD16
A1
E1
J9
M9
R1
VDD
VDD
VDD
VDD
VDD
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
PM@
QSA7
QSA#7
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CKE
MDA59
MDA60
MDA58
MDA62
MDA63
MDA56
MDA61
MDA57
MDA51
MDA53
MDA48
MDA55
MDA52
MDA49
MDA54
MDA50
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CK
CK
CMDA11
C406
4.7U_0603_6.3V6M
A3
E3
J3
N1
P9
VSS
VSS
VSS
VSS
VSS
CMDA10
CMDA18
CLKA1#
CLKA1
+VDD_MEM18
A1
E1
J9
M9
R1
VDD
VDD
VDD
VDD
VDD
CAS
F3
B3
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CKE
L7
DQMA5
DQMA4
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CK
CK
MDA39
MDA32
MDA38
MDA34
MDA33
MDA37
MDA35
MDA36
MDA44
MDA43
MDA47
MDA40
MDA41
MDA46
MDA42
MDA45
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
A12
RAS#
C404
4.7U_0603_6.3V6M
2
PM@
PM@
<19>
R267
475_0402_1%
A3
E3
J3
N1
P9
VSS
VSS
VSS
VSS
VSS
CLKA1
CLKA1
1
C
U11
L2
L3
A12
RAS#
2
U10
CMDA10
CMDA18
CMD14
CMD15
<19>
CLKA1#
CLKA1#
PM@
PM@
HY5PS1G1631CFR-25 FBGA 84P
PM@
HY5PS1G1631CFR-25 FBGA 84P
PM512M@
0.01U_0402_16V7K
1
A
C417
1000P_0402_50V7K
1
C418
2
PM512M@
DDR2 BGA MEMORY
+VDD_MEM18
1
C419
4.7U_0603_6.3V6M
1
C420
2
0.01U_0402_16V7K
2
1
C421
2
0.1U_0402_16V4Z
DDR BGA MEMORY
+VDD_MEM18
0.1U_0402_16V4Z
1
C422
2
1
C423
0.01U_0402_16V7K
1
C424
2
2
0.1U_0402_16V4Z
2
0.01U_0402_16V7K
PM@
1
C408
1000P_0402_50V7K
1
C409
2
1
C410
2
C411
2
PM@ 0.01U_0402_16V7K
PM@
PM@
PM@
PM@
PM@
PM@
PM@
Security Classification
Issued Date
PM@
4.7U_0603_6.3V6M
1
1
C412
2
C413
2
0.1U_0402_16V4Z
PM@
2008/11/10
PM@
0.01U_0402_16V7K
1
1
1
C414
2
2
2
0.1U_0402_16V4Z
PM@
PM@
Compal Secret Data
A
C415
0.01U_0402_16V7K
PM@
PM@
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
VRAM 2
Size
Document Number
Rev
0.1
KAL90
Date:
Thursday, November 20, 2008
Sheet
1
8
of
16
5
4
3
2
1
+3VS
INVTPWM
1
C1904
3
1
5
2
G
1
3
S
2
6
INVTPWM
2
10K_0402_5%
Q111
2N7002_SOT23
+LCDVDD
4.7U_0805_10V4Z
2
@
2
For GMCH DPST
@
C1905
0.1U_0402_16V4Z
2
R1620
100K_0402_5%
1
W=60mils
1
1
1
+3VS
0.047U_0402_16V7K
2
2
2 0_0402_5%
R1617
D
3 2
4
G
PM@
4.7U_0805_10V4Z
Q110
AO3413_SOT23-3
2
D
1
1K_0402_5%
1
C1903
2N7002DW-T/R7_SOT363-6
R1619 1 GM@
ENVDD
C1902
S
2
R1616
Q109A
<18>
DPST_PWM <10>
@
Q109B
2 0_0402_5%
2
G
1
1
2
5
A
3
1
NC7SZ14P5X_NL_SC70-5
R1615
100K_0402_5%
2N7002DW-T/R7_SOT363-6
R1618 1
Y
W=60mils
R1614
300_0603_5%
<10> GMCH_ENVDD
4
1
U44
+3VS
+3V
NC
LCD POWER CIRCUIT
+LCDVDD
D
P
D
C
C
TXOUT0+
TXOUT0-
1
2
RP43
1 PM@
2
RP44
1 PM@
2
RP45
1 PM@
2
RP46
TXOUT1TXOUT1+
TXOUT2+
TXOUT2-
+3VS
1
TXCLKTXCLK+
R1621
2
BKOFF#
BKOFF#
1
L58 2
1
KC FBM-L11-201209-221LMAT_0805
C1908
VGA_TXOUT2+ <17>
VGA_TXOUT2- <17>
VGA_TXCLK- <17>
VGA_TXCLK+ <17>
B+
DAC_BRIG
1
4
3
VGA_TXOUT1- <17>
VGA_TXOUT1+ <17>
DISPOFF#
2
L59 2
1
KC FBM-L11-201209-221LMAT_0805
1
4
3
VGA_TXOUT0+ <17>
VGA_TXOUT0- <17>
CH751H-40PT_SOD323-2
+INVPWR_B+
W=40mils
4
3
VGA_TXOUT0+
VGA_TXOUT00_0404_4P2R_5%
VGA_TXOUT1VGA_TXOUT1+
0_0404_4P2R_5%
VGA_TXOUT2+
VGA_TXOUT20_0404_4P2R_5%
VGA_TXCLKVGA_TXCLK+
0_0404_4P2R_5%
PM@
4.7K_0402_5%
D34
<35>
4
3
INVTPWM
DISPOFF#
C1910
1
C1906
1
C1907
1
C1909
2
220P_0402_50V7K
2
220P_0402_50V7K
2
220P_0402_50V7K
680P_0402_50V7K 68P_0402_50V8J
2
2
I2CC_SCL
I2CC_SDA
1
2
RP47
TXOUT0+
TXOUT0-
2
1
RP48
2 GM@
1
RP49
2 GM@
1
RP50
2 GM@
1
RP51
4
3
GMCH_LCD_CLK
GMCH_LCD_DATA
0_0404_4P2R_5%
GMCH_LCD_CLK <10>
GMCH_LCD_DATA <10>
GM@
B
LCD/PANEL BD. Conn.
TXOUT1TXOUT1+
JLVDS1
+INVPWR_B+
+3VS
<18> I2CC_SCL
<18> I2CC_SDA
I2CC_SCL
I2CC_SDA
R1767
0_0402_5%
1
2
@
LED PANEL PIN1&34 SHORT
<27>
<27>
USB20_N6
USB20_P6
0_0402_5%
R1623 1
R1624 1
0_0402_5%
2 USB20_CMOS_N6
2 USB20_CMOS_P6
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
DAC_BRIG
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
DAC_BRIG <35>
INVTPWM R1622 1
DISPOFF#
2 0_0402_5%
TXOUT2+
TXOUT2-
INVT_PWM <35>
TXCLKTXCLK+
+LCDVDD
W=60mils
+3VS
TXOUT1TXOUT1+
1
TXOUT2+
TXOUT2-
2
1
C1911
0.1U_0402_16V4Z
2
0_0404_4P2R_5%
GMCH_TXOUT1GMCH_TXOUT1+
3
4
0_0404_4P2R_5%
GMCH_TXOUT2+
GMCH_TXOUT2-
3
4
0_0404_4P2R_5%
GMCH_TXCLKGMCH_TXCLK+
3
4
0_0404_4P2R_5%
GMCH_TXOUT0+ <10>
GMCH_TXOUT0- <10>
GMCH_TXOUT1- <10>
GMCH_TXOUT1+ <10>
GMCH_TXOUT2+ <10>
GMCH_TXOUT2- <10>
GMCH_TXCLK- <10>
GMCH_TXCLK+ <10>
GM@
+LCDVDD
TXOUT0TXOUT0+
B
GMCH_TXOUT0+
GMCH_TXOUT0-
3
4
1
C1912
10U_0805_10V4Z
2
C1913
0.1U_0402_16V4Z
TXCLKTXCLK+
+3VS
ACES_88242-4001
CONN@
A
A
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
LVDS Connector
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
22
of
52
A
B
C
CRT Connector
D35
D
D36
E
W=40mils
D37
+5VS
+R_CRT_VCC
+CRT_VCC
D38
1
1
1
DAN217_SC59 DAN217_SC59 DAN217_SC59
F1
2
1
1
1
2
1.1A_6VDC_FUSE
1
C1914
0.1U_0402_16V4Z
2
3
2
3
2
3
2
RB491D_SC59-3
W=40mils
+3VS
1
JCRT1
CRT_R
CRT_R_1
2
FCM2012C-800_0805
L61
1
CRT_G_1
2
FCM2012C-800_0805
L63
1
CRT_B_1
2
FCM2012C-800_0805
1
L60
CRT_G
L62
CRT_R_2
1
2
FCM2012C-800_0805
CRT_G_2
1
2
FCM2012C-800_0805
CRT_B_2
L65
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
150_0402_1%
1
C1915
C1916
1
2
2
10P_0402_50V8J
C1917
1
C1918
2
10P_0402_50V8J
1
1
C1919
C1920
1
1
2
2
2
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
150_0402_1%
GM@
10P_0402_50V8J
1
C1923
10P_0402_50V8J
2
GM@
GM@
C1924
change to 12pf for Discrete
change to 15pf for Discrete
+CRT_VCC
1
C1927
1
C1921
C1922
10P_0402_50V8J 10P_0402_50V8J
2
2
2
0.1U_0402_16V4Z
2
R1631
1
L4
2
10_0603_5%
1
L5
2
10_0603_5%
CRT_HSYNC_2
16
17
1
2
100P_0402_50V8J
1
10K_0402_5%
R1630
100K_0402_5%
1
P
2
A
1
C1928 2
68P_0402_50V8J 1
Y
CRT_HSYNC_1
4
3
G
CRT_HSYNC
OE#
5
2
U45
CONN@
DSUB_12
C1926
C1925
10P_0402_50V8J
10P_0402_50V8J
2
2
SUYIN_070546FR015S263ZR
CRT_DET# <27>
CRT_VSYNC_2
1
1
2
74AHCT1G125GW_SOT353-5
GND
GND
2
2
2
150_0402_1%
RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND
DSUB_15
2
1
R1626
R1627
2
2
FCM2012C-800_0805
1
R1625
L64
1
1
CRT_B
1
C1929
+CRT_VCC
68P_0402_50V8J
5
P
CRT_VSYNC
A
U46
Y
4
CRT_VSYNC_1
3
G
2
OE#
2
0.1U_0402_16V4Z
1
+CRT_VCC
1
C1930
74AHCT1G125GW_SOT353-5
+CRT_VCC
<10> GMCH_CRT_HSYNC
R1637 1 GM@
2
30.1_0402_1%
CRT_HSYNC
<10> GMCH_CRT_B
R1638 1 GM@
2
0_0402_5%
CRT_B
<10> GMCH_CRT_G
R1640 1 GM@
2
0_0402_5%
<10> GMCH_CRT_R
R1641 1 GM@
2
DSUB_12
2
G
3
Q112
2N7002_SOT23
DSUB_15
0_0402_5%
1
CRT_G
2
G
CRT_VSYNC
3
2
R1639
Q113
2N7002_SOT23
CRT_R
3
0_0402_5%
1
GMCH_CRT_DATA <10>
GM@
1
S
30.1_0402_1%
R1636
2
S
2
VGA_DDC_DATA <18>
PM@
D
R1635 1
2 R1634
0_0402_5%
1
D
<10> GMCH_CRT_VSYNC
2
3
pull-up 2.2k on GPU side
R1633
4.7K_0402_5%
2
R1632
4.7K_0402_5%
pull-up 10k on AMD M82M MXM side
+3VS
1
1
Place closed to chipset
1
GMCH_CRT_CLK <10>
0_0402_5%
1
GM@
GM@
2 R1642
0_0402_5%
VGA_DDC_CLK <18>
PM@
pull-up 2.2k on GPU side
<17> VGA_CRT_VSYNC
R1643 1
2
0_0402_5%
CRT_VSYNC
<17> VGA_CRT_HSYNC
R1644 1 PM@
2
0_0402_5%
CRT_HSYNC
<17> VGA_CRT_B
R1645 1 PM@
2
0_0402_5%
CRT_B
<17> VGA_CRT_G
R1646 1 PM@
2
0_0402_5%
CRT_G
<17> VGA_CRT_R
R1647 1 PM@
2
0_0402_5%
CRT_R
pull-up 10k on AMD M82M MXM side
PM@
4
4
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
CRT Connector
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
E
23
of
52
4
3
2
JHDMI1
+3VS
HDMI_HPD
1
3.3V Level
2
2 2.2K_0402_5%
2 2.2K_0402_5%
PM@
@ VGA_HDMI_SCLK
1
2
VGA_HDMI_SDATA 3
2 2.2K_0402_5%
2 2.2K_0402_5%
R1650
4.7K_0402_5%
HDMI_SDATA
HDMI_SCLK
HDMI_SCLK
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0-
HDMI_SDATA
1
HDMI_R_D0+
HDMI_R_D1-
D
S
R1652 1
R1653 1
+3VS
+5VS
Q115
BSH111_SOT23
HDMI_R_D1+
HDMI_R_D2-
Place closed to JHDMI1
PM@
@
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
Q114
BSH111_SOT23
G
VGA_HDMI_SDATA
<18> VGA_HDMI_SDATA
2
2
3
D
VGA_HDMI_SCLK
S
<18> VGA_HDMI_SCLK
R1649
4.7K_0402_5%
G
R1648 1
R1651 1
+3VS
+5VS
D
1
+HDMI_5V_OUT
DDC to HDMI CONN
1
5
HDMI_R_D2+
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
D
20
21
22
23
TYCO_1939864-1
MP:Update HDMI Hot Plug DET circuit.
CONN@
+HDMI_5V_OUT
HDMI_HPD
1
2
R104
0_0603_5%
A
G
2
U47
2
+3VS
R1655
100K_0402_5%
1
+HDMI_5V_OUT
@
C1932
D39
Y
4HDMI_DET
HDMI_DET
<18>
2
0.1U_0402_16V4Z
+5VS
F2
2
1
+HDMI_5V
RB491D_SC59-3
1
W=40mils
HDMI_CLK-
2
1.1A_6VDC_FUSE
C1933
0.1U_0402_16V4Z
3
C
2
1
R1654
2.2K_0402_5%
1
P
0.1U_0402_16V4Z
2
1
5
1
OE#
C1931
74AHCT1G125GW_SOT353-5
1
R1656
1
HDMI_R_CK-
2
0_0402_5%
PM@
L66
1
2
4
@
C
1
2
2
4
3
3
WCM-2012-900T_0805
HDMI_CLK+
1
R1657
2
0_0402_5%
PM@
HDMI_R_CK+
HDMI_TX0-
1
R1658
2
0_0402_5%
PM@
HDMI_R_D0-
L67
1
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
HDMI_CLK+
HDMI_CLKHDMI_TX0+
HDMI_TX0HDMI_TX1+
HDMI_TX1HDMI_TX2+
HDMI_TX2-
VGA_HDMI_TXC+
VGA_HDMI_TXCVGA_HDMI_TXD0+
VGA_HDMI_TXD0VGA_HDMI_TXD1+
VGA_HDMI_TXD1VGA_HDMI_TXD2+
VGA_HDMI_TXD2-
4
@
1
2
2
4
3
3
WCM-2012-900T_0805
HDMI_TX0+
1
R1659
2
0_0402_5%
PM@
HDMI_R_D0+
HDMI_TX1-
1
R1660
2
0_0402_5%
PM@
HDMI_R_D1-
B
B
L68
1
4
@
1
2
2
4
3
3
WCM-2012-900T_0805
HDMI_TX1+
1
R1661
2
0_0402_5%
PM@
HDMI_R_D1+
HDMI_TX2-
1
R1662
2
0_0402_5%
PM@
HDMI_R_D2-
L69
1
4
@
HDMI_TX2+
1
2
2
4
3
3
WCM-2012-900T_0805
1
R1663
HDMI_R_D2+
2
0_0402_5%
PM@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
HDMI Connector
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
24
of
52
5
4
3
2
1
DMI for ESI-compatible operation
+3VS
PCI_GNT#1
RP36
1
2
3
4
D
Low= DMI for ESI-compatible operation
High= Default* (Internal pull-up)
PCI_DEVSEL#
PCI_FRAME#
PCI_REQ#1
PCI_REQ#2
8
7
6
5
D
U23B
RP37 Structure>
<BOM
8
7
6
5
PCI_PLOCK#
PCI_IRDY#
PCI_PERR#
PCI_PIRQB#
8.2K_1206_8P4R_5%
<BOM Structure>
+3VS
RP38
1
2
3
4
PCI_PIRQG#
PCI_REQ#0
PCI_PIRQH#
PCI_PIRQE#
8
7
6
5
8.2K_1206_8P4R_5%
C
1
2
3
4
RP39
<BOM Structure>
8
7
6
5
PCI_PIRQF#
PCI_SERR#
PCI_PIRQA#
PCI_PIRQC#
8.2K_1206_8P4R_5%
1
2
3
4
RP40
<BOM Structure>
8
7
6
5
PCI_STOP#
PCI_PIRQD#
PCI_REQ#3
PCI_TRDY#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI
F1
G4
B6
A7
F13
F12
E6
F6
PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D8
B4
D6
A5
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
C14
D4
R2
PLT_RST#
CLK_PCI_ICH
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
@
PAD
T11
PAD
T12
PAD
PAD
PAD
PAD
T13
T14
T15
T16
@
@
@
@
@
PAD
T17
PCI_RST# <34>
@
Place closely pin B10
CLK_PCI_ICH
2
1
2
3
4
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
R1276
10_0402_5%
@
PLT_RST# <8,17,27,30,31,35>
CLK_PCI_ICH <16>
C
1
8.2K_1206_8P4R_5%
C1573
10P_0402_50V8J
@
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
8.2K_1206_8P4R_5%
<BOM Structure>
J5
E1
J6
C4
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
2
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
H4
K6
F2
G2
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
1
<BOM Structure>
A16 Swap Override Strap
Low= A16 swap override Enable
High= Default*
PCI_GNT#3
R1277
2 1K_0402_5%
1
B
PCI_GNT#3
B
@
Boot BIOS Loaction
0
1
P
Y
1
A
NC7SZ08P5X_NL_SC70-5
4
PLT_RST_BUF#
<33>
1
SPI_CS#1
U24
2 B
G
PCI_GNT#0
PLT_RST#
3
Boot BIOS Strap
5
+3VS
R1278
100K_0402_5%
SPI
1
0
PCI
1
1
LPC*
R1280
R1281
2 1K_0402_5%
1
@
1
2 1K_0402_5%
2
<BOM Structure>
<BOM Structure>
PCI_GNT#0
SPI_CS#1 <27>
@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
ICH9M(1/4)-PCI
Size
Document Number
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
25
of
52
4
3
NC
OUT
4
2
NC
IN
1
SM_INTRUDER#
C1575
18P_0402_50V8J
2
1
D
+RTCVCC
1
R1287
20K_0402_5%
1
+RTCVCC
close to RAM door
ICH_INTVRMEN
High = Internal VR Enable
2
close to RAM door
1
2
R1290
10K_0603_5%
C1577
@
1U_0603_10V6K
1
2
2
R1289
332K_0402_1%
1
R1288
20K_0402_5%
+RTCVCC
1
<37> HDA_BITCLK_MDC
SATA_LED#
R1300
1
<37> HDA_SYNC_MDC
C
R1301
1
<37> HDA_RST_MDC#
R1302
+3V
INTVRMEN
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
G13
D14
LAN_RXD0
LAN_RXD1
LAN_RXD2
D13
D12
E13
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
B10
GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
1
R1305
1
<37> HDA_SDOUT_MDC
2
R1306
HDA_SDOUT_ICH
33_0402_5%
2
10K_0402_5%
PROJECT_ID2
1
AG5
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
SATA_LED#
AG8
SATALED#
SATA for HDD
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA for ODD
<29> SATA_DTX_C_IRX_N1
<29> SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1
AH13
AJ13
AG14
AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
10K_0402_5%
2
2
1
2 @
1
56_0402_5%
56_0402_5%
@
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
@
+1.05VS
H_DPRSTP#
R1284
H_DPSLP#
R1286
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
K5
K4
L6
K2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
FWH4/LFRAME#
K3
LPC_FRAME#
LDRQ0#
LDRQ1#/GPIO23
J3
J1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
R1292 2
N7
AJ27
EC_GA20
H_A20M#
DPRSTP#
DPSLP#
AJ25
AE23
DPRSTP# R1293 1
DPSLP#
R1294 1
D
<35>
<35>
<35>
<35>
LPC_FRAME#
A20GATE
A20M#
<35>
1 10K_0402_5%
<35>
<4>
+3VS
EC_GA20
H_A20M#
FERR#
AJ26
FERR#
CPUPWRGD
AD22
H_PWRGOOD
IGNNE#
AF25
H_IGNNE#
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT#
H_INTR
EC_KBRST#
NMI
SMI#
AF23
AF24
H_NMI
H_SMI#
STPCLK#
AH27
H_STPCLK#
THRMTRIP#
AG26
THRMTRIP_ICH#
TP12
AG27
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AH9
AJ9
AE10
AF10
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
AH18
AJ18
AJ7
AH7
HDA_RST#
<29> SATA_DTX_C_IRX_N0
<29> SATA_DTX_C_IRX_P0
<42> SATA_LED#
R1307
AE7
AF4
AG4
AH3
AE5
<18> HDA_SDIN3
R1291
U23A
B22
A22
<38> HDA_SDIN0
<37> HDA_SDIN1
TPM Settings
1
Reset r1290 for power on then shut down issue
ICH_INTVRMEN
1
2
R1299
OPEN
RTCRST#
SRTCRST#
INTRUDER#
GLAN_COMP
2
24.9_0402_1%
HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
1
Keep ME RTC Registers
RTCX1
RTCX2
PROJECT_ID2
+1.5VS_PCIE_ICH
OPEN
A25
F20
C22
+3VS
10K_0402_5%
SHORT
Keep CMOS
C23
C24
1
2
R1291
10K_0603_5%
C1576
@
1U_0603_10V6K
1
2
R1297
Clear ME RTC Registers
ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#
ICH_RTCX2
2
SHORT
LPC
2
32.768KHZ_12.5P_MC-306
R1290
Clear CMOS
CPU
3
1M_0402_5%
CMOS Settings
RTC
X1
R1285
10M_0402_5%
2
1
R1283
ICH_RTCX1
LAN / GLAN
1
C1574
18P_0402_50V8J
2
1
IHDA
+RTCVCC
2
SATA
5
0_0402_5% H_DPRSTP#
0_0402_5% H_DPSLP#
2
2
1
R1295
H_FERR#
2
56_0402_5%
H_PWRGOOD
H_IGNNE#
H_INIT#
H_INTR
H_DPRSTP# <5,8,49>
H_DPSLP# <5>
H_FERR#
<5>
2
R1296
1
56_0402_5%
2
R1298
1
10K_0402_5%
<4>
+1.05VS
<4>
<4>
<4>
+3VS
EC_KBRST# <35>
H_NMI
H_SMI#
<4>
<4>
R258 need to place within 2" of ICH9M
R257 must be place within 2" of R258 w/o stub.
H_STPCLK# <4>
R1303 1
2 54.9_0402_1%
H_THERMTRIP#
2
R1304
SATA_DTX_C_IRX_N5
SATA_DTX_C_IRX_P5
SATA_ITX_DRX_N5
SATA_ITX_DRX_P5
H_THERMTRIP#
1
56_0402_5%
C
<4,8>
+1.05VS
SATA_DTX_C_IRX_N5 <34>
SATA_DTX_C_IRX_P5 <34>
CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS
CLK_PCIE_SATA#
CLK_PCIE_SATA
R1308 1
<16>
<16>
2 24.9_0402_1%
10mils width less than 500mils
ICH9-M ES_FCBGA676
1
R1309
1
R1310
1
R1311
1
R1312
<38> HDA_BITCLK_AUDIO
<38> HDA_SYNC_AUDIO
HDA for AUDIO
<38> HDA_RST_AUDIO#
<38> HDA_SDOUT_AUDIO
close ICH9
HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1
SATA_ITX_DRX_N5
SATA_ITX_DRX_P5
B
1
C1578
1
C1579
SATA_ITX_C_DRX_N0
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P0
2
0.01U_0402_16V7K
1
C1580
1
C1581
SATA_ITX_C_DRX_N1
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P1
2
0.01U_0402_16V7K
1
C1582
1
C1583
SATA_ITX_C_DRX_N5
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P5
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_N0
<29>
SATA_ITX_C_DRX_P0
<29>
SATA_ITX_C_DRX_N1
<29>
SATA_ITX_C_DRX_P1
<29>
SATA_ITX_C_DRX_N5
<34>
SATA_ITX_C_DRX_P5
<34>
+VCC_HDA_ICH
+1.05VS
R1319
1K_0402_5%
<18> HDA_SYNC_VGA
HDA for VGA
<18> HDA_RST_VGA#
HDA_SDOUT_ICH
@
<18> HDA_SDOUT_VGA
ICH_TP3
@
ICH_TP3
@
5
HDA_SDOUT
GPIO33
Description
0
0
RSVD
0
1
Enter XOR Chain
1
0
Normal Operation
1
1
Set PCIE port config bit 1
4
Q89
2SC2411K_SOT23
H_THERMTRIP#
@
Flash Descriptor Security Override Strap
XOR Chain Entrance Strap
R1323
1K_0402_5%
C
2
B
E
HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%
PM@
<27>
<44,45>
3
1
R1318
1 PM@
R1320
1 PM@
R1321
1 PM@
R1322
<18> HDA_BITCLK_VGA
A
MAINPWON
R1317
330_0402_5%
1
2
1
B
A
Low= Descriptor Security override
High= Default* (Internal pull-up)
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
ICH9M(2/4)-LAN,IDELPC,RTC
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
26
of
52
5
4
3
2
1
+3VS
Place closely pin B2
B
R3
PBTN_OUT#
D20
LAN_RST#
ICH_PWROK
B16
PM_SLP_M#
CL_RST0#
CL_RST1#
<33> PCIE_PTX_C_IRX_N2
<33> PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
<33> PCIE_ITX_C_PRX_P2
C1588 2
C1589 2
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2
L29
L28
M27
M26
J29
J28
K27
K26
<31> PCIE_PTX_C_IRX_N3
<31> PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
<31> PCIE_ITX_C_PRX_P3
C1590 2
C1591 2
1
1
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
0.1U_0402_16V7K
PCIE_ITX_PRX_P3
0.1U_0402_16V7K
<33> PCIE_PTX_C_IRX_N4
<33> PCIE_PTX_C_IRX_P4
PCIE_ITX_C_PRX_N4
<33> PCIE_ITX_C_PRX_P4
C1592 2
C1593 2
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4
G29
G28
H27
H26
1
1
PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
PCIE_ITX_PRX_N5
0.1U_0402_16V7K
PCIE_ITX_PRX_P5
0.1U_0402_16V7K
E29
E28
F27
F26
PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
PCIE_ITX_C_PRX_N5
PCIE_ITX_C_PRX_P5
C1594 2
C1595 2
ICH_SPI_CLK R1380 1
ICH_SPI_CS0# R1383 1
ICH_SPI_MOSI
ICH_SPI_MISO
R1384 1
R1385 1
D
2 15_0402_5%
2 15_0402_5%
@ <25>
@
2 15_0402_5%
2 15_0402_5%
@
@<34> USB_OC#0
<34> CP_PE#
<34> USB_OC#2
S
DMI Termination Voltage
ICH SPI ROM for HDCP
GPIO49
Low= Desktop used
High= Mobile* (Internal pull-up)
+3VS
ICH_SPI_CLK_R
ICH_SPI_CS0#_R
SPI_CS#1
<33> USB_OC#5
Low= Disable*
High= iTPM enable by MCH strap
CS#
WP#
HOLD#
GND
VCC
SCLK
SI
SO
8
6
5
2
ICH_SPI_CLK
ICH_SPI_MOSI
ICH_SPI_MISO
ICH_GPIO13
MX25L4005AMC-12G_SO8
If ICH SPI not used, Left NC
5
1
1
2
ICH_PWROK
1
R1341
2
10K_0402_5%
EC_PWROK
1
R1346
2
10K_0402_5%
PLT_RST# <8,17,25,30,31,35>
R1349 2
PAD
1 0_0402_5%
+3VS
@
T21
@
CL_CLK0 <8>
U26
ICH_PWROK
CL_DATA0 <8>
CL_VREF0_ICH
CL_VREF1_ICH
4
B
A
Y
NC7SZ08P5X_NL_SC70-5
2
EC_PWROK
1
VGATE
A16
C18
C11
C20
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
ICH_SPI_MOSI_R
ICH_SPI_MISO_R
USB_OC#0
CP_PE#
USB_OC#2
USB_OC#3
D23
D24
F23
SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6
D25
E23
SPI_MOSI
SPI_MISO
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
USBRBIAS
2
1
R1388
Within 500 mils
22.6_0402_1%
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47
AG2
AG1
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI
USB
2
R1406
CP_PE#
1
0_0402_5%
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBRBIAS
USBRBIAS#
PAD T24
C
@
PAD
T25
2
1
+3V
R1359
100K_0402_5%
2
1
ACIN
D12
CH751H-40PT_SOD323-2
R1357 2
1 0_0402_5%
Q90
MMBT3906_SOT23-3
@
SB_RSMRST#
1
3
<35,41,42,43,46>
R1364
10K_0402_5%
1
R1365
V27
V26
U29
U28
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0
Y27
Y26
W29
W28
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1
AB27
AB26
AA29
AA28
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2
AD27
AD26
AC29
AC28
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3
CLK_PCIE_ICH#
CLK_PCIE_ICH
AF29
AF28
DMI_IRCOMP
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0
<8>
<8>
<8>
<8>
2008/11/10
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1
<8>
<8>
<8>
<8>
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2
<8>
<8>
<8>
<8>
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3
<8>
<8>
<8>
<8>
4
3
6
2
D13B
4
3
5
BAV99DW-7_SOT363
R1373
2.2K_0402_5%
B
+3VS
CLK_PCIE_ICH# <16>
CLK_PCIE_ICH <16>
R1379 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
@
@
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
PAD T29
PAD T30
R1377
3.24K_0402_1%
Within 500 mils
+1.5VS_PCIE_ICH
<33>
<33>
<34>
<34>
<34>
<34>
USB20_N5 <33>
USB20_P5 <33>
USB20_N6 <22>
USB20_P6 <22>
USB20_N7 <33>
USB20_P7 <33>
USB20_N8 <33>
USB20_P8 <33>
USB20_N9 <34>
USB20_P9 <34>
USB20_N10 <34>
USB20_P10 <34>
CL_VREF0_ICH
USB CONN
New Card
C1596
ESATA/USB CONN
1
R1381
453_0402_1%
0.1U_0402_16V4Z
2
USB/B
+3V
CMOS Camera
Mini Card(WLAN)
R1386
3.24K_0402_1%
Mini Card(TV-Tuner)
Bluetooth
CL_VREF1_ICH
Finger Print
C1597
No Reboot Strap
1
R1387
453_0402_1%
A
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SPI ROM
Footprint 150mil
@
+3V
BAV99DW-7_SOT363
Compal Secret Data
Security Classification
2
4.7K_0402_5%
1
T26
T25
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
EC_RSMRST# <35>
D13A
Low= Default*
SB_SPKR High= "No Reboot"
ICH9-M ES_FCBGA676
Issued Date
EC_PWROK <35,37>
CL_RST#0 <8>
ICH_GPIO24
ICH_GPIO10
ICH_ACIN
ICH_GPIO9
U27
@
@
2
10K_0402_5%
No used Integrated LAN,
connecting LAN_RST# to GND
@
C29
C28
D27
D26
2
1
3
2
<23> CRT_DET#
Q91G
2N7002_SOT23
1
3
7
4
@
1
R1336
CK_PWRGD <16>
F22
C19
F21
D18
2
LAN_RST#
PBTN_OUT# <35>
F24
B19
C25
A19
C1584
10P_0402_50V8J
D
2
PM_DPRSLPVR <8,49>
2
0_0402_5%
CK_PWRGD
R6
@
1
N29
N28
P27
P26
1
CRT_DET
ICH_SPI_CS0#
ICH_SPI_WP#
2
ICH_SPI_HOLD#
2
2
100_0402_5%
1
R1344
SB_RSMRST#
@
R5
1
C1585
10P_0402_50V8J
@
1
R1338
PM_BATLOW#
D22
@
PM_SLP_S3# <35>
PM_SLP_S4# <35>
PM_SLP_S5# <35>
ICH_PWROK <8>
B13
CL_VREF0
CL_VREF1
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
2
SATA
GPIO
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P1
High: CRT Plugged
Internal TPM Strap
+3VS R1389
3.3K_0402_5%
1
R1390 1
3.3K_0402_5%
RSMRST#
CL_DATA0
CL_DATA1
0.1U_0402_16V7K
0.1U_0402_16V7K
<30>
<30>
Reader
<30>
<30>
10K_1206_8P4R_5%
A
PWRBTN#
LAN_RST#
CL_CLK0
CL_CLK1
1
1
R1382
10K_0402_5%
RP42
USB_OC#10
USB_OC#3
USB_OC#7
USB_OC#6
DPRSLPVR
BATLOW#
SLP_M#
+3VS
8
7
6
5
M2
DPRSLPVR/GPIO16
CLPWROK
C1586 2
C1587 2
For Robson2 <33>
USB_OC#5
USB_OC#9
USB_OC#8
USB_OC#11
8
7
6
5
ICH_PWROK
CK_PWRGD
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1
<34>
<34>
Card<34>
<34>
For PCIE LAN<31>
For Card
10K_1206_8P4R_5%
SPI_MOSI
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
S4_STATE#
G20
PWROK
1
T19
ICH9-M ES_FCBGA676
For Wireless LAN<33>
RP41
1
2
3
4
ICH_TP8
ICH_TP9
ICH_TP10
TP11
C10
S4_STATE#/GPIO26
PAD
@
2
For Express
PROJECT_ID0
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
PROJECT_ID1
2
10K_0402_5%
PM_DPRSLPVR
2
100K_0402_5%
ICH_GPIO49
2
1K_0402_5%
1
2
3
4
M7
AJ24
B21
AH20
AJ20
AJ21
VRMPWRGD
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
U23D
2 CP_PE#
10K_0402_5%
2 USB_OC#0
10K_0402_5%
1
R1376
1 @
R1378
SB_SPKR
PAD
PAD
PAD @
@
@
A20
WAKE#
SERIRQ
THRM#
SUS_CLK
C16
E16
G17
E
1
2
1
ICH_GPIO57
<38>
SB_SPKR
<8> MCH_ICH_SYNC#
R1361
<26>
ICH_TP3
100K_0402_5%
T26
T27
T28
D21
AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8
ICH_GPIO13
ICH_GPIO17
ICH_GPIO18
ICH_GPIO20
CR_WAKE#
ICH_GPIO27
ICH_GPIO28
SATA_CLKREQ#
ICH_GPIO38
ICH_GPIO39
ICH_GPIO48
ICH_GPIO49
ICH_GPIO57
<30> CR_WAKE#
T22 PAD
T23 PAD
<16> SATA_CLKREQ# @
@
@
+3V
1 ICH_VGATE
0_0402_5%
ICH_TP11
2
R1343
CLKRUN#
P1
R1328
10_0402_5%
2
@
1
R1370
1
R1371
1 @
R1401
1
R1372
1 @
R1374
1 @
R1375
@
L4
E20
M5
AJ23
OCP#
CRT_DET
CR_CPPE#
EC_SMI#
@
R1355
10K_0402_5%
2
C
STP_PCI#
STP_CPU#
PAD
OCP#
+3V
+3V
A14
E19
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
R1333
10_0402_5%
CLK_ICH_14M <16>
CLK_ICH_48M <16>
C
VGATE
<30> CR_CPPE#
<35>
EC_SMI#
<35>
EC_SCI#
ICH_SMBCLK
1
2
R1351
2.2K_0402_5%
ICH_SMBDATA
1
2
R1352
2.2K_0402_5%
EC_SWI#
1
2
R1353
10K_0402_5%
ICH_SMLINK0
1
2
R1354
10K_0402_5%
ICH_SMLINK1
1
2
R1356
10K_0402_5%
LINKALERT#
1
2
R1358
10K_0402_5%
XDP_DBRESET#
1
2
R1360
10K_0402_5%
1
2 ICH_PCIE_WAKE#
R1362
1K_0402_5%
PM_BATLOW#
1
2
R1363
8.2K_0402_5%
EC_LID_OUT#
1
2
R1366
10K_0402_5%
ICH_GPIO10
1
2
R1367
10K_0402_5%
ICH_GPIO13
1
2
R1368
10K_0402_5%
S4_STATE#
1 <BOM Structure>
2
R1369
10K_0402_5%
SMBALERT#/GPIO11
H_STP_PCI#
H_STP_CPU#
ICH_PCIE_WAKE#
SERIRQ
EC_THERM#
<8,16,49> VGATE
PMSYNC#/GPIO0
A17
PM_CLKRUN#
<35> PM_CLKRUN#
<33,34> ICH_PCIE_WAKE#
<35>
SERIRQ
<35> EC_THERM#
SUS_STAT#/LPCPD#
SYS_RESET#
EC_LID_OUT#
CLK_ICH_14M
CLK_ICH_48M
2
B
@
<16> H_STP_PCI#
<16> H_STP_CPU#
M6
H1
AF3
CLK14
CLK48
1
@
<35> EC_LID_OUT#
T20
R4
G19
PM_SYNC#
<8> PM_SYNC#
<4>
SUS_STAT#
XDP_DBRESET#
clocks
CLK_ICH_14M
5
@
@
RI#
P
@
PAD
F19
2 10K_0402_5%
G
@
T18
<4> XDP_DBRESET#
EC_SWI#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
CLK_ICH_48M
3
@
EC_SWI#
SMB
PROJECT_ID1
PROJECT_ID0
R1325 1
Direct Media Interface
@
<35>
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
AH23
AF19
AE21
AD20
PCI - Express
@
<16,31,33,34> ICH_SMBCLK
<16,31,33,34> ICH_SMBDATA
G16
A13
E17
C17
B18
Power MGT
@
Place closely pin AC1
U23C
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
SYS / GPIO
D
SERIRQ
2
10K_0402_5%
PM_CLKRUN#
2
8.2K_0402_5%
EC_THERM#
2
8.2K_0402_5%
H_STP_PCI#
2
10K_0402_5%
H_STP_CPU#
2
10K_0402_5%
SB_SPKR
2
1K_0402_5%
CR_WAKE#
2
10K_0402_5%
ICH_SPI_MOSI
2
1K_0402_5%
OCP#
2
10K_0402_5%
CR_CPPE#
2
10K_0402_5%
ICH_GPIO17
2
10K_0402_5%
ICH_GPIO18
2
10K_0402_5%
ICH_GPIO20
2
10K_0402_5%
SATA_CLKREQ#
2
10K_0402_5%
ICH_GPIO38
2
10K_0402_5%
ICH_GPIO39
2
10K_0402_5%
ICH_GPIO48
2
10K_0402_5%
MISC
GPIO
Controller Link
1
R1324
1
R1332
1
R1326
1
R1327
1
R1329
1
R1334
1
R1330
1
R1331
1
R1335
1
R1337
1
R1339
1
R1340
1
R1342
1
R1345
1
R1347
1
R1348
1
R1350
2
Title
ICH9M(3/4)-USB,GPIO,PCIE
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
27
of
52
1
1
C1598
D14
CH751H-40PT_SOD323-2
1
C1599
1
+ICH_V5REF
0.1U_0402_16V4Z
2
2
1U_0402_6.3V6K
+ICH_V5REF_SUS
+ICH_V5REF
1
+5V
2
+5VALW
2
D
C1602
1U_0402_6.3V6K
+3V
2
2
D15
CH751H-40PT_SOD323-2
1
1
R1391
100_0402_1%
10_0402_5%
1
R1393
+ICH_V5REF_SUS
2
C1605
1U_0402_6.3V6K
+1.5VS_PCIE_ICH
L38
2
1
KC FBM-L11-201209-221LMAT_08051
+1.5VS
(220UF*1, 22UF*2, 2.2UF*1)
C1607 +
C1608
1
C1609
1
C1610
220U_D2_4VM_R15
10U_0805_10V4Z
2
2
2
10U_0805_10V4Z
2.2U_0603_6.3V6K
+1.5VS_SATAPLL_ICH
C
L39 1
2
MBK1608301YZF_0603
+1.5VS
1
(10UF*1, 1UF*1)
1
C1620
C1621
10U_0805_10V4Z
2
2
1U_0402_6.3V6K
AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
VCCRTC
V5REF
V5REF_SUS
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
VCCA3GP
1
@
A6
CORE
A23
+RTCVCC
R1392
100_0402_1%
3
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
V_CPU_IO[1]
V_CPU_IO[2]
VCC3_3[01]
VCC3_3[02]
VCC3_3[07]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
G
C1623
1
Q92
AO3413_SOT23-3
0.1U_0402_16V4Z
2
D
1
1
C1624
2
1U_0402_6.3V6K
2
1U_0402_6.3V6K
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
+5V
B
AC9
AC18
AC19
AC21
G10
G9
AC12
AC13
AC14
close to AC7
AJ5
+1.5VS
1
0.1U_0402_16V4Z
2
1
AA7
AB6
AB7
AC6
AC7
close to AJ5
2
0.1U_0402_16V4Z
2
1 +VCCLAN1_05_INT_ICH
C1633
0.1U_0402_16V4Z
+VCCLAN_ICH
A10
A11
A12
B12
0_0603_5%
1
C1634
2
0.1U_0402_16V4Z
+1.5VS
+VCC_GLANPLL_ICH
R1399
(10UF*1, 2.2UF*1)
0_0603_5%
1
A27
C1639
D28
D29
E26
E27
C1638
10U_0805_10V4Z
2
2.2U_0603_6.3V6K
A26
+1.5VS
+VCCGLAN_ICH
R1400
(4.7UF*1)
0_0603_5%
C1640
VCCSUS1_5[2]
1
C1601
U23E
1
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
+1.5VS_DMIPLL_ICH
L37 1
2
MBK1608301YZF_0603
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
C1604
C1603
10U_0805_10V4Z
2
0.01U_0402_16V7K
+1.05VS
(4.7UF*1)
1
4.7U_0805_10V4Z
2
R29
W23
Y23
AB23
AC23
+1.05VS
C1611
AG29
AJ6
AC10
C1612
1
C1613
1
(4.7UF*1, 0.1UF*2)
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
AD19
AF20
AG24
AC20
close to AG29
close to AD19
C1614
1
C1615
1
C1616
1
C1617
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCUSBPLL
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCCL1_05
VCCCL1_5
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN3_3
1
C1618
VCCCL3_3[1]
VCCCL3_3[2]
1
C1619
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
close to AJ6
close to B9
close to K7
+VCC_HDA_ICH
AJ4
R1394
0_0603_5%
AJ3
1
AC8 TP_VCCSUS1_05_ICH_1
F17 TP_VCCSUS1_05_ICH_2
AD8 TP_VCCSUS1_5_ICH_1
F18
+VCCSUS1_5_ICH_INT_2
A18
D16
D17
E22
PAD
PAD
@
@
T31
T32
PAD
@
1
2
2
R1395
R1396
1
C1626
0.1U_0402_16V4Z
2
+1.5VS
0.1U_0402_16V4Z
+VCCSUS_HDA_ICH
T33
+3VS
@
0_0603_5%
R1397
C1627
0_0603_5%
@
0.1U_0402_16V4Z
AF1
+3V
+1.5V
Check Power Source
+3V
C1629
1
C1630
1
0.1U_0402_16V4Z
2
2
0.022U_0402_16V7K
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
G22
G23
0_0603_5%
C1622
0.022U_0402_16V7K
VCC1_5_A[20]
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
close to G6
+3VS
B9
F9
G3
G6
J2
J7
K7
C1628
VCC1_5_A[18]
VCC1_5_A[19]
+1.5VS
(10UF*1, 0.01UF*1)
1
VCC1_5_A[17]
GLAN POWER
A
C1632
VCCSUS1_5[1]
USB CORE
C1631
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
VCCSUS1_05[1]
VCCSUS1_05[2]
ATX
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
ARX
C1625
1
VCCSUSHDA
VCCPSUS
+1.5VS
2
<41> SBPWR_EN#
R1398
1
+1.05VS
C1600
VCCSATAPLL
VCCPUSB
AJ19
S
3
+5VALW
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C1606
VCCHDA
+3VS
2
U23F
VCCP_CORE
2
4
PCI
+3VS
2
5
+5VS
close to A18
(0.1UF*1, 0.022UF*2)
close to T1
+VCCCL1_05_INT_ICH
+VCCCL1_5_INT_ICH
A24
B24
+3VS
C1635
1
C1637
1
C1636
1
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
2
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
(0.1UF*1)
1U_0402_6.3V6K
D
C
B
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
ICH9-M ES_FCBGA676
A
@
@
(1UF*1, 0.1UF*1)
ICH9-M ES_FCBGA676
4.7U_0805_10V4Z
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Classification
+3VS
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
4
3
2
Title
ICH9M(4/4)-POWER&GND
Size
Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
28
of
52
5
4
3
+5VS
C1934
2
1
2
1000P_0402_50V7K
D
1
+3VS
0.1U_0402_16V4Z
1
2
C1935
0.1U_0402_16V4Z
1
1
C1936
2
1
C1937
2
10U_0805_10V4Z
1
C1938
2
C1939
2
1000P_0402_50V7K
10U_0805_10V4Z
D
SATA HDD Conn.
JSATA1
<26> SATA_DTX_C_IRX_N0
<26> SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
1
C1940
1
C1941
SATA_DTX_IRX_N0
2
0.01U_0402_16V7K
SATA_DTX_IRX_P0
2
0.01U_0402_16V7K
1
2
3
4
5
6
7
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
<26> SATA_ITX_C_DRX_P0
<26> SATA_ITX_C_DRX_N0
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
+5VS
C
GND
HTX+
HTXGND
HRXHRX+
GND
VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
GND
VCC12
GND
C
24
23
OCTEK_SAT-22SU1G_NR
CONN@
+5VS
0.1U_0402_16V4Z
1
C1942
2
1
2
1000P_0402_50V7K
C1943
1
C1944
2
10U_0805_10V4Z
SATA ODD Conn.
B
B
JSATA2
SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1
<26> SATA_ITX_C_DRX_P1
<26> SATA_ITX_C_DRX_N1
SATA_DTX_IRX_N1
SATA_DTX_IRX_P1
R1664 1
@
2 1K_0402_1%
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GND
GND
16
17
OCTEK_SLS-13DB1G_NR
A
<26> SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_N1
1
C1945
SATA_DTX_IRX_N1
2
0.01U_0402_16V7K
<26> SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_P1
1
C1946
SATA_DTX_IRX_P1
2
0.01U_0402_16V7K
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
HDD & ODD Connector
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
29
of
52
5
4
3
2
1
MDIO PULL HIGH/LOW ?
+3VS
L70
MBK1608121YZF_0603
1
2
40mil
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS
1
C1947
1
C1948
1
C1949
1
C1950
2
2
2
2
+1.8VS_APVDD
40mil
1
C1951
1
0.1U_0402_16V4Z
C1952
+3V_MCVCC
1
C1954
1
C1955
2
2
XDWP_SDWP
@
D
0.1U_0402_16V4Z
1
C1953
2
10U_0805_10V4Z
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
XD_RB
0.1U_0402_16V4Z
1
2
1
2
R1665
1000P_0402_50V7K
10K_0402_5%
R1666
D
10K_0402_5%
+3VS
XD_CLE
1
2
XDCD0#_SDCD#
1
R1668
2
XDCD1#_MSCD#
1
R1669
2
XD_RE
1
2
1
2
U48
<16> CLK_PCIE_READER#
<16> CLK_PCIE_READER
PCIE_ITX_C_PRX_N5
PCIE_ITX_C_PRX_P5
<27> PCIE_ITX_C_PRX_N5
<27> PCIE_ITX_C_PRX_P5
C1956 1
C1957 1
<27> PCIE_PTX_C_IRX_N5
<27> PCIE_PTX_C_IRX_P5
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
R1670 1
PCIE_PTX_IRX_N5
PCIE_PTX_IRX_P5
2 8.2K_0402_1%
APREXT
APREXT 12 mil
APCLKN
APCLKP
9
8
APRXN
APRXP
11
12
APTXN
APTXP
7
38
39
+3VS
R1667
3
4
R1674
2 0_0402_5%
T39 PAD
1
<27> CR_CPPE#
1
2
PLT_RST#
PCIES_EN
PCIES
JMB385
D40
@
CH751H-40PT_SOD323-2
1
2
<27> CR_WAKE#
1
2
R1675
0_0402_5%
@
@
<42> 5IN1_LED#
XRSTN
XTEST
13
14
SEEDAT
SEECLK
@
XDCD1#_MSCD#
XDCD0#_SDCD#
15
16
CR1_CD1N
CR1_CD0N
MC_PWREN#
17
CR1_PCTLN
TP_SEECLK
MC_PWREN# 30 mil
21
DV33
DV33
DV33
DV18
DV18
19
20
44
18
37
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
48
47
46
45
43
42
41
40
29
28
27
26
25
23
22
NC
NC
NC
34
35
36
APREXT
C
<8,17,25,27,31,35>
APVDD
APV18
TAV33
5
10
30
APGND
GND
GND
GND
GND
CR1_LEDN
+1.8VS_APVDD
+3VS
10K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
+1.8VS_APVDD
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
MDIO5 R1672 1
XDWP_SDWP
XD_CLE
XD_D4
XD_D5
XD_D6
XD_D7
XD_RE
XD_RB
XD_ALE
R1671
2 22_0402_5%
200K_0402_5%
XDCE_SDCLK_MSCLK
XD_ALE
R1673
200K_0402_5%
C
6
D41
24
31
32
33
XDCD0#_SDCD#
2
XDCD1#_MSCD#
3
1
XD_CD#
DAN202UT106_SC70-3
C1958
270P_0402_50V7K
JMB385-LGEZ0B_LQFP48_7X7
4 IN 1 Socket Push Type(New)
B
B
JREAD1
Memory Card Power Switch
+3VS
+3V_MCVCC
U49
1
2
3
4
OUT
OUT
OUT
FLG
40mil
8
7
6
5
C1959 1
1
MC_PWREN#
GND
IN
IN
EN#
1 2
TPS2061DRG4_SO8
R1676
300_0603_5%
@
C1961 1
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
D
@
2
G
3
MC_PWREN#
C1960 1
3
+3V_MCVCC
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_D4
XD_D5
XD_D6
XD_D7
32
10
9
8
7
6
5
4
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
SDCMD_MSBS_XDWE#
XDWP_SDWP
XD_ALE
XD_CD#
XD_RB
XD_RE
XDCE_SDCLK_MSCLK
XD_CLE
34
33
35
40
39
38
37
36
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
11
31
7IN1 GND
7IN1 GND
Q116
2N7002_SOT23
S
@
A
MC_PWREN#
1
2
1
R1677
2
0_0805_5%
XD-VCC
41
42
7 IN 1 CONN
21
28
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW
20
14
12
30
29
27
23
18
16
25
1
XDCE_SDCLK_MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
(MMC
XD_D4
(MMC
XD_D5
(MMC
XD_D6
(MMC
XD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#
SD-WP-SW
2
XDWP_SDWP
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
26
17
15
19
24
22
13
XDCE_SDCLK_MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#
+3V_MCVCC
Data
Data
Data
Data
Bit
Bit
Bit
Bit
4)
5)
6)
7)
7IN1 GND
7IN1 GND
A
TAITW_R015-B10-LM
+3V_MCVCC
CONN@
C1962
4.7U_0805_10V4Z
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
SD-VCC
MS-VCC
4
3
2
Title
Card Reader JMB385
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
30
of
52
5
4
3
2
1
LAN AR8121/8112
LAN_MIDI0-
2 0_0603_5%
R1681
1
R1686 1
2 0_0603_5%
1
8112@
4
2
1
2
LAN_MIDI3-
C1970
1
2 C1965 0.1U_0402_16V4Z
2 C1969 0.1U_0402_16V4Z
1
8121@
8121@
+3V_LAN
.
e
d
o
m
l
l
a
r
o
f
9
4
L
d
n
a
8
4
R
,
1
9
5
R
f
f
u
t
S
:
2
1
1
8
R
A
AVDDL/DVDDL
0.1U_0402_16V4Z
2
R1697
4.7K_0402_1%
U50
0.1U_0402_16V4Z
2
8121@
2 0_0603_5%
+3V_LAN
R1695
1
C1974 4.7K_0402_1%
.
d
e
v
o
m
e
2
9
5
R
d
n
a
d
e
f
f
u
s
9
4
L
,
1
9
5
R
,
g
n
i
k
c
o
l
c
r
e
v
o
t
o
n
f
I
.
d
e
v
o
m
e
r
SPI_CLK/DVDDL
D
8121@
a
d
e
f
f
u
t
s
9
4
L
,
2
9
5
R
,
g
n
i
k
c
o
l
c
r
e
v
o
f
I
:
1
2
1
8
R
A
/
3
1
1
8
R
A
2 0_0603_5%
1
C1975
clos to u40
0.1U_0402_16V4Z
5
4
n
i
P
+1.2_DVDDL R1698 1
2 0_0603_5% SPI_DO/AVDDH
1U_0603_10V4Z
2 C1964 0.1U_0402_16V4Z
8
2
n
i
P
C1971
C1972 +2.5V_AVDDH R1694
1 8121@
10U_0603_6.3V6M
1
2
0.1U_0402_16V4Z
C1973 8121@
2
8121@
0.1U_0402_16V4Z
2
8121@
+1.2_DVDDL R1696 1
8121@
8121@
LAN_MIDI3+
2
AVDDVCO2
2
4.7UH_1008HC-472EJFS-A_5%_1008
5
2
n
i
P
1
+2.5V_VDD
DVDDL/AVDDL
C1967
1000P_0402_50V7K
1
1
2 0_0603_5%
C1968
LAN_MIDI2-
2 C1963 0.1U_0402_16V4Z
C1976
8121@
1
1
2
3
4
1U_0603_10V4Z
@
A0
A1
A2
GND
VCC
WP
SCL
SDA
8
7
6
5
2
2 0_0603_5%
R1693
1 8121@
1
1
1
R1692
1 8121@
+1.2_AVDDL
AVDDVCO1
2
4
n
i
P
8121@
+2.5V_AVDDH
VDDLO/CTR12
6
3
n
i
P
2
2
n
i
P
2 0_0603_5%
6
n
i
P
R1690
1
2
L72
1
5
n
i
P
2
Q117
1
1
LAN_MIDI2+
R1688
10K_0402_1%
8121@
+1.2_AVDDL
+1.2_AVDDL
LAN_MIDI1-
R1678 49.9_0402_1%
1
2
R1679 49.9_0402_1%
1
2
R1682 49.9_0402_1%
1
2
R1683 49.9_0402_1%
1
2
R1684 49.9_0402_1%
1
2
R1687 49.9_0402_1%
1
2
R1689
49.9_0402_1%
8121@
1
2
R1691
49.9_0402_1%
8121@
1
2
8121@
2
1
MMJT9435T1G_SOT223
3
0.1U_0402_16V4Z
2
LAN_MIDI1+
1
1
n
i
P
0_0603_5%
R1685
1
2
D
C1966
2 0_0603_5%
8121@
8121@
8121@
1
LAN_MIDI0+
e
k
o
h
c
H
u
7
.
4
R1680 1
+1.2_AVDDL
:
1
2
1
8
R
A
+3V_LAN
L71
4.7UH_1008HC-472EJFS-A_5%_1008
+1.2_DVDDL
1
2
TWSI_SCL
TWSI_SDA
AT24C02BN-SH-T_SO8
U51
2
C
C
:
2
1
1
8
R
A
<32>
VDDHO/VDD18O
LAN_TCT
C1978 0.1U_0402_16V4Z
+3V_LAN
1
2
1U_0603_10V4Z
C1977
+2.5V_AVDDH
2
R1699
1
1
n
i
P
1+2.5V_AVDDH
C1979
0_0603_5%
VDDHO/VDD18O
2
1
+2.5V_VDD
2
1
VDDHO/VDD18O/VDD18O
2
VDD3V
6
SPI_CS/LED_DUPLEXn/LED_DUPLEXn 27
VDD3V/VDDHO/VDDHO
5
VDDLO/CTR12/CTR12
10U_0805_10V4Z
CE2 is 8112@
ceramic capacitor
VDDLO/CTR12
+1.2_AVDDL
R1700
1
R1703
1
7
0_0402_5%
1000P_0402_50V7K
R1701 1
2
C1984 1
2 0.1U_0402_16V7K PCIE_PTX_IRX_N3
C1985 1
0.1U_0402_16V7K
PCIE_PTX_IRX_P3
2
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3
VAUX_AVL/VBG1P18/VBG1P18
8112@ 0.1U_0402_16V4Z
2
0_0603_5%
+2.5V_VDD
2 8121@
0_0603_5%
VAUX/VREF
2
0_0603_5%
8112@
DVDDL/AVDDL
2
0_0603_5%
8112@
AVDDL/DVDDL
2
8112@
4
37
38
44
43
WAKEn
TX_N
TX_P
RX_N
RX_P
9
10
XTLO
XTLI
34
35
TESTMODE
NC
2
<27>
<27>
<27>
<27>
<35> EC_PME#
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3
1
LAN_X1
LAN_X2
Place closed to Chip
5
4
n
i
P
+1.2_AVDDL R1705
1
B
PERSTn
6
3
n
i
P
2
2
n
i
P
+1.2_DVDDL R1704
1
3
8112@
1
2
1
2
LAN_X2
+3VALW
25MHZ_20P
C1994
27P_0402_50V8J
40
41
TXN0/TXN0/TRXN0
TXP0/TXP0/TRXP0
RXN1/RXN1/TRXN1
RXP1/RXP1/TRXP1
NC/NC/TRXN2
NC/NC/TRXP2
NC/NC/TRXN3
NC/NC/TRXP3
14
13
18
17
21
20
24
23
AR8112/8113/8121
LAN_ACTIVITY#
<32>
1000_LINK_LED
C1980 0.1U_0402_16V4Z
CLK_PCIE_C_LAN#1
2
CLK_PCIE_LAN# <16>
CLK_PCIE_C_LAN 1
2
C1981 0.1U_0402_16V4ZCLK_PCIE_LAN <16>
LAN_MIDI0LAN_MIDI0- <32>
LAN_MIDI0+
LAN_MIDI0+ <32>
LAN_MIDI1LAN_MIDI1- <32>
LAN_MIDI1+
LAN_MIDI1+ <32>
LAN_MIDI2LAN_MIDI2- <32>
LAN_MIDI2+
LAN_MIDI2+ <32>
LAN_MIDI3LAN_MIDI3- <32>
LAN_MIDI3+
LAN_MIDI3+ <32>
AVDDVCO2
+1.2_AVDDL
AVDDL/DVDDL
AVDDL/DVDDL
+1.2_AVDDL
AVDDVCO1
+1.2_AVDDL
AVDDL0
AVDDL1
AVDDL2
DVDDL/AVDDL/AVDDL
AVDDL3
AVDDL4
AVDDL5
42
39
36
22
16
11
8
DVDDL0
AVDDL/DVDDL/DVDDL
DVDDL1
SPI_CLK/DVDDL/DVDDL
46
45
32
28
+1.2_DVDDL
AVDDL/DVDDL
+1.2_DVDDL
SPI_CLK/DVDDL
SPI_DO/AVDDH/AVDDH
AVDDH0
AVDDH1
25
19
15
SPI_DO/AVDDH
+2.5V_AVDDH 1
2 C2000
+2.5V_AVDDH 1
2 C2001
C1986
C1987
C1988
C1989
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
2
2
2
2
1
2 C1990 0.1U_0402_16V4Z
1
1
1
2 C1991 0.1U_0402_16V4Z
2 C1992 0.1U_0402_16V4Z
2 C1993 0.1U_0402_16V4Z
B
+3V_LAN
Y2
LAN_X1
26
REFCLKN
REFCLKP
s
o
r
e
h
t
A
+3V_LAN
LAN_RESET#
VAUX/VREF
PLT_RST#
TWSI_SDA
TWSI_SCL
10/100_LINK_LED
30
29
48
47
SPI_DI/NC/LED_Link1000n
C1983
7
n
i
P
R1702
1
1 VDDLO/CTR12
C1982
6
n
i
P
+3V_LAN
<8,17,25,27,30,35>
0_0603_5%
2
5
n
i
P
AVDDL
TWSI_DATA
TWSI_CLK
LED_LINK10_100n
LED_ACTn
1
1
R1707
60mil
2
0_1206_5%
1
C1995
27P_0402_50V8J
2
1
C1996
C1997
1
<16,27,33,34>
C1998
1
<16,27,33,34>
C1999
ICH_SMBCLK
+3V_LAN
1
2
R1706 4.7K_0402_1%
31
33
SMCLK
SMDATA
49
GND
ICH_SMBDATA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1708
1
2.37K_0402_1%
2
12
For AR8112:
R294=2.49K
8121@
For AR8113/8121: R294==2.37K
RBIAS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AR8121-AL1E_QFN48_6X6
D42
10/100_LINK_LED
1
2
1SS355_SOD323-2
A
LAN_LINK#
A
<32>
D43
1000_LINK_LED
1
2
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
1SS355_SOD323-2
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Atheros Ar121/8112
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
31
of
52
5
4
3
2
1
LAN AR8121/8112
T40
D
<31>
<31>
LAN_MIDI0+
LAN_MIDI0-
LAN_MIDI0+
LAN_MIDI0-
L_LAN_MIDI0+
L_LAN_MIDI0-
<31>
LAN_MIDI1+
LAN_MIDI1+
L_LAN_MIDI1+
L_LAN_MIDI1-
<31>
LAN_MIDI1-
LAN_MIDI1-
L_LAN_MIDI2+
L_LAN_MIDI2-
<31>
LAN_MIDI2+
LAN_MIDI2+
L_LAN_MIDI3+
L_LAN_MIDI3-
<31>
LAN_MIDI2-
LAN_MIDI2-
1
2
3
4
5
6
7
8
9
10
11
12
D
TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-
MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-
24
23
22
21
20
19
18
17
16
15
14
13
RJ45_MIDI0+
RJ45_MIDI0RJ45_MIDI1+
RJ45_MIDI1-
1
RJ45_MIDI2+
RJ45_MIDI2-
C2002
220P_0402_50V7K
RJ45_MIDI3+
RJ45_MIDI3-
350uH_GSL5009-1 LF
JPJ1
<31> LAN_ACTIVITY#
2
R1709
+3V_LAN
2
L_LAN_ACTIVITY# 12
Yellow LED-
11
Yellow LED+
1
1K_0402_5%
LAN_MIDI3+
RJ45_MIDI3-
8
PR4-
<31>
LAN_MIDI3-
LAN_MIDI3-
RJ45_MIDI3+
7
PR4+
RJ45_MIDI1-
6
PR2-
RJ45_MIDI2-
5
PR3-
RJ45_MIDI2+
4
PR3+
RJ45_MIDI1+
3
PR2+
RJ45_MIDI0-
2
PR1-
RJ45_MIDI0+
1
PR1+
1
LAN_MIDI3+
C
C2003
1
C2004
1
0.1U_0402_16V4Z
2
2
2
C2005
1
C2006
1
8121@
R1712
8121@
75_0402_1%
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z8121@ 0.1U_0402_16V4Z
R1713
75_0402_1%
2
1
2
LAN_TCT
2
<31>
R1711
75_0402_1%
2
R1710
75_0402_1%
LAN_TCT
1
1
<31>
RJ45_GND
40mil
L_LAN_LINK#
<31> LAN_LINK#
2
R1714
+3V_LAN
8121@
10
1
1K_0402_5%
Guide Pin
SHLD2
14
SHLD1
13
C
Green LED-
9
Green LED+
SUYIN_100073FR012G101ZL
Place close to TCT pin
1
2
C2007
220P_0402_50V7K
RJ45_GND
1
LANGND
1
2
1
C2008
1000P_1206_2KV7K
C2009
2
2
40mil
C2010
4.7U_0805_10V4Z
0.1U_0402_16V4Z
B
B
L_LAN_ACTIVITY#
1
2
C2011
68P_0402_50V8J
@
L_LAN_LINK#
1
2
C2012
68P_0402_50V8J
@
For EMI
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
LAN Magnetic & RJ45
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
32
of
52
A
B
C
D
E
For Robson2
+1.5VS
1
+3VS
C2013
1
4.7U_0805_10V4Z
2 KAL90@
2
C2014
0.1U_0402_16V4Z
KAL90@
1
2
1
C2015
0.1U_0402_16V4Z
KAL90@
2
C2016
4.7U_0805_10V4Z
KAL90@
1
2
Mini Card Power Rating
C2017
0.1U_0402_16V4Z
KAL90@
1
JMINI1
1
3
5
7
9
11
13
15
<16> MINI1_CLKREQ#
<16> CLK_PCIE_MINI1#
<16> CLK_PCIE_MINI1
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
<27> PCIE_PTX_C_IRX_N4
<27> PCIE_PTX_C_IRX_P4
<27> PCIE_ITX_C_PRX_N4
<27> PCIE_ITX_C_PRX_P4
+3VS
For MINICARD Port80 Debug
<35> E51TXD_P80DATA
<35> E51RXD_P80CLK
KAL90@
E51TXD_P80DATA R1717 1
E51RXD_P80CLK
2 0_0402_5% CL_RST#1_R
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
+3VS
Normal
+3VS
1000
750
+3V
330
250
250 (wake enable)
Normal
+1.5VS
500
375
5 (Not wake enable)
1
+1.5VS
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
PLT_RST_BUF#
PLT_RST_BUF# <25>
MINI1_SMBCLK
MINI1_SMBDATA
R1715 1
R1716 1
2 0_0402_5% ICH_SMBCLK
2 0_0402_5% ICH_SMBDATA
@
@
ICH_SMBCLK <16,27,31,34>
ICH_SMBDATA <16,27,31,34>
USB20_N7 <27>
USB20_P7 <27>
USB CONN.
(LED_WWAN#)
(LED_WLAN#)
+USB_VCCA
W=80mils
+USB_VCCA
2
1
C2018 +
150U_D2_6.3VM
@
FOX_AS0B226-S99N-7F
53
54
55
56
Auxiliary Power (mA)
Peak
G1
G2
G3
G3
2
Primary Power (mA)
Power
CONN@
1
C2019
470P_0402_50V7K
2
2
JUSB1
D62
4
+USB_VCCA
USB20_N0
3
VIN
IO1
IO2 GND
2
USB20_P0
<27>
<27>
1
1
2
3
4
USB20_N0
USB20_P0
USB20_N0
USB20_P0
PRTR5V0U2X_SOT143-4
5
6
7
8
For Wireless LAN
+3VS_WLAN
+3VS_WLAN
R1718 1
R1719 1
@
2 0_1206_5%
+3VS
2 0_1206_5%
+3V
1
2
1
4.7U_0805_10V4Z
2
C2021
0.1U_0402_16V4Z
1
2
1
C2022
0.1U_0402_16V4Z
2
1
C2023
4.7U_0805_10V4Z
2
1
C2024
0.1U_0402_16V4Z
2
C2025
To USB/B Connector
0.1U_0402_16V4Z
80mil
JP15
3
JMINI2
R1720 1
@
2 0_0402_5%
WLAN_BT_DATA
WLAN_BT_CLK
<27,34> ICH_PCIE_WAKE#
<34> WLAN_BT_DATA
<34> WLAN_BT_CLK
<16> MINI2_CLKREQ#
<16> CLK_PCIE_MINI2#
<16> CLK_PCIE_MINI2
<27> PCIE_PTX_C_IRX_N2
<27> PCIE_PTX_C_IRX_P2
<27> PCIE_ITX_C_PRX_N2
<27> PCIE_ITX_C_PRX_P2
+3VS_WLAN
For MINICARD Port80 Debug
2 0_0402_5% CL_RST#2_R
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
(WAKE#)
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
2
3
4
5
6
7
8
GND
GND
+3VS_WLAN
+1.5VS
1
2
3
4
5
6
7
8
9
10
+5VALW
3
+5VALW
SYSON#
USB20_N5
USB20_P5
<34,41>
C2026
USB20_N5 <27>
USB20_P5 <27>
1
4.7U_0805_10V4Z
2
USB_OC#5 <27>
ACES_85201-08051
WL_OFF#
PLT_RST_BUF#
+3V_WLAN
R1721 1
R1722 1
MINI2_SMBCLK R1723 1
MINI2_SMBDATA R1724 1
WL_OFF# <35>
2 0_0603_5%
2 0_0603_5%
@
+3VS
+3V
2 0_0402_5% ICH_SMBCLK
2 0_0402_5% ICH_SMBDATA
@
@
USB20_N8 <27>
USB20_P8 <27>
(LED_WWAN#)
(LED_WLAN#)
MINI1_LED# <36>
(9~16mA)
G1
G2
G3
G3
E51TXD_P80DATA R1725 1
E51RXD_P80CLK
1
3
5
7
9
11
13
15
GND1
GND2
GND3
GND4
SUYIN_020173MR004G565ZR
CONN@
+1.5VS
C2020
VCC
DD+
GND
53
54
55
56
4
4
FOX_AS0B226-S99N-7F
CONN@
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
MINI CARD (WLAN & Robson2)
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
E
33
of
52
A
B
C
D
E
New Card Power Switch
U52
12
14
2
4
+3V
17
PCI_RST#
PCI_RST#
<35,41,47> SYSON
<35,37,41,50> SUSP#
20
SUSP#
1
3.3Vout
3.3Vout
AUX_IN
6
SYSON
3.3Vin
3.3Vin
PERST#
STBY#
NC
CPPE#
C2027
+3VS_CARD
1
1
10U_0805_10V4Z
2
40mil
+3VALW_CARD
Imax = 1.35A
C2028
C2029
1
1
C2031
10U_0805_10V4Z
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
R1726
10K_0402_5%
CLKREQ1#
2
B
2
C2036
1
D
3
S
A
NC7SZ32P5X_NL_SC70-5
Q118
2N7002_SOT23
RCLKEN1 2
G
+1.5VS
1
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z
PERST1#
<27> CP_PE#
<16> CLK_PCIE_CARD#
<16> CLK_PCIE_CARD
0.1U_0402_16V4Z
U53
Y
CLKREQ1#
CP_PE#
C2033
4
<27> PCIE_PTX_C_IRX_N1
<27> PCIE_PTX_C_IRX_P1
EXP_CLKREQ# <16>
<27> PCIE_ITX_C_PRX_N1
<27> PCIE_ITX_C_PRX_P1
27
28
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
1
GND
GND
29
30
SANTA_131851-A_LT
1
CONN@
+3V
+3VS
1
1
10U_0805_10V4Z
2
2
Finger Print Conn.
2
JP16
KAL90@ C2037
0.1U_0402_16V4Z
2
1
USB20_N10
USB20_P10
6
5
4
3
2
1
2
3
<27> USB20_N10
<27> USB20_P10
2
R578
0_0603_5%
KAL90@
2
R577
0_0603_5%
@
D44
SM05T1G_SOT23-3
Bluetooth Conn.
ESATA CONN
G2
G1
4
3
2
1
+USB_VCCA
ACES_85201-04051
W=60mils
+3VS
1000P_0402_50V7K
1
CONN@
C2038 +
150U_Y_6.3VM
1
+3VALW
CP_USB#
+3VS_CARD
+3VS
10U_0805_10V4Z
2
USB20_N1
USB20_P1
<27,33> ICH_PCIE_WAKE#
+3VALW_CARD
21
Thermal_Pad
C2035
<27>
<27>
C2032
7
+3V
1
1
+3VS
16
1
10U_0805_10V4Z
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
<16,27,31,33> ICH_SMBCLK
<16,27,31,33> ICH_SMBDATA
+1.5VS_CARD
G577NSR91U_TQFN20_4x4
C2034
C2030
PERST1#
8
RCLKEN
+3VS
JEXP1
Imax = 0.75A
19
GND
CPUSB#
60mils
15
OC#
SHDN#
Imax = 0.275A
+1.5VS_CARD
3
5
AUX_OUT
SYSRST#
CP_PE#
10
(Internal Pull High to AUXIN)
CP_USB#
9
(Internal Pull High to AUXIN)
RCLKEN1
18
11
13
5
<25>
+3VS
1.5Vout
1.5Vout
+1.5VS_CARD
G Vcc
1
1.5Vin
1.5Vin
+3VS_CARD
3
+1.5VS
New Card Socket (Left/TOP)
+3VALW_CARD
40mil
2
@
1
1
C2039
C2040
2
0.1U_0402_16V4Z
2
@
JP17
1
2
10K_0402_5%
4
+USB_VCCA
1U_0603_10V4Z
USB20_N2
3
2
1
VIN
IO1
IO2 GND
2
<27>
<27>
USB20_P2
W=40mils
0.1U_0402_16V4Z
2
SATA_ITX_C_DRX_P5
SATA_ITX_C_DRX_N5
<26> SATA_ITX_C_DRX_P5
<26> SATA_ITX_C_DRX_N5
C2044 2
C2045 2
<26> SATA_DTX_C_IRX_N5
<26> SATA_DTX_C_IRX_P5
+BT_VCC
1
1
C2047
R1728
4.7U_0805_10V4Z
300_0603_5%
2
2
0.1U_0402_16V4Z
1
SATA_ITX_C_DRX_N5
Q120
2N7002_SOT23
3
3
VIN
IO1
IO2 GND
2
@
@
12
13
14
15
1
PRTR5V0U2X_SOT143-4
S
+3V
80mil
JP18
<33> WLAN_BT_DATA
<33> WLAN_BT_CLK
SHIELD
SHIELD
SHIELD
SHIELD
SATA_ITX_C_DRX_P5
+BT_VCC
4
ESATA
CONN@
4
+5VALW
1
2
3
4
5
6
7
8
1 GND
2
3
4
5
6
7
8 GND
+5VALW
9
+USB_VCCA
R1730
0_0402_5%
1
2
U54
1
2
3
4
D61
4
+5VALW
SATA_IRX_DTX_P5
10
3
VIN
IO1
IO2 GND
2
SATA_IRX_DTX_N5
C2048
1
1
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
R1729
100K_0402_5%
8
7
6
5
1
2
R1731
10K_0402_5%
TPS2061DRG4_SO8
PRTR5V0U2X_SOT143-4
4.7U_0805_10V4Z
2
ACES_87213-0800G
USB_OC#2 <27>
2
USB20_P9
USB20_N9
R1754
0_0402_5%
1R1768 0_0402_5%
2
1
2
GND
A+
AGND
BB+
GND
D60
D
2
G
3
5
6
7
8
9
10
11
TYCO_1909574-1
2
C2046
<27>
<27>
SATA_IRX_DTX_N5
SATA_IRX_DTX_P5
0.01U_0402_25V7K
0.01U_0402_25V7K
1
1
USB
VBUS
DD+
GND
1
PRTR5V0U2X_SOT143-4
Q119
AO3413_SOT23-3
1
2
3
4
USB20_N2
USB20_P2
USB20_N2
USB20_P2
1
C2043
2
C2042
1
1
R1727
1
BT_ON#
D59
G
<35>
D
3
3
0.1U_0402_16V4Z
2
S
C2041
1
USB_OC#0 <27>
1
2
CONN@
4
C2049
0.1U_0402_16V4Z
<33,41> SYSON#
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
NEW CARD & eSATA Connector
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
E
34
of
52
4
3
2
1
For EC Tools
+3VALW
KSI[0..7]
KSI[0..7]
L73
C2056
1000P_0402_50V7K
2
C
2
+3VALW +3VALW
+3VALW
1
1
R1739
10K_0402_5%
R1840
47K_0402_5%
1
2
R1841
47K_0402_5%
D45
<37>
1
RCIRRX
2
EC_RCIRRX
CH751H-40PT_SOD323-2
+5VS
2 TP_CLK
4.7K_0402_5%
2 TP_DATA
4.7K_0402_5%
1
R1741
1
R1743
<36,44>
<36,44>
<4,18,36>
<4,18,36>
+3VALW
B
2 EC_SMB_CK1
4.7K_0402_5%
2 EC_SMB_DA1
4.7K_0402_5%
1
R1745
1
R1746
2
R1769
1
R1747
@
<27> PM_SLP_S3#
<27> PM_SLP_S5#
<27>
EC_SMI#
<36>
LID_SW#
1 EC_I2C_INT2
10K_0402_5%
2 LID_SW#
100K_0402_5%
<31>
EC_PME#
<8> MCH_TSATN_EC#
<40> FAN_SPEED1
<34>
BT_ON#
<37>
ON/OFF
<42> PWR_SUSP_LED
<36,42> NUM_LED#
+3VS
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
EC_GPIOB
EC_GPIOC
EC_PME#
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED
NUM_LED#
2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%
EC_CRY1
EC_CRY2
<36> EC_ESB_CK
<36> EC_ESB_DA
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
77
78
79
80
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
1
R1750
1
R1751
1
R1752
1
R1753
2 @
4.7K_0402_5%
2 @
4.7K_0402_5%
2 @
0_0402_5%
2 @
0_0402_5%
BATT_TEMP
BATT_OVP
3S/4S#
+3VALW
@
83
84
85
86
87
88
EC_MUTE
EC_I2C_INT2
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
3S/4S#
65W/90W#
SBPWR_EN
ID_JAL90_JAW50#
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SPIDI/FWR#
EC_SPIDO/FRD#
EC_SPICLK
EC_SPICS#/FSEL#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_RCIRRX
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
SM Bus
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
GPI
XCLK1
XCLK0
KB926QFC0_LQFP128_14X14
TP_CLK
TP_DATA
C
+3VALW
65W/90W#
2
R1740
3S/4S# <46>
65W/90W# <46>
SBPWR_EN <41,47>
PAD T49 @
PAD T50 @
1
C2061
C2060
8.2K_0402_5%
2
0.1U_0402_16V4Z
EC_CRY1
B
EC_CRY2
1
1
15P_0402_50V8J
2
PM_SLP_S4# <27>
ENBKL
<10,18>
EAPD
<38>
EC_THERM# <27>
SUSP#
<34,37,41,50>
PBTN_OUT# <27>
MC_RST# <36>
SUSP#
PBTN_OUT#
MC_RST#
AD_BID0
R1744
Rb
EC_RSMRST# <27>
EC_LID_OUT# <27>
EC_ON
<37>
EC_SWI# <27>
EC_PWROK <27,37>
BKOFF# <22>
WL_OFF# <33>
ENBKL
EAPD
R1742
100K_0402_5%
Ra
FSTCHG <46>
BATT_GRN_LED# <36>
@ <42>
CAPS_LED#
BATT_AMB_LED# <36>
PWR_LED <42>
SYSON
<34,41,47>
VR_ON
<37,49>
ACIN
<27,41,42,43,46>
EC_PWROK
BKOFF#
WL_OFF#
2
+3VALW
PAD T51
EC_LID_OUT#
EC_ON
1
100K_0402_5%
Analog Board ID definition,
Please see page 3.
EC_SI_SPI_SO <36>
EC_SO_SPI_SI <36>
EC_SPICLK <36>
EC_SPICS#/FSEL# <36>
FSTCHG
BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED
SYSON
VR_ON
ACIN
1
1
100K_0402_5%
1
@
EC_MUTE <39>
EC_I2C_INT2 <37>
PGD_IN
<49>
BT_LED# <36>
TP_CLK
<36>
TP_DATA <36>
C2062
15P_0402_50V8J
2
X2
32.768KHZ_12.5P_MC-306
For KB926 C0 reversion
C2063
1U_0402_6.3V6K
C2064
BATT_TEMP
2
C2065
BATT_OVP
2
C2066
ACIN
2
20mil
L74
ECAGND 2
1
FBM-L11-160808-800LMT_0603
100P_0402_50V8J
1
100P_0402_50V8J
1
100P_0402_50V8J
1
A
EC_GPIOB
EC_GPIOC
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
ID_JAL90_JAW50#
2
R1737
2 @
R1738
100K_0402_5%
DAC_BRIG <22>
EN_DFAN1 <40>
IREF
<46>
CALIBRATE# <46>
SPI Device Interface
GPIO
2
4.7K_0402_5%
PAD T48
@
PAD T42
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SPI Flash ROM
1
R1734
BATT_TEMP <44>
BATT_OVP <46>
ADP_I
<46>
AD_BID0
DAC_BRIG
EN_DFAN1
IREF
PS2 Interface
PAD T41
ACOFF
<46>
ECAGND
2
1
C2059 0.01U_0402_16V7K
@
68
70
71
72
11
24
35
94
113
+3VS
A
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
63
64
65
66
75
76
INVT_PWM <22>
BEEP#
<38>
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
DA Output
GND
GND
GND
GND
GND
1
R1748
1
R1749
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SCI#
AD
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
INVT_PWM
BEEP#
4
PLT_RST#
<27>
EC_SCI#
<27> PM_CLKRUN#
2
1
R1736
47K_0402_5%
2
1
C2058
0.1U_0402_16V4Z
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
PWM Output
21
23
26
27
1
<8,17,25,27,30,31>
+3VALW
12
13
37
20
38
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
IN
<16> CLK_PCI_LPC
D
@
OUT
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
10K_0402_5%
NC
1
2
R1733
NC
@
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
ACES_85205-0400
ENBKL
AGND
R1735 2
1
2
3
4
5
7
8
10
69
C2057 @
22P_0402_50V8J
2
1
<26> EC_GA20
<26> EC_KBRST#
<27>
SERIRQ
<26> LPC_FRAME#
<26>
LPC_AD3
<26>
LPC_AD2
33_0402_5%
<26>
LPC_AD1
<26>
LPC_AD0
E51RXD_P80CLK <33>
E51TXD_P80DATA <33>
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
U55
E51RXD_P80CLK
E51TXD_P80DATA
67
9
22
33
96
111
125
D
9/21 add R for nvidia
0.1U_0402_16V4Z
1
2
3
4
1
2
3
4
C2051
2
Place on RAM door
JP19
3
2
2
0.1U_0402_16V4Z
C2055
1000P_0402_50V7K
1
1
+3VALW
<36>
2
2
2
0.1U_0402_16V4Z
EC_PME#
2
10K_0402_5%
1
R1732
C2054
KSO[0..17]
1
2
C2050
KSO[0..17]
1
2 +EC_VCCA
2 FBM-L11-160808-800LMT_0603
1
0.1U_0402_16V4Z
1
2
1
+3VALW
0.1U_0402_16V4Z
1 C2053
1
C2052
ECAGND
1
<36>
2
5
4
3
2
Title
EC ENE KB926
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
1
35
of
52
To TP/B Conn.
U56
1
R1757
+3VALW
C2067 1
2
0_0603_5%
EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#
2 0.1U_0402_16V4Z
1
3
7
4
+SPI_VCC
EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#
R1758 1
R1760 1
+3VALW
1
3
7
4
VCC
SCLK
SI
SO
JP21
+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI
EC_SI_SPI_SO
8
6
5
2
+5VS
<35>
<35>
CE#
WP#
HOLD#
VSS
VDD
SCK
SI
SO
8
6
5
2
EC_SPICLK_R
R1759 1
R1761 1
R1762 1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
Reserved
for BIOS simulator.
@
Footprint SO8
EC_SPICLK <35>
EC_SO_SPI_SI <35>
EC_SI_SPI_SO <35>
LEFT_BTN# 3
SW4
SMT1-05-A_4P
1
4
2
C2068
100P_0402_50V8J
1
2
2
6
5
4
3
2
1
8
7
8
7
ACES_85201-0605
C2069
100P_0402_50V8J
CONN@
5
6
MX25L8005M2C-15G_SOP8
1
6
5
4
3
2
1
TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#
TP_CLK
TP_DATA
MX25L512AMC-12G_SO8
U57
<35> EC_SPICS#/FSEL#
CS#
WP#
HOLD#
GND
TP_CLK
(Right)
<4,18,35> EC_SMB_DA2
<35> EC_ESB_CK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
<35> EC_ESB_DA
1
@
LEFT_BTN# 3
SW1
SMT1-05-A_4P
1
4
2
kal90@
RIGHT_BTN#3
SW2
SMT1-05-A_4P
1
4
2
kal90@
JP22
1 KAL90@ 2
0_0402_5%
1 KAL90@ 2
R1766
0_0402_5%
<35,44> EC_SMB_CK1
R1765
<35,44> EC_SMB_DA1
<37> EC_I2C_INT1
<35>
MEDIA_DA
MC_RST#
MC_RST#
+3VALW
MEDIA_CK
1
2
@ R1790
0_0402_5%
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
C2093 @
0.1U_0402_16V4Z
R1808
10K_0402_5%
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
GND
GND
e-key/B
JP28
JP25
KSO0
KSI5
ACES_85201-08051
1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
PSOT24C_SOT23
5
6
JP23
(Left)
1 KALH0@2
R1846
0_0402_5%
1 KALH0@2
R1847
0_0402_5%
1@
2
R1763
0_0402_5%
1 @
2
R1764
0_0402_5%
<4,18,35> EC_SMB_CK2
0.1U_0402_16V4Z
5
6
<35>
KSO[0..17] <35>
D46
2
5
6
1
2
KSI[0..7]
KSO[0..17]
4
0_0603_5%
KALH0@ 2
1
R106
0_0603_5%
KAL90@ 2
1
R109
To Media/B Conn. 0_0603_5%
KSI[0..7]
3
C2070
R105
INT_KBD Conn.
TP_DATA
2
+5VS +3VS MCVCC
ENE suggestion SPI Frequency over 66MHz
SST: 50MHz
MXIC: 70MHz
ST: 40MHz
+5VS
SW5
SMT1-05-A_4P
RIGHT_BTN#3
1
CONN@
1
2
3
4
E&T_6905-E04N-00R
CONN@
G1
G2
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
GND
GND
1
2
3
4
+5VS
+3VS
MINI1_LED#
FB_KSI4
BT_LED#
FB_KSI3
MINI1_LED# <33>
BT_LED# <35>
CONN@
ACES_85201-08051
27
28
To BTN/B Conn.
ACES_85201-26051
KSO16
CONN@
KSO17
C2071 1
C2072 1
2
2
100P_0402_50V8J
100P_0402_50V8J
@
FB_KSI4
KSI4
2
0_0402_5%
1
R1834
1
KSO15
C2073 1
2
100P_0402_50V8J
KSO7
C2074 1
2
100P_0402_50V8J
KSO14
C2075 1
2
100P_0402_50V8J
KSO6
C2076 1
2
100P_0402_50V8J
KSO13
C2077 1
2
100P_0402_50V8J
KSO5
C2079 1
2
100P_0402_50V8J
KSO12
C2080 1
2
100P_0402_50V8J
KSO4
C2078 1
2
100P_0402_50V8J
KSI0
C2081 1
2
100P_0402_50V8J
KSO3
C2082 1
2
100P_0402_50V8J
KSO11
C2083 1
2
100P_0402_50V8J
KSI4
C2084 1
2
100P_0402_50V8J
KSO10
C2085 1
2
100P_0402_50V8J
KSO2
C2086 1
2
100P_0402_50V8J
100P_0402_50V8J
KSO1
C2088 1
2
100P_0402_50V8J
KSO0
NUM_LED# <35,42>
2
0_0402_5%
R1835
@
FB_KSI3
1
R1832
1
R1833
KSI3
2
0_0402_5%
2
0_0402_5%
MEDIA_LED# <42>
KSI1
WL_BTN#
KSI2
BT_BTN#
KSI3
EMAIL_BTN#
KSI4
IE_BTN#
KSI5
E-KEY_BTN#
JP26
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND
GND
+5VS
+3VS
MINI1_LED#
KSI1
FB_KSI4
KSO0
KSI2
BT_LED#
FB_KSI3
MINI1_LED# <33>
BT_LED# <35>
ACES_85201-1005N
KSI1
C2087 1
2
Lid Switch
CONN@
(Hall Effect Switch)
KSI2
C2089 1
2
100P_0402_50V8J
KSO0
C2090 1
2
100P_0402_50V8J
KSO9
C2091 1
2
100P_0402_50V8J
KSI5
C2092 1
2
100P_0402_50V8J
KSI3
C2094 1
2
100P_0402_50V8J
KSI6
C2095 1
2
100P_0402_50V8J
FOR EMI
+3VALW
2
100P_0402_50V8J
1
C2098 1
2
C2103
0.1U_0402_16V4Z
1
OUTPUT
4
2
3
1
+5VALW
1 R1772 2
200_0402_1%
2
1 R1773 2
@
330_0402_5%
4
PWR_LED#
B
1
A
3PWR_SUSP_LED#
HT-297UD/CB _BLUE/AMB_0603
GND
LED1
Compal Footprint+5VALW
PWR_LED# <42>
PWR_SUSP_LED# <42>
U58
A3212ELHLT-T_SOT23W-3
R1771
47K_0402_5%
2
KSI7
100P_0402_50V8J
2
2
VDD
C2097 1
R1770
10K_0402_5%
1
2
3
1
D48
1
2 LID_SW#
RB751V_SOD323
C2101 1
LID_SW# <35>
2
R1774
1
2
180_0402_5%
2
YG
1
BATT_GRN_LED#
+5VALW
1 R1775
4
A
3
BATT_AMB_LED#
2
C2099 1
2
100P_0402_50V8J
BT_LED#
C2100 1 @ 2
100P_0402_50V8J
@
KSO0
C2104 1
2
100P_0402_50V8J
KSI1
C2106 1 @ 2
100P_0402_50V8J
KSI2
C2108 1 @ 2
100P_0402_50V8J
KSI3
C2110 1 @ 2
100P_0402_50V8J
KSI4
C2113 1 @ 2
100P_0402_50V8J
C2111
10P_0402_50V8J
footpint not right
360_0402_5%
HT-297DQ-GQ_AMB-YG
BATT_GRN_LED# <35>
100P_0402_50V8J
MINI1_LED#
@
LED2
+5VALW
2
@
@
1
KSO8
KSI5
+3VS
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Deciphered Date
2008/11/17
Title
BIOS, I/O Port & K/B Connector
BATT_AMB_LED# <35>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Tuesday, January 06, 2009
Sheet
36
of
52
A
B
C
D
E
Power Button
ON/OFF switch
HDA MDC Conn.
+3V
+3VALW
1
1
JMDC1
2
10K_0603_5%
@
R1780
2
R1779
100K_0402_5%
@
1
<26> HDA_SYNC_MDC
<26> HDA_SDIN1
<26> HDA_RST_MDC#
D49
2
ON/OFFBTN#
<42> ON/OFFBTN#
<26> HDA_SDOUT_MDC
10K_0603_5%
Bottom Side
1
51ON#
3
1
3
5
7
9
11
ON/OFF
<35>
51ON#
<43>
1
2
R1781
HDA_SDIN1_MDC
33_0402_5%
1
3
5
7
9
11
1
15mil
2
R1777
1
2
4
6
8
10
12
1
R1776
1
R1778
+MDC_VCC
2
4
6
8
10
12
+1.5V
2
C2114
1
1U_0603_10V4Z
HDA_BITCLK_MDC <26>
R1782
0_0402_5%
CONN@
51ON#
+3V
+3V
ACES_88018-124N
2
DAN202UT106_SC70-3
2
0_0402_5%
2
0_0402_5% @
1
TOP Side
1
1
1
MCVCC
D50
<36> EC_I2C_INT1
1
3
1
S 2N7002_SOT23
D
3
3
R1783
10K_0402_5%
1
Q122
For EMI
D
Q124 kal90@
2
G
10K_0402_5%
R1838 kal90@
D
2
G
22P_0402_50V8J
2
MCVCC +3VS
2
1
EC_ON
EC_ON
2
<35>
2
C2115
R1836 kal90@
510K_0402_5%
RLZ20A_LL34
R1845 KALH0@
1
2
1000P_0402_50V7K
1
2
C2116
2
S 2N7002_SOT23
S 2N7002_SOT23
Q138 kal90@
2
G
1
10K_0402_5%
2
2
2
+3VALW
R1837
Power ON Circuit
1
@
10K_0402_5%
@
1
D47
2
EC_I2C_INT2 <35>
1SS355_SOD323-2
+3VS
+3VALW
R42
1
2 0_0402_5%
1
+3VALW
I
O
2
3
14
I
7
2
C2117
1U_0603_10V6K
@
O
4
G
1
P
P
2
2
CH751H-40PT_SOD323-2
U59B
SN74LVC14APWLE_TSSOP14
SYS_PWROK
1
R1785 @
2
0_0402_5%
EC_PWROK <27,35>
For South Bridge
7
1
VR_ON
U59A
SN74LVC14APWLE_TSSOP14
G
<35,49>
14
R1784
@
180K_0402_5%
D51 @
1
3
3
+3VS
+3VALW
+3VALW
1
+RTCBATT
O
8
VS_ON
For +VCCP/+1.05VS
2
CIR
+3VALW
<47,48>
R1788
1K_0402_5%
1
I
R1789
100_0805_5%
KAL90@
1
D52
1 1
14
P
9
G
6
2
S
U59D
SN74LVC14APWLE_TSSOP14
7
C2118
0.1U_0402_16V7K
O
7
SUSP
2
G
Q123
2N7002_SOT23
3
<41,48>
SUSP
I
G
5
2
D
U59C
SN74LVC14APWLE_TSSOP14
P
2
R1787
10K_0402_1%
1
2
1
<34,35,41,50> SUSP#
14
R1786 @
10K_0402_1%
IR1 KAL90@
4.7U_0805_10V4Z
KAL90@
1
OUT
GND
RCIRRX
4
2
RCIRRX
<35>
+RTCVCC
1
2
2
2
Vs
GND
TSOP36236TR_4P
3
3
1
C2119
BAS40-04_SOT23-3
C2121 KAL90@
1
1000P_0402_50V7K
2
+CHGRTC
C2122
0.1U_0402_16V4Z
4
4
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Power OK, Reset,RTC, CIR, MDC
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
E
37
of
52
A
B
C
D
E
F
G
H
+VDDA
1
+5VAMP
R1528
10K_0402_5%
2
+5VS
2
(output = 300 mA)
U40
1
1
1
L46 1
C1831
C1832
2
KC FBM-L11-201209-221LMAT_0805
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z
2
3
IN
OUT
40mil
5
GND
SHDN
BYP
G9191-475T1U_SOT23-5
1
C1833 1U_0402_6.3V6K
R1529
10K_0402_5%
E
560_0402_5%
1
R1532
2SC2411K_SOT23
268@
888VB@
888VC@
L47
MBK1608121YZF_0603
1
2
2
560_0402_5%
10mil
HD Audio Codec
D29
CH751H-40PT_SOD323-2
1
1
C1839
C1840
35
AMP_LEFT
FRONT_R
36
AMP_RIGHT
1K_0402_5%
1 INT_MIC_R
KLH0@
16
MIC2_L
SURR_L
39
HP_LEFT
17
MIC2_R
SURR_R
41
HP_RIGHT
<39>
LINE_L
23
LINE1_L
SIDE_L
45
<39>
LINE_R
LINE1_R
SIDE_R
20
19
MIC1_L
<39>
MIC1_R
MIC1_L
MIC1_C_L
2
4.7U_0603_6.3V6M
MIC1_C_R
2
4.7U_0603_6.3V6M
MONO_IN
1
C1851
1
C1852
MIC1_R
SENSE A
4
2 10K_0402_1%
1 20K_0402_1%
<39> HP_PLUG#
R1545 2
1 39.2K_0402_1%
Impedance
SPDIF
Codec Signals
39.2K
PORT-A (PIN 39, 41)
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
<35>
100P_0402_50V8J 1
2 C1857
DMIC_DATA
1
2
R1548
1 KAL90@ 2
R1549 888VB@
1
2
R1552 KALH0@
PORT-F (PIN 16, 17)
10K
PORT-G (PIN 43, 44)
5.1K
PORT-H (PIN 45, 46)
1
R1546
0_0402_5%
0_0402_5%
12
PCBEEP
SDATA_IN
PIN37_VREFO
LINE1_VREFO
RESET#
MIC1_VREFO_R
SPDIFO2
GPIO0/DMIC_CLK MIC2_VREFO
SENSE A
SENSE B
VREF
47
SPDIFI/EAPD
SPDIFO
C1849
220P_0402_50V7K
2 KALH0@
HDA_BITCLK_AUDIO <26>
HDA_SDIN0_AUDIO
1
R1540
2
33_0402_5%
Digital MIC
HDA_SDIN0 <26>
+3VS
JP13
MIC1_VREFO_L
MIC1_VREFO_R
30
MIC2_VREFO
CODEC_VREF
27
40
SENSE C
33
AVSS1
AVSS2
26
42
1
For ESD 10/11
2
10mil
C1855
1
1
C1856
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
R1547
20K_0402_1%
3
5
6
G1
G2
2
C1854
220P_0402_50V8J
1
C1853
220P_0402_50V8J
ALC888S-VC_LQFP48_7x7
888VC@
1
R1550
2
0_0805_5%
1
R1551
2
0_0805_5%
1
R1553
2
0_0805_5%
1
R1554
2
0_0805_5%
1
R1555
2
0_0805_5%
1
R1556
2
0_0805_5%
0_0402_5%
<18> SPDIF_HDMI
AGND
DMIC_DATA
1
2
R1557 @
SPDIF_HDMI 1
2
R1558 888VC@
HDA_GPIO0
0_0402_5%
DMIC_DATA
1888VB@ 2
R1559
DMIC_CLK
1
2
R1560 KAL90@
HDA_GPIO3
0_0402_5%
Issued Date
C
@
1
2
3
4
ACES_88266-04001
CONN@
D30
SM05T1G_SOT23-3
0_0402_5%
GND
D
GNDA
GND
GNDA
FBMA-L10-160808-301LMT_0603
Compal Electronics, Inc.
Compal Secret Data
2008/11/10
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
1
2
3
4
DMIC_CLK R1541 KAL90@ 0_0603_5%
DMIC_CLK_R
DMIC_DATA
DMIC_DATA_R
R1542 KAL90@ 0_0603_5%
10mil
Security Classification
A
1
DMIC_CLK
0_0402_5%
2 C1850
22P_0402_50V8J
2
1
0_0402_5%
32
JDREF
GPIO1/DMIC_DATA
DVSS
DMIC_DATA_R
R1537 KALH0@ 0_0603_5%
@
29
28
SDATA_OUT
T38
37
MIC1_VREFO_L
2
3
13
34
2 SPDIF_R 48
0_0402_5%
4
7
8
31
SYNC
1
R1539
2
6
LINE2_VREFO
DGND
PORT-E (PIN 14, 15)
20K
EAPD
BITCLK
MIC1_R
1
R1538 @
For EMI
44
DMIC_CLK_R
HP_RIGHT <39>
DMIC_CLK_268
43
15mil
HP_LEFT <39>
PAD
46
R1535
2.2K_0402_5%
KALH0@
AMP_RIGHT <39>
2
<39> LINEIN_PLUG#
<39> MIC_PLUG#
R1543 1
R1544 2
39.2K
SENSE B
HDA_GPIO0
HDA_GPIO3
SENSE_A
LFE
CD_GND
MIC1_L
5
<26> HDA_SDOUT_AUDIO
Place close to Codec
CD_R
22
10
<26> HDA_SYNC_AUDIO
CENTER
21
11
<26> HDA_RST_AUDIO#
3
CD_L
AMP_LEFT <39>
1
<39>
2
3
18
G1
G2
ACES_88266-02001
CONN@
9
FRONT_L
LINE2-R
24
3
4
+1.5VS
MIC2_VREFO
LINE2-L
MIC2_C_L
1
2
C1845 KALH0@ 4.7U_0603_6.3V6M
MIC2_C_R
1
2
C1846 KALH0@ 4.7U_0603_6.3V6M
LINE_L
LINE_C_L
1
2
C1847
4.7U_0603_6.3V6M
LINE_R
LINE_C_R
1
2
C1848
4.7U_0603_6.3V6M
1
2
C1844
15
R49
Sense Pin
1
C1843
14
DMIC_CLK_R 2
<39>
1
U41
DVDD
2
DVDD_IO
2
AVDD1
2
L48
MBK1608121YZF_0603
1
2
@
+1.5VS_DVDD
1
1
2
0.1U_0402_16V4Z
10U_0805_10V4Z
2
2
38
C1841
10U_0805_10V4Z
40mil
25
+VDDA
0.1U_0402_16V4Z
1
1
C1842
AVDD2
L49 1
2
FBM-L11-160808-800LMT_0603
10mil
JP24
DMIC_DATA_R
DMIC_CLK_R
2
0.1U_0402_16V4Z
2
2
10U_0805_10V4Z
+AVDD_HDA
ANALOG MIC
+3VS
R1534
0_0603_5%
2
2
R1533
10K_0402_5%
+3VS_DVDD
1
2
1U_0402_6.3V6K
Q103
2
B
2
SB_SPKR
2
BOM Option
ALC268
ALC888S-VB
ALC888S-VC
MONO_IN
1U_0402_6.3V6K
1
2
R1531
1.3K_0402_1%
1
1
<27>
R1530
4.7U_0805_10V4Z
0.01U_0402_16V7K
1
2
1
1
3
2
1U_0402_6.3V6K
C1838
1
C1836
1
2
1
C1837
1
BEEP#
1
<35>
2
C1835
4.75V
C1834
2
1
C
+VDDA
1
4
2
1
1
60mil
L45 1
2
KC FBM-L11-201209-221LMAT_0805
E
F
Title
HD Audio Codec ALC888S-VC
Size
B
Document Number
Rev
0.2
kAL90KALH0
Date:
Wednesday, December 10, 2008
G
Sheet
38
H
of
52
4
B
C
D
2
1
C1871
1U_0603_10V4Z
2
1
D
1
C1873 S
3
R1574
100K_0402_1%
2
12
14
1
VOL_AMP
2
0.01U_0402_16V7K
2 EC_MUTE
G
Q104
2N7002_SOT23
25
2
1
3
1
VDD
20
10
19
HPOUT_R
HPOUT_L
+5VAMP
+5VAMP
/SD
HP_PLUG#
VSS
CP+
CP-
GND
PGND
PGND
CGND
GND
BIAS
15
16
1
2
23
7
13
29
C1872
1U_0603_10V4Z
R1572
100K_0402_5%
R1573
100K_0402_5%
Q105
AO3413_SOT23-3
2
SPDIF_PLUG#
2
C1874
APA2057A_TSSOP28
2.2U_0603_10V6K
Q44B
2N7002DW-T/R7_SOT363-6
5
Q44A
2N7002DW-T/R7_SOT363-6
2
S/PDIF Out JACK
LINE Out/Headphone Out
D33
PJDLC05_SOT23-3
+5VSPDIF
20mil
Gain= 10dB
C1875
R1575
56.2_0603_1%
HPOUT_L 1
HPOUT_L_1 1
2
L51
HPOUT_R 1
HPOUT_R_1 1
2
L50
R1576
56.2_0603_1%
2
2
D63
PJDLC05_SOT23-3
@
C1876
1
For ESD Protect
330P_0402_50V7K 330P_0402_50V7K
1
1
HPOUT_L_2
2
FBM-11-160808-700T_0603
HPOUT_R_2
2
FBM-11-160808-700T_0603
1
2
6
3
SPDIF_PLUG#
<38>
5
4
7
8
10
SPDIF
SPDIF
+5VSPDIF
1
C1877
100P_0402_50V8J
2
JHP1
2
2
HP_PLUG# <38>
3
CVSS
BEEP
1
EC_MUTE <35>
PVDD
PVDD
17
18
INR_H
INL_H
4
28
HP_R
HP_L
HP EN
For ESD 10/11
1
1
R1571
43K_0402_1%
26
SPKL+
SPKL-
3
VOL_AMP
39K_0402_5%
8
9
CONN@
2
2
4
6
LOUT+
LOUT-
5
6
C1866
220P_0402_50V8K
1
2
C1867
1
220P_0402_50V8K
2
C1868
220P_0402_50V8K
2
@
6 1
24
HP_RIGHT_R
39K_0402_5% HP_LEFT_R
/AMP EN
@
G1
G2
ACES_88266-04001
1
2
1
2 100K_0402_5%
2
SPKR+
SPKR-
2
R1568 1
HP_RIGHT_C 1
2
4.7U_0603_6.3V6M
R1569
HP_LEFT_C
2
1
4.7U_0603_6.3V6M
R1570
22
21
1
2
3
4
1
27
D31
SM05T1G_SOT23-3
2
1
<38> HP_LEFT
2 100K_0402_5%
ROUT+
ROUT-
3
+5VAMP
HP_RIGHT
1
C1869
HP_LEFT
1
C1870
<38> HP_RIGHT
R1567 1
INR_A
INL_A
1
2
3
4
1 C1865
220P_0402_50V8K
D32
SM05T1G_SOT23-3
1
HPF Fc = 154Hz
+5VAMP
3
5
SPK_L+
SPK_LSPK_R+
SPK_R-
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
3
2.2K_0402_5%
2
2
2.2K_0402_5%
HVDD
CVDD
1
1
2
2
2
2
D
1
U42
JP14
R1561 1
R1562 1
R1563 1
R1564 1
S
2 AMP_RIGHT_C
1U_0402_6.3V6K
2 AMP_LEFT_C
1U_0402_6.3V6K
SPKL+
SPKLSPKR+
SPKR-
G
AMP_RIGHT_C-1
1
C1862
AMP_LEFT_C-1
1
2
1
C1863
C1864
0.47U_0603_16V4Z
R1566
R1565
<38> AMP_LEFT
11
C1858
0.1U_0402_16V4Z
2
C1861
0.47U_0603_16V4Z
1
2
<38> AMP_RIGHT
C1859
C1860
0.1U_0402_16V4Z
2
2
4.7U_0805_10V4Z
20mil
1
1
1
2
1
3
W=40mil
+3VS
E
Int. Speaker Conn.
+5VAMP
2
A
9
2
SINGA_2SJ-E373-T01
CONN@
<38> LINEIN_PLUG#
1
LINE-IN JACK
JLINE1
8
7
D64
PJDLC05_SOT23-3
KAL90@
<38>
LINE_L
1
For ESD
I/O status:
a. input/output mount 75 ohm
b. input only mount 1K ohm
MIC1_L
1
2
R1582
75_0603_1%
SINGA_2SJ-E351-S03
C1879
220P_0402_50V7K
2 KAL90@
(HDA Jack)
CONN@
MIC JACK
MIC1_L_1
1
2
L55
FBM-11-160808-700T_0603
1
C1880
220P_0402_50V7K
4
JMIC1
MIC1_VREFO_R
8
7
R1580
2.2K_0402_5%
5
4
MIC1_R_R
3
6
2
1
MIC1_L_R
2
<38>
1
3
1
MIC1_R
R1579
2.2K_0402_5%
L54
FBM-11-160808-700T_0603
MIC1_R_1 1
2
2
<38>
LINE_L_R
3
3
6
2
1
<38> MIC_PLUG#
MIC1_VREFO_L
R1581
75_0603_1%
1
2
LINE_R_R
1
KAL90@
LINE_L_1 1
2
L53
FBM-11-160808-700T_06031
KAL90@
C1878
220P_0402_50V7K
2
2
2
R1578
75_0603_1%
4
3
LINE_R
LINEIN_PLUG# 5
2
<38>
R1577 KAL90@
L52 KAL90@
75_0603_1%
FBM-11-160808-700T_0603
LINE_R_1 1
1
2
2
3
1
SINGA_2SJ-E351-S01
C1881
2
D65
2
CONN@
PJDLC05_SOT23-3
4
(HDA Jack)
1
220P_0402_50V7K
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Amplifier & Audio Jack
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Tuesday, January 06, 2009
39
Sheet
E
of
52
FAN1 Conn
+5VS
+5VS
10U_0805_10V4Z
2
1
C2124
1
U60
H1
H_3P2
H5
H_3P2
H6
H_3P2
H7
H_3P2
H8
H_3P2
1
1
1
@
H12
H_4P2
1
1
@
H11
H_4P2
@
@
@
H13
H_3P7N
1
1
C2126
1000P_0402_50V7K
1
2
@
H10
H_4P2
1
+3VS
@
H9
H_4P2
1
2
1
BAS16_SOT23-3
C2125
10U_0805_10V4Z
1
2
R1791
10K_0402_5%
@
@ H22
H21
H_3P2
1
1
H26
H_3P2
1
H_7P0 H25
H_3P2 H_3P2
1
H23
H_3P2
1
H_3P2
1
H20
H_3P2
1
H19
H_3P2
1
1
2
3
@
H18
H_3P2
1
@
@
@
@
@
@
@
@
@
@
ACES_85205-03001
@ FD3
FD4
1
FD2 @
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
@
@
@
@
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
@
1
@ FD1
H33
H34
H_10P0X6P0N H_5P5X4P3N
1
H29
H30
H_4P7X3P7N H_5P1X4P1N
1
CONN@
1
C2127
1000P_0402_50V7K
@
H17
H_3P2
1
<35> FAN_SPEED1
@
JP27
1
+VCC_FAN1
1
40mil
2
H4
H_3P2
1
2
1
1
APL5605KI-TRL SOP 8P
C60
1
H3
H_3P2
D54
1
0.1U_0402_16V4Z
D53
1SS355_SOD323-2
8
7
6
5
1
1
GND
GND
GND
GND
2
+VCC_FAN1
2 R41
1
300_0402_5%
VEN
VIN
VO
VSET
2
<35> EN_DFAN1
1
2
3
4
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
FAN & COVER LIGHT& Screw Hole
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Thursday, November 20, 2008
Sheet
40
of
52
A
B
C
10U_0805_10V4Z
2
2
10U_0805_10V4Z
C2134
1
2
10U_0805_10V4Z
2
4
2
C2136
1
2
R1793
470_0603_5%
1
R1794
470_0603_5%
10U_0805_10V4Z
2
2
SI4800BDY-T1-E3_SO8
1U_0603_10V4Z
SYSON#
<33,34> SYSON#
1
Q31A
3
1
C2133
10U_0805_10V4Z
2
2
SI4800BDY-T1-E3_SO8
1U_0603_10V4Z
3
2
1
1 C2135
6
1
R1792
100K_0402_5%
5
6
7
8
3 1
C2131
1
1
1
U62
3
2
1
1 C2132
+5VALW
+3V
4
U61
C2130
+3VALW
+5VS
5
6
7
8
E
+3VALW TO +3V_SB(ICH8M AUX Power)
+5VALW TO +5VS
+5VALW
D
2N7002DW-T/R7_SOT363-6
1
SBPWR_EN#
R1797
100K_0402_5%
C2138
2
1
C2137
2
1
5
3V_GATE
2
1
R1796
200K_0402_5%
+VSB
4
SUSP
6
5
4
6
1
<34,35,47> SYSON
Q39B
2N7002DW-T/R7_SOT363-6
Q30B
2N7002DW-T/R7_SOT363-6
5VS_GATE
2
1
R1795
200K_0402_5%
+VSB
SYSON
Q39A
SUSP
SBPWR_EN#
Q30A
0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6
0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6
+5VALW
2
1
1
2
2
+3VS
SUSP
SUSP
3
@
@
1
0_0402_5%
4
D
@
VGA_SUSP
2
R1402
2
2
2
R1405
2 SUSP
G
Q125
2N7002_SOT23
S
5VS_GATE
2N7002DW-T/R7_SOT363-6
1
D
5
<34,35,37,50> SUSP#
R1800
10K_0402_5%
VGA_SUSP
S
3
10U_0805_10V4Z
2
2
1U_0603_10V4Z
R1799
470_0603_5%
2
1
Q31B
R1404
4.7K_0402_5%
1
2
C2140
1
1
4
10U_0805_10V4Z
SI4800BDY-T1-E3_SO8
2
2
10U_0805_10V4Z
2
R1403
4.7K_0402_5%
2
C2142
3
2
1
1 C2139
1 1
C2141
5
6
7
8
1
<37,48>
+3VS
U63
1
+5VS
3
+3VALW TO +3VS
+3VALW
1
R1798
100K_0402_5%
1 SUSP
0_0402_5%
@
2
G
Q128
2N7002_SOT23
+5VALW
2
<50> NVVDD_PWRGD
+1.5V to +1.5VS
PM@
1
PM@
SUSP
2
2
1
1
1
4
D
@
2 SYSON#
G
Q131
2N7002_SOT23
@
3
S
@
2 SYSON#
G
Q132
2N7002_SOT23
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
3
2N7002_SOT23
Q137
@
1
1
S
3
1
2
3
S
S
R1812
470_0603_5%
D
2 SUSP
G
Q130
2N7002_SOT23
3
D
@
2 SUSP
G
Q129
2N7002_SOT23
R1811
470_0603_5%
1
1
1
R1810
470_0603_5%
1
S
3
C2152
1
2
1 1
3
2
+1.5V
D
2 SUSP
G
Q127
2N7002_SOT23
3
3
+1.8V
D
2
G
<27,35,42,43,46> ACIN
+0.9VS
1
1
D
S
S
2N7002_SOT23
Q136
PM@
R1809
470_0603_5%
1
R1807
470_0603_5%
4
R1804
100K_0402_5%
SUSP
R1825
2.2M_0402_1%
@
D
2
G
+1.05VS
2
+1.5VS
5
0.1U_0603_25V7K
2
Q19A
2N7002DW-T/R7_SOT363-6
R1824
2.2M_0402_1%
PM@
<27,35,42,43,46> ACIN
Q19B
2N7002DW-T/R7_SOT363-6
1.5VS_GATE
2
1
R1806
510K_0402_5%
D
2
G
Q126
S
2N7002_SOT23
<35,47> SBPWR_EN
2
+VSB
2
1
VGA_SUSP
C2151
0.1U_0603_25V7K
2
Q14A
2N7002DW-T/R7_SOT363-6
PM@
VGA_SUSP 2
5
SBPWR_EN#
<28> SBPWR_EN#
R1803
470_0603_5%
4
1
6
PM@
3
1
1
C2146
2 C2145
1
10U_0805_10V4Z
2
2
1U_0603_10V4Z
SI4800BDY-T1-E3_SO8
2
910K_0402_5%~D
3
C2150
1
10U_0805_10V4Z
2
2
10U_0805_10V4Z
Q14B
2N7002DW-T/R7_SOT363-6
1.8VS_GATE
2
1
3
PM@
PM@
R1805
1
C2149
1
PM@
5
6
7
8
6
+VSB
PM@
SI4856/AO4430
PM@
R1802
470_0603_5%
10U_0805_10V4Z
2
2
1U_0603_10V4Z
SI4856ADY_SO8
10U_0805_10V4Z
2
2
10U_0805_10V4Z
C2144
1
1
C2143
1
2
1
2
3
4
3
C2148
1
S
S
S
G
4
C2147
1
D
D
D
D
2
U65
U64
8
7
6
5
R1801
100K_0402_5%
+1.5VS
1
+1.5V
4
+1.8VS
1
+1.8V to +1.8VS
+1.8V
B
C
D
Title
DC Interface
Size
B
Date:
Document Number
Rev
0.2
kAL90KALH0
Wednesday, December 24, 2008
Sheet
E
41
of
52
5
4
3
2
1
Enlightener LED
+5VALW
ON/OFF LED LEFT
+5VALW
2
R1813
300_0402_5%
(BLUE)
R1826
300_0402_5%
KAL90@
1
1
D
+5VALW
2
2
+5VALW
R1814
1
KAL90@
R1816
1
KAL90@
LED10
HT-191NBQA_BLUE_0603
KAL90@
1
ACIN#
(BLUE)
LED3
KAL90@
LED5
HT-191NBQA_BLUE_0603
KAL90@
1
ON/OFF LED RIGHT
(BLUE)
2
(BLUE)
LED4
R1815
2
2
220_0402_5%
2
4
453_0402_1%
1
A
3
PWR_LED#
+5VALW
PWR_SUSP_LED#
+5VALW
1
KAL90@
R1817
1
KAL90@
2
2
220_0402_5%
2
4
453_0402_1%
(AMB)
HT-297UD/CB _BLUE/AMB_0603
KAL90@
(AMB)
ACIN#
B
R1818
<37>
5
6
+5VALW
LED11 KALH0@
+5VALW
1
KAL90@
R1819
1
KAL90@
2
2
220_0402_5%
B
1
2
4
453_0402_1%
A
3
(AMB)
HT-297UD/CB _BLUE/AMB_0603
KAL90@
PWR_LED#
2
UD
+5VALW
3
R1843 KALH0@
453_0402_1%
1
2
2
R1844 KALH0@
220_0402_5%
1
2
1
2
100P_0402_50V8J
PWR_LED#
C2155 1 @ 2
100P_0402_50V8J
ON/OFFBTN#
C2160 1 @ 2
100P_0402_50V8J
NUM_LED#
C2162 1
2
100P_0402_50V8J
CAPS_LED#
C2167 1 @ 2
100P_0402_50V8J
MEDIA_LED#
C2165 1 @ 2
100P_0402_50V8J
PWR_LED#
1
NB
C2158 1
PWR_SUSP_LED#
@
HT-210UD/NB_AMB/BLUE
1
1
C
FOR EMI
(BLUE)
LED9
HT-191NBQA_BLUE_0603
KAL90@
NUM_LED#
PWR_SUSP_LED#
@
LED8
HT-191NBQA_BLUE_0603
KAL90@
NUM_LED#
PWR_LED#
PWR_SUSP_LED#
PWR_SUSP_LED#
2
1
2
R1842 KALH0@
220_0402_5%
1
2
LED12 KALH0@
R1823
150_0402_1%
KAL90@
2
1
2
LED7
HT-191NBQA_BLUE_0603
KAL90@
1
NB
(BLUE)
R1822
150_0402_1%
KAL90@
MEDIA_LED#
R1839 KALH0@
453_0402_1%
1
2
(AMB)
HT-210UD/NB_AMB/BLUE
+5VS
2
2
2
1
@
3
1
CAPS_LED
(BLUE)
R1821
453_0402_1%
KAL90@
<36>
LED6
ON/OFFBTN#
+5VALW
R1820
10K_0402_5%
PWR_SUSP_LED#
ON/OFF LED DOWN
UD
+5VS
D
<36>
(BLUE)
2
NUM_LED
PWR_LED#
PWR_SUSP_LED#
1
4
(BLUE)
PWR_LED#
KAL90@
ON/OFFBTN#
+5VS
A
3
ON/OFF Button
3
MEDIA_LED
1
HT-297UD/CB _BLUE/AMB_0603
SW3
EVQPLHA15_4P
C
B
CAPS_LED#
<35,36>
CAPS_LED#
<35>
6
PWR_LED#
Q133A
2N7002DW-T/R7_SOT363-6
B
D57
B
2
<35> PWR_LED
D58
1
R1831
2
2
3
D56
ON/OFFBTN#
ACIN#
2
3
NUM_LED#
2
3
PWR_SUSP_LED#
D55
CAPS_LED#
1
MEDIA_LED#
3
PWR_LED#
2
10K_0402_5%
PJSOT24C_3P_C/A_SOT-23
Q133B
2N7002DW-T/R7_SOT363-6
KAL90@
5
<35> PWR_SUSP_LED
R1830
ACIN#
1
D
2
A
<30>
5IN1_LED#
SATA_LED#
6
4
3
5
<26> SATA_LED#
+3VS
Q134A
2N7002DW-T/R7_SOT363-6
1
MEDIA_LED#
Q134B
2N7002DW-T/R7_SOT363-6
2
G
ACIN
<27,35,41,43,46>
3
Q135
KAL90@
2N7002_SOT23 S
+3VS
10K_0402_5%
D4 USE
PJSOT24C 3P C/A SOT-23
SCA00000E00
24V
2
D1 D2 D3 USE PANJIT PJMBZ6V8
SCA00000I00
6.8V
A
MEDIA_LED#
<36>
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
4
1
KAL90@
PJMBZ6V8_3P_C/A_SOT-23
3
PJMBZ6V8_3P_C/A_SOT-23
1
1
1
1
PWR_SUSP_LED#
PJMBZ6V8_3P_C/A_SOT-23
3
2
Title
PWR/B
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Wednesday, December 24, 2008
Sheet
1
42
of
52
A
B
C
D
1
1
PR1
1M_0402_1%
1
2
DC231000500
VIN
VIN
VS
1
2DC_IN_S2
@ PR2
10K_0402_5%
2
1
2
PR6
20K_0402_1%
PC6
0.1U_0603_25V7K
2
1
PR8
10K_0402_1%
1
2
PR123
1
2
1
2
2
3
-
2
PD3
GLZ4.3B_LL34-2
2
+
0
PU1A
LM358DT_SO8
PR7
10K_0402_1%
PR5
22K_0402_5%
1
2
8
2 1
P
1
G
2
PR209
10K_0402_1%
1
<27,35,41,42,46> ACIN
1
PC1
1000P_0402_50V7K
PR3
84.5K_0402_1%
PR4
0_0402_5%
1
2
4
1
2
1
PC4
100P_0402_50V8J
PC2
100P_0402_50V8J
2
PC3
1000P_0402_50V7K
2
PJP3
2
3
1
2
1
G
G
VIN
PL1
SMB3025500YA_2P
1
DC_IN_S1
1
1
<BOM Structure>
SINGA_2DC-G756I200
PC5
1000P_0402_50V7K
RTCVREF
0_0603_5%
MCVCC
PQ25
@ SI2301BDS-T1-E3_SOT23-3
PQ28
@ SI2301BDS-T1-E3_SOT23-3
3
3
Min.
H-->L 16.976V
L-->H 17.430V
1
D
3
S
1
2
G
D
Typ
17.525V
17.901V
2
Max.
17.728V
18.384V
2
PR122
@ 200K_0402_1%
2
@
Vin Dectector
RTCVREF
2
1
1
PR102
200K_0402_1%
1
G
2
G
D
1
D
S
S
+3VALWP
2
PQ45
@ 2N7002W-T/R7_SOT323-3
2
SPOK
G
@
PQ46
2N7002W-T/R7_SOT323-3
<44,45>
PJ2
S
2
3
+3VALWP
PJ3
2
1
1
+3VALW
2
+1.5VP
JUMP_43X118
PJ4
VIN
2
+5VALWP
2
1
1
+1.5V
JUMP_43X118
PJ5
2
1
1
+5VALW
2
+0.9VSP
2
1
1
+0.9VS
3
3
JUMP_43X79
2
JUMP_43X118
PD4
LL4148_LL34-2
2
PR11
200_0603_5%
1
2
N1
3
+VSB
+1.8VP
2
2
+1.8V
1
1
JUMP_43X118
PJ8
2
+1.05VSP
1
VS
PJ17
2
1
1
+1.05VS
+1.8VP
2
2
JUMP_43X118
+1.8V
1
1
JUMP_43X118
<37> 51ON#
PC8
0.1U_0603_25V7K
2
-
1
1
OUT
IN
GND
PC9
10U_0805_10V4Z
1
2
2
2
2
+1.1VS
PJ20
1
1
+VGA_CORE
+VGA_COREP
2
JUMP_43X118
2
1
1
+VGA_CORE
JUMP_43X118
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
PC10
1U_0805_25V4Z
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
1
JUMP_43X79
2
N2
1
3
@
Title
DCIN & DETECTOR
2
3.3V
1
PR16
560_0603_5%
1
2
2
+CHGRTC
PR15
560_0603_5%
1
2
1
+1.05VS
PJ9
2
ML1220T13RE
45@
PR14
200_0603_5%
PU2
G920AT24U_SOT89-3
+1.1VSP
1
1
+RTCBATT
+RTCBATT
+VGA_COREP
RTCVREF
2
JUMP_43X118
+
PBJ1
2
4
PJ18
PJ16
2
+1.05VSP
2
PC7
0.22U_0603_25V7K
2
PR13
22K_0402_1%
1
2
2
PR12
100K_0402_1%
1
1
1
CHGRTCP
1
1
PR10
68_1206_5%
2
PR9
PQ1
68_1206_5%
TP0610K-T1-E3_SOT23-3
PJ7
2
JUMP_43X39
1
1
BATT+
PJ6
2
+VSBP
1
PD5
LL4148_LL34-2
2
1
B
C
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Tuesday, December 09, 2008
D
Sheet
43
of
52
A
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 96 degree C
Recovery at 60 degree C
VL
VL
VL
2
VMB
PR17
47K_0402_1%
1
PR18
47K_0402_1%
1
2
TM_REF1
2
-
2
1
2
LL4148_LL34-2
3
PU3A
LM393DG_SO8
VL
PR25
100K_0402_1%
2
2
PR26
1K_0402_1%
PR23
100K_0402_1%
2
1
1
1
2
PC15
1000P_0402_50V7K
1
2
1
+3VALWP
PR22
15.4K_0402_1%
PR24
6.49K_0402_1%
2
1
2
1
PR21
100_0402_1%
1
PC14
0.22U_0603_16V7K
2
2
PR20
100_0402_1%
1
PD6
1
O
4
SUYIN_250133MR007G115ZL
+
P
3
<26,45>
PQ2
DTC115EUA_SC70-3
8
PR19
13.7K_0402_1%
1
2
G
PC13
0.01U_0402_25V7K
1
MAINPWON
1
PC11
0.1U_0603_25V7K
1
PH1
100K_0603_1%_TH11-4H104FT
2
PC12
1000P_0402_50V7K
2
EC_SMCA
EC_SMDA
BATT+
1
BATT_S1
1
1
2
3
4
5
6
7
2
1
2
3
4
5
6
7
2
PJP2
1
PL2
SMB3025500YA_2P
1
2
1
2
2
BATT_TEMP <35>
PH2 near main Battery CONN :
BAT. thermal protection at 79 degree C
Recovery at 47 degree C
EC_SMB_CK1 <35,36>
EC_SMB_DA1 <35,36>
2
VL
@ PR27
47K_0402_1%
1
@ PR28
47K_0402_1%
1
2
PQ3
TP0610K-T1-E3_SOT23-3
@ PH2
100K_0603_1%_TH11-4H104FT
2
8
O
-
4
@ PR32
15.4K_0402_1%
7
3
PU3B
LM393DG_SO8
2
2
@ PC18
0.22U_0603_16V7K
@ PD7
LL4148_LL34-2
2
1
P
+
1
6
G
5
TM_REF1
1
@
2
1
2
@ PR30
13.7K_0402_1%
1
2
PC17
0.1U_0603_25V7K
2
PR31
22K_0402_1%
1
2
VL
2
3
@
VL
+VSBP
1
2
1
1
PR29
100K_0402_1%
PC16
0.22U_1206_25V7K
3
B+
1
VL
2
1
PQ4
2
G
1
PR34
0_0402_5%
2
D
3
1
<43,45> SPOK
PC19
0.1U_0402_16V7K
1
PR33
100K_0402_1%
S
2N7002W-T/R7_SOT323-3
<BOM Structure>
@
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
BATTERY CONN / OTP
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
D
Sheet
44
of
52
5
4
3
2
1
ISL6237_B+
ISL6237_B+
PR35
0_0805_5%
1
2
PJ10
1
1
3
2
1
PHASE1
16
LX5
LGATE1
18
DL5
PR40 0_0603_5%
2
<BOM 1
Structure>
PHASE2
3
2
1
25
4
1
PC32
0.1U_0603_25V7K
PQ8
AO4712_SO8
2
LGATE2
FB3
30
OUT2
32
REFIN2
@ PR42
10K_0402_1%
1
VL
PGND
22
OUT1
10
FB1
11
BYP
9
SKIP
29
2VREF_ISL6237
1
PC36
1
REF
8
LDOREFIN
PR46
100K_0402_1%
1
2
POK1
13
@ PR44
2
5
GND
12
ILIM2
31
ILIM2
PC25
2200P_0402_50V7K
2
1
VL
PR48
330K_0402_1%
2
1
2
<43,44>
B
1
PR49
330K_0402_1%
1
PU4
ISL6237IRZ-T_QFN32_5X5
PR53
0_0402_5%
2
+5VALWP Ipeak=8.444A ; Imax=5.91A
Choke DCRmax=60m ohm, DCRtyp=54m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Iocp=Ilimit+Delta I/2
=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)
2VREF_ISL6237
PC143
1U_0603_10V6K
1
2
2VREF_ISL6237
2
ILIM1
@ PC39
0.047U_0402_16V7K
PQ35
TP0610K-T1-E3_SOT23-3
2
0_0402_5%
1
0_0402_5%
2
SPOK
ILM1
21
2
PR51
0_0402_5%
1
2
2
PC38
0.047U_0402_16V7-K
1
1
TON
EN2
2
27
NC
EN1
1
@ PR55
47K_0402_5%
1
2
1
PR54
0_0402_5%
2
3
EN_LDO
1
1
2
2
28
@ PR50
0_0402_5%
PR52
806K_0603_1%
A
1
A
POK2
14
PC37
0.22U_0603_25V7K
VL
<26,44> MAINPWON
NC
2
4
PR47
200K_0402_5%
1
2
PD12
1SS355_SOD323-2
+ PC35
C
150U_D2E_6.3VM_R18
0.22U_0603_10V7K
20
PD8
GLZ5.1B_LL34-2
1
2
1
2
FB5
PR45
1
1
B
+3.3VALWP Ipeak=8.444A ; Imax=5.91A
Choke DCRmax=60m ohm, DCRtyp=54m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
VS
Iocp=Ilimit+Delta I/2
=10.134A ~ 11.967A
Delta I=1.934A (Freq=300KHz)
2
2
BST5A
1
DH5
17
PR41
63.4K_0402_1%
3
7
15
BOOT1
PR43
10K_0402_1%
1
2
23
UGATE1
PR39
4.7_1206_5%
2
1
DL3
19
PL4
8.2UH +-20% FDV0630-8R2M=P3 3.7A
2
1
PC34
680P_0402_50V7K
2
1
BOOT2
PC29
1U_0603_10V6K
1
2
PVCC
5
6
7
8
UGATE2
24
+5VALWP
2
26
LDO
DH3
PR37
2
1 BST3A
0_0603_5%
<BOM Structure>
PC31
0.1U_0603_25V7K
LX3
PQ6
AO4466_SO8
4
PC28
4.7U_0603_6.3V6M
2
1
<BOM Structure>
PC27
1U_0603_10V6K
1
2
TP
VCC
VIN
33
1
2
3
PC33
680P_0402_50V7K
2
6
1
1
4
2
2
C
1
2
PR38
0_0402_5%
+
2
PC30
330U_D2E_6.3VM_R25M
PQ7
AO4712_SO8
2
1
PR36
4.7_1206_5%
1
1
PC26
0.1U_0603_25V7K
PC24
4.7U_1206_25V6K
2
1
5
6
7
8
8
7
6
5
PL3
8.2UH +-20% FDV0630-8R2M=P3 3.7A
1
2
+3VALWP
VL
PQ5
AO4466_SO8
4
1
2
3
PC20
4.7U_1206_25V6K
2
1
<BOM Structure>
PC23
4.7U_1206_25V6K
2
1
D
JUMP_43X118
8
7
6
5
2
PC22
2200P_0402_50V7K
2
1
2
PC21
4.7U_1206_25V6K
2
1
D
B+
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
+5VALWP/+3VALWP
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
45
of
52
A
B
PH
25
LX_CHG
PD10
2
ACSET
ACOP
PC54
1U_0603_10V6K
DL_CHG
LODRV
23
PGND
22
LEARN
21
CELLS
20
CELLS
9
AGND
1
ACOFF
2
RTCVREF
11
SRP
19
SE_CHG+
SRN
18
SE_CHG-
BAT
17
TP
29
1
12
VADJ
2
13
/BATDRV
SRSET
14
15
PR74
340K_0402_1%
2
2
1
1
1
1
<35> CALIBRATE#
3
2
PR81
100K_0402_1%
PQ18
2
G
<35> FSTCHG
1
S
3
S
S
2N7002W-T/R7_SOT323-3
PR86
100K_0402_1%
2
1
D
D
4
2
4
CHGEN#
D
2N7002W-T/R7_SOT323-3
3
PC144
1000P_0402_50V7K
1
PQ19
2
G
1
1
2
@ PR177
4.3K_0402_5%
24751_VREF
1
2
PR82
100K_0402_1%
S
VADJ
2
3
S
1
2
G
1
1
3
PR80
0_0402_5%
1
2
PQ17
SI2301BDS-T1-E3_SOT23-3
2N7002W-T/R7_SOT323-3
REGN
<27,35,41,42,43>
D
@ PQ16
2N7002W-T/R7_SOT323-3
2
D
S
ACIN
ACGOOD#
PR84
221K_0402_1%
2
1
3
PQ36
2
G
PR78
887K_0402_1%
2
PR180
200K_0402_1%
2
1
1
D
24751_VREF
2
PQ15_GATE
2N7002W-T/R7_SOT323-3
3
PC66
0.01U_0402_25V7K
2
2
PQ37
2
G
@ PR176
0_0402_5%
1
<35>
1
ACSET
PC163
0.1U_0402_16V7K
ACOFF 1
2
ADP_I
G
PR79
105K_0402_1%
1
4
1
-
6
PR181
340K_0402_1%
2
1
8
5
PR179
100K_0402_1%
2
1
PR76
499K_0402_1%
@ PR75
100K_0402_1%
24751_VREF
D
+
24751_VREF
3
S
G
PU1B
LM358DT_SO8
7 0
P
PR77
10K_0402_1%
1
2
24751_VREF
2
Per cell=4.5V
@PC63
@PC63
0.01U_0402_25V7K
2
2
2
BATT-OVP=0.1112*VMB
PC64
100P_0402_50V8J
1
1
LI-3S :13.5V----BATT-OVP=1.5012V
PC65
0.01U_0402_25V7K
BATT-OVP=0.1112*VMB
IREF <35>
For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
Icharge=(Vsrset/Vdac)*(0.1/PR62)
IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge
IREF=0.7748*Icharge
PR73
100K_0402_1%
BQ24751ARHDR_QFN28_5X5
1
VS
LI-4S :18.0V----BATT-OVP=2.001V
PR83
64.9K_0402_1%
24751_VREF 1
2
SRSET
PR72
10_0603_5%
1
2
1
IADAPT
<35> BATT_OVP
16
BATDRV
PR71
17.4K_0402_1%
2
1
1
VMB
Vacset=3.3*(50K/(50K+64.9K))=1.436V
Icharge Setting
ICHG setting
ACGOOD
2
ACGOOD#
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A
PC61
0.1U_0603_25V7K
1
VADJ
1
ACSET
65W adapter R=(100K*100K)/(100K+100K)=50K
PQ20
2
G
@PC59
@PC59
0.1U_0603_25V7K
1
VDAC
2
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A
PR70
100K_0402_1%
2
PC62
0.1U_0603_25V7K
90W adapter
Vacset=3.3*(100K/(64.9K+100K))=2.001V
65W/90W#
2
PC58
0.1U_0603_25V7K
VREF
PC60
1U_0603_10V6K
1
CP point=Iadapter*85%
PR85
100K_0402_1%
2
<35>
1
3
24751_VREF 10
PR69
100K_0402_1%
1
2PQ15_GATE
2
CP Point Setting
<35>
1
PC57
0.1U_0402_16V7K
1
2
1
OVPSET
24751_VREF
PQ15
SI2301BDS-T1-E3_SOT23-3
Fsw : 300KHz
PC55
P
C55
680P_0402_50V7K
2
3
8
PR68
54.9K_0402_1%
Input UVP : 17.26V
2
PQ13
AO4466_SO8
4
1
<35>
Cells selector
Input OVP : 22.3V
BATT+
3
<BOM Structure>
1
OVPSET
2
@ PQ14
2N7002W-T/R7_SOT323-3
2
3S/4S#
G
S
3
PR62 0.02_1206_1%
4
2
24
1
7
PR67
340K_0402_1%
1
@ PR64
4.7_1206_5%
2
PC56
0.47U_0603_16V7K
1
2
2
PR66
0_0402_5%
1
2
1
1
D
6
REGN
CELLS
2
ACSET
PL5
10UH_PCMB104T-100MS_6A_20%
1
2
2
2
PR63
54.9K_0402_1%
1
LL4148_LL34-2
PC51
0.1U_0603_25V7K
REGN
2
4 Cell
1
1
ACDRV
ACDET
2
4
5
1
ACDRV
ACDET
1
DH_CHG
2
26
4
PC53
10U_1206_25V6M
HIDRV
1
ACN
ACP
/BATDRV
PQ11
AO4466_SO8
4
2
1
2
3
3
2
1
PR61
0_0603_5%
1
2
5
6
7
8
BTST
1
PQ12
SI4835DDY-T1-E3_SO8
PC52
10U_1206_25V6M
27
2
BTST
PR57
100K_0402_1%
1
2
PC48
0.1U_0603_25V7K
1
2
1
PVCC
5
6
7
8
28
PC40
0.01U_0402_25V7K
3
2
1
2
@PC49
@PC49
0.1U_0603_25V7K
ACN
ACP
PC42
4.7U_1206_25V6K
CHGEN
1
2
@ PR65
47K_0402_1%
3 Cell
VREF
CHG_B+
1
5
6
7
8
1
PVCC
PU5
1
1
1
2
2
2
PC47
0.1U_0603_25V7K
PR60
340K_0402_1%
PC50
2.2U_0805_25V6K
24751_VREF
GND
1
3
2
1
4
1
2
1
PR59
100K_0402_1%
2
PC45
0.01U_0402_25V7K
4
2
1
PC46
0.1U_0402_16V7K
1
2
Place close to back to back MOS
CELLS
2
CHGEN#
2
2
JUMP_43X118
PR174
3.3_1210_5%
2
PJ11
PR56
1
0.015_1206_1%
2
1
8
7
6
5
PC44
2200P_0402_25V7K
1
2
3
2
1
2
3
1
1
8
7
6
5
PR58
3.3_1210_5%
1
B+
PQ10
AO4407A_SO8
PC43
4.7U_1206_25V6K
VIN
D
@
PQ9
AO4407A_SO8
C
2N7002W-T/R7_SOT323-3
CP setting
A
Charger ADJ
PR78
PR84
4.0V
Calibrate#
L
@
@
4.1V
L
887K
221K
4.2V
H
@
@
B
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
CHARGER
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
D
Sheet
46
of
52
1
2
8
2
1
PR92
18.2K_0402_1%
1
GND_T
29
FB1
PGOOD2
28
PR98
3.3K_0402_5%
2
1
2
2
VIN2
3
VCC1
VCC2
4
5
VIN1
ISL6228_B+
PR97
22.6K_0402_1%
8
7
6
5
VO1
OCSET_1.05V
10
OCSET1
1.05V_EN
11
EN1
FB2
2
PQ21
AO4466_SO8
FB_1.8V-1
27
VO2
26
OCSET2
25
EN2
24
PHASE2
23
6228_1.8VO2
Vref=0.6V
OCSET_1.8V
2
1
1
PC86
1U_0402_6.3V6K
1
PQ24
FDS6670AS_NL_SO8
5
6
7
8
D
D
D
D
G
S
S
S
+5VALW
4
3
2
1
2
1
2
3
1
@ PR108
4.7_1206_5%
+1.8VP
1
+
2
@ PC89
680P_0402_50V7K
DCR 6m ohm(max)
LG_1.8V
2
PL12
1UH_FDV0630-1R0M-P3_10.3A_20%
PC88
330U_D2E_2.5VM
Cout ESR=15m ohm
Vo=0.6*((PR87+PR83)/PR83)=1.8V
1.8VP Ipeak=11.93A, Imax=8.351A
Csen=L/(Rocset*DCR)=1uF/(Rocset*6m ohm)=0.022uF
=>Rocset=7.575K, Choose 10K because of thermal factor
Iocp=(Rocset*10uA)/DCR=(10K*10uA)/(0.006*1.3)=12.82A
1.05V_EN
1
<35,41> SBPWR_EN
3
2
1
BOOT2
LX_1.8V
LG_1.05V
@ PR178
0_0402_5%
1
2
PR105
10K_0402_1%
UG_1.8V
PR109
PC87
0_0603_5%
0.1U_0402_16V7K
BST_1.8V 1
2
1
2
+5VALW
PC85
1U_0402_6.3V6K
22
21
PVCC2
20
LGATE2
19
PGND2
18
17
15
DCR 11.9m ohm(max)
Cout ESR=15m ohm
+1.05VSP
OCP Seting is same as ICL50
Vo=Vref*((PR80+PR82)/PR80)
Ipeak=14.02A, Imax=9.81A
Iocp=14.02*1.2=16.824A
Csen=L/(Rocset*DCR)
0.015U=1U/(Rocset*6m) Rocset=11.111K~11.8K
Iocp=(Rocset*10uA)/DCR
Iocp=(11K*10uA)/(6m ohm*1.3) =15.1A
UGATE2
PGND1
BOOT1
LGATE1
2
PC84
0.1U_0402_16V7K
PVCC1
S
S
S
1
2
3
1
2
PC83
@ 680P_0402_50V7K
3
PQ23
AO4466_SO8
4
16
PR106
0_0603_5%
1 2
1BST_1.05V14
PC82
0.022U_0402_16V7K
1
2
PC79
4.7U_1206_25V6K
UGATE1
4
1
G
2
2
13
<34,35,41> ISL6228_B+
2
PQ22
FDS6670AS_NL_SO8
UG_1.05V
SYSON
@ PC78
0.01U_0402_25V7K
1
2
8
7
6
5
PHASE1
1
PR103
0_0402_5%
1
2
2
+
12
2
PC80
330U_D2E_2.5VM
PL6
1UH +-20% FDV0630-1R0M=P3 10.3A
PR104
@ 4.7_1206_5%
D
D
D
D
1
1
LX_1.05V
2
1
1
2
3
1
1
PC81
4.7U_1206_25V6K
PU6
2
4
ISL6228HRTZ-T_QFN28_4X4
+1.05VSP
FB_1.8V
PR100
10K_0402_1%
1
2
5
6
7
8
PR101
11.8K_0402_1%
9
PC77
4.7U_1206_25V6K
2
1
2
PC75
0.015U_0402_16V7K
1
2
PC76
4.7U_1206_25V6K
2
1
ISL6228_B++
PC74
1000P_0402_50V7K
1
2
PR99
45.3K_0402_1%
1
2
1
6228_1.05VO1
1
PC69
0.1U_0603_25V7K
PC73
1000P_0402_50V7K
2
1
PR91
22K_0402_1%
2
7
PR96
11.8K_0402_1%
1
2
PGOOD1
FB_1.05V-1
+5VALW
PR90
10_0603_1%
2
1
1
2
PC71
1000P_0402_50V7K
PR94
59K_0402_1%
<BOM Structure>
PR95
45.3K_0402_1%
2
1
FB_1.05V
2
2
PR93
3.3K_0402_5%
1
2
1
PR89
10_0603_1%
2
1
ISL6228_B++
1
PC72
1000P_0402_50V7K
2
1
PR88
2.2_0603_1%
1
2
FSET2
ISL6228_B+
6
PJ12
JUMP_43X118
2 2
1 1
PC70
0.1U_0603_25V7K
D
PC68
1U_0402_6.3V6K
2
ISL6228_B++
1
B+
PJ15
JUMP_43X118
2 2
1 1
FSET1
B+
PR87
2.2_0603_1%
2
1
+5VALW
1
1
PC67
1U_0402_6.3V6K
2
C
1
B
2
A
<37,48> VS_ON
PR112
0_0402_5%
1
2
2
4
@PC94
@PC94
0.1U_0402_16V7K
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
1.8VP / 1.05VSP
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
D
Sheet
47
of
52
5
4
3
2
1
1
51117_B+
PR110
0_0402_5%
2
1
D2
D2
G1
S1
1
2
3
4
DL_1.5V
LX_1.5V
TRIP
11
V5DRV
10
DRVL
9
+1.5VP
1
+
+5VALW
PC95
330U_D2E_2.5VM
2
DL_1.5V
TPS51117RGYR_QFN14_3.5x3.5
1
PGOOD
DH_1.5V
12
2
6
13
LL
1
VFB
VFB=0.75V
DRVH
2
5
VBST
V5FILT
PGND
4
14
15
TP
1
EN_PSV
VOUT
2
PC98
1U_0603_10V6K
TON
3
2.2UH +-20% FDV0630-2R2M=P3 7.2A
PL8
1
2
PR113
PC93
0_0603_1%
0.1U_0603_25V7K
1
2BST_1.5V-1 1
2
BST_1.5V
PR115
17.8K_0402_1%
1
@ PC96
47P_0402_50V8J
1
2
2
8
PR114
300_0603_5%
1
2
PU7
GND
@ PC90
0.01U_0402_25V7K
7
2
+5VALW
C
G2
S2/D1
S2/D1
S2/D1
D
B+
AO4932_SO8
1
<37,47> VS_ON
8
7
6
5
2
PQ26
DH_1.5V
PR111
200K_0402_1%
1
2
PJ13
JUMP_43X118
2 2
1 1
PC91
4.7U_1206_25V6K
D
PC97
4.7U_0805_10V6K
C
1
PR116
10K_0402_1%
1
2
2
PR117
10K_0402_1%
+1.8V
PJ14
JUMP_43X79
2
1
1
VFB=0.75V
Vo=VFB*(1+PR87/PR88)=0.75*(1+4.02K/10K)=1.05V
Ton=200K
Fsw=400KHz
VIN
2
GND
VCNTL
6
NC
5
+3VALW
B
1
1
1
2
2
PU8
3
REFEN
NC
7
4
VOUT
NC
8
GND
9
2
2
PR118
1K_0402_1%
1
PC99
4.7U_0603_6.3V6M
PC100
1U_0402_6.3V6K
1
+0.9VSP
2
PR120
2N7002W-T/R7_SOT323-3
S <BOM Structure>
1K_0402_1%
2
3
D
2
PC103
0.1U_0402_16V7K
PQ27
2
G
PC101
0.1U_0402_16V7K
2
1
PR119
0_0402_5%
1
2
1
<37,41> SUSP
1
RT9173DPSP_SO8
1
Cout ESR=15m ohm
Ipeak=14.02A, Imax=9.81A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=2.4872A
=>1/2DeltaI=1.243A
Vtrip=Rtrip*10uA=17.8K*10uA=0.178V
Iocpmin=Vtrip/Rdsonmax*1.2+1.243A
=0.178/(0.0115*1.2)+1.243=12.898A+1.243A=14.141A
Iocpmax=(0.178/(0.009*1.1))+1.243A=17.98A+1.243A
=19.22A
Iocp=14.141A~19.22A
B
PC104
10U_0805_6.3V6M
A
A
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
+1.5VP/+0.9VSP
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
48
of
52
5
4
3
2
1
+5VS
3
2
1
PVCC
31
LGATE2
30
PGND2
29
PHASE2
28
PHASE_CPU2
UGATE2
27
UGATE_CPU2-1
BOOT2
26
NC
25
BOOT_CPU2
1
2
1
2
PR152
0_0603_1%
PC127
0.22U_0603_10V7K
LGATE_CPU1
LGATE_CPU2
2
PR121
0_0603_5%
1 U_CPU2-1
4
PR164
10_0603_5%
1
2
PC134 1000P_0402_50V7K
1
2
PC136
1
820P_0402_50V7K
2
1
2
3
2
1
PC116
1000P_0603_50V7K
2
1
1
PR144
10K_0402_1%
2
1
PR155
10K_0402_1%
2
1
PR157
3.65K_0805_1%
2
1
3
2
1
5
6
7
8
5
6
7
8
3
2
1
2
PR156
1_0402_5%
@ PR159
0_0603_5%
1
2
VSUM
1
2
PC132
0.22U_0603_10V7K
VCC_PRM
ISEN2
B
1
1
1
3
PR168
2.61K_0402_1%
2
PR173 4.42K_0402_1%
2
PH3
10KB_0603_5%_ERTJ1VR103J
1
1
PR172 1K_0402_1%
2
2
2
PC139 180P_0402_50V8J
1
2
PR170
20_0402_5%
C
VSUM
PC138
0.01U_0603_50V7K
PR171
11K_0402_1%
2
1
PR169
0_0402_5%
1
2
<5> VSSSENSE
@PC137
@PC137
0.022U_0603_50V7K
2
+CPU_CORE
PR167
20_0402_5%
1
2
2
<5> VCCSENSE
CPU_B+
VCC_PRM
CPU_B+
PC135
0.1U_0603_25V7K
1
1
2
PR165
1K_0402_1%
PR166
0_0402_5%
1
2
2
2
1
B
+5VS
PC131
1U_0402_6.3V6K
LGATE_CPU2
PR163
255_0402_1%
1
2
ISEN1
ISEN2
2
1_0603_5%
LGATE_CPU2
220P_0402_50V7K
1
2
1
PR158
2
PC133
1
1
2
@ PR161
0_0402_5%
PR162
1K_0402_1%
2
1
PR160 97.6K_0402_1% PC130 470P_0402_50V7K
1
2
2
1
1
PL11
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4
PC129
PR154
680P_0402_50V7K
6.8_1206_5%
2
1 2
1
24
4
PC128 1000P_0402_50V7K
PR145
1_0402_5%
PC121
0.22U_0603_10V7K
ISEN1
SI7686DP-T1-E3_SO8
PQ34
AO4456_SO8
+CPU_CORE
3
@ PR146
0_0603_5%
1
2
VSUM
PQ32
PQ33
AO4456_SO8
4
2
1
32
PC122
10U_1206_25V6M
2
1
LGATE1
5
PGND1
33
LGATE_CPU1
3
2
1
PHASE_CPU1
3
2
1
2
UGATE_CPU1
LGATE_CPU1
34
PQ31
AO4456_SO8
4
PC120
680P_0402_50V7K
PR142
6.8_1206_5%
1 2
1
5
6
7
8
37
35
PHASE1
4
PC114
2200P_0402_50V7K
2
1
PL10
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4
PHASE_CPU1
D
PC115
220U_25V_M
2
2
PC119
0.22U_0603_10V7K
2 1
2
PQ30
AO4456_SO8
UGATE1
PC113
10U_1206_25V6M
2
1
PQ29
SI7686DP-T1-E3_SO8
4
1
+
PC117
1000P_0603_50V7K
2
1
PR107
0_0603_5%
1 U_CPU1
5
6
7
8
PR138
0_0603_1%
BOOT_CPU1 1
36
ISEN2
23
GND
VDD
22
2
21
FB2
VIN
12
20
FB
VSUM
COMP
11
PC112
10U_1206_25V6M
2
1
5
1
<5>
UGATE_CPU1 2
VID0
38
VW
2
1
1
OCSET
10
PC109
0.022U_0402_16V7K
PC110
2.2U_0603_6.3V6K
PC124
2200P_0402_50V7K
2
1
<5>
PL9
FBMA-L18-453215-900LMA90T_1812
2
1
PR143
3.65K_0805_1%
2
1
CPU_VID1
PR125
1_0603_5%
PC123
10U_1206_25V6M
2
1
<5>
B+
CPU_B+
2
<5>
CPU_VID2
BOOT1
ISEN1
40
41
42
39
VID1
VID2
VID3
VID4
VID5
43
44
46
45
DPRSLPVR
47
48
49
SOFT
6.81K_0402_1%
2
1
PU10
ISL6262ACRZ-T_QFN48_7X7
8
9
13K_0402_1%
1
2
1
1000P_0402_50V7K
PR153
1
NTC
7
19
PC126
6
13
PR151
VR_TT#
VO
PC125
0.022U_0603_25V7K
1
2
RBIAS
5
18
C
4
DFB
VR_TT#
PMON
17
PR149
147K_0402_1%
2
1
PSI#
3
DROOP
0_0402_5%
2
DPRSTP#
20_0402_5%
2
16
1@ PR148
PGOOD
RTN
PR147
1
PSI#
1
15
<5>
<5>
CPU_VID3
2
1
PR129 0_0402_5%
2
1
PR135 0_0402_5%
2
1
PR136 0_0402_5%
2
1
PR137 0_0402_5%
2
1
PR130 0_0402_5%
2
1
PR131 0_0402_5%
2
1
PR132 0_0402_5%
2
1
PR133 0_0402_5%
PC118
1U_0402_6.3V6K
2
1
PR140
1.91K_0402_1%
2
1
2
1
<8,16,27> VGATE
GND
+3VS
+3VS
0_0402_5%
2
CLK_EN#
PR134
1
VSEN
<16> CLK_ENABLE#
PGD_IN
CPU_VID4
CPU_VID0
0_0402_5%
2
VID6
PR128
1
0_0402_5%
2
14
<5,8,26> H_DPRSTP#
<35>
<5>
2
PR127
1
VR_ON
<8,27> PM_DPRSLPVR
PR139
499_0402_1%
CPU_VID5
2
PR126
499_0402_1%
1
2
3V3
D
<5>
VR_ON
VDIFF
<35,37>
CPU_VID6
VCC_PRM
PC140
0.1U_0402_16V7K
1
2
A
PC141
1
0.22U_0402_6.3V6K
A
1
2
2
PC142
0.22U_0603_10V7K
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
+CPU_CORE
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
49
of
52
5
4
3
2
1
PL13
1
B+_core
2
1
1
2
VGA_CORE
Imax=15.9A
Ipeak=22.8A
Iocp=30A
LX_VCORE
DH_VCORE
DH_VCORE-1
1 PR183 2
PR184 0_0603_5%
BST_VCORE
1
2
PR182
10K_0402_1%
1
0_0603_5%
+5VS
2
D
6269_VCORE
PC165
10U_1206_25V6M
2
1
PC164
10U_1206_25V6M
FBMA-L11-322513-201LMA40T_1210
2
PC166 0.1U_0603_25V7K
D
1
<41> NVVDD_PWRGD
5
B+
15
16
PQ38
SI7686DP-T1-E3_SO8
1
BOOT
PHASE
UG
2
PVCC
PR1862
6269_VCORE
4
4.7_0603_5%
1
2 PC167
14
DCR=3m OHM
3
2
1
VIN
PGOOD
GND
3
+3VS
1
PU12
2
8
PR185
0_0603_5%
6269_VCORE
2.2U_0603_6.3V6K
PL14
13
PGND
12
ISEN
11
DL_VCORE
1UH_PCMB103E-1R0MS_20A_20%
1
2
1
2
1
+NVVDD_SENSE
C
PR193
+3VS
2
2
1
1
PR197
9.76K_0402_1%
2
PR196
2
2
@ PR211
57.6K_0402_1%
GPU_VID1 <18>
PR200
10K_0402_1%
PC175
0.022U_0402_25V7K
1
1
2
1
3
S
2
5.9K_0402_1%
2
1
PR199
10K_0402_1%
2
1
2
2N7002W-T/R7_SOT323-3
G
<BOM Structure>
PQ41D
PR198
1
10K_0402_5%
1 1
1
PC174
2
0_0402_5%
3K_0402_1%
Rds=4.8mOHM
VFB=0.6V
PC173
0.01U_0402_25V7K
2
PR194
ISL6268CAZ-T_SSOP16
1
PR195
49.9K_0402_1%
2
6800P_0402_25V7K
1
2
22P_0402_50V8J
PC172
2
@680P_0603_50V7K
+
330U_V_2.5VM_R9M
PC171
1 PC169
3
2
1
3
2
1
10
9
6
2
2
S
S
S
G
PR192
1
4
G
1 2
SI7636DP-T1-E3_SO8
10_0402_1%
D
PR191
@4.7_1206_5%
S
S
S
4
+VGA_COREP
1
5
SI7636DP-T1-E3_SO8
VO
PC170
0.1U_0402_16V7K
C
PR190
ISEN_VCORE
1
2
6.34K_0402_1%
FSET
1
100K_0402_1%
EN
FB
5
PQ40
D
PQ39
1
2
7
1
COMP
SUSP#
LG
5
PR187
10K_0402_5%
PR189
<34,35,37,41> SUSP#
VCC
2
@
4
1
2
PC168
2.2U_0603_6.3V6K
PR201
6.81K_0402_1%
B
+3VS
2
+1.8VS
2
PCIE_OK
B
@ PR210
1
PR202
2
1
2
G
<BOM Structure> 10K_0402_1%
GPU_VID0 <18>
1
S
3
PC176
PJ19
JUMP_43X79
@
2
1
2
4.7K_0402_5%
PR203
1
2
PQ42 D
2N7002W-T/R7_SOT323-3
1
1
+3VS
1
1
10K_0402_5%
+5VS
1
2
4
VOUT
3
FB
2
VIN
9
+1.1VSP
GPU_VID1
Core Voltage Level
0
0
0.9 V
0
1
1.05 V
PC180
1
1
1
PC182
22U_0805_6.3V6M
2
2
PC179
2
PR207
1.15K_0402_1%
0.01U_0402_25V7K
S IC APL5913-KAC-TRL SO 8P
1
0
1.17 V
1
1
1.35 V
A
@ PC181
22U_1206_6.3V6M
1
0.1U_0402_16V7K
2
PR208
3K_0402_1%
Compal Secret Data
Security Classification
Issued Date
2008/11/10
2008/11/17
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
2
1
VOUT
GPU_VID0
2
1
M86-M
PC178
10U_0805_10V4Z
1
2
PR212
@ 10K_0402_5%
2
NVVDD_PWRGD
A
EN
GND
8
1
SUSP#
5
PR204
10K_0402_1%
0.022U_0402_25V7K
1
10K_0402_1%
1
2
VIN
2
POK
PR206
6
PU13
7
VCNTL
@ 10K_0402_5%
<34,35,37,41> SUSP#
1U_0402_6.3V6K
2
2
PC177
PR205
4
3
2
Title
Compal Electronics, Inc.
VGA_CORE/1.1VSP
Size Document Number
Custom kAL90KALH0
Date:
Rev
0.2
Thursday, November 20, 2008
Sheet
1
50
of
52
5
4
3
2
Version change list (P.I.R. List)
Item
D
1
2
3
4
Page 1 of 2
for PWR
Fixed Issue
cpu load line fail
Reason for change
Rev.
0.2
Measure cpu load line can't fit spec
Change resistance size
0.2
EMI request
Change p-mos part number
Change device size
1
0.2
Vender change EOL
0.2
device too large can't fit layout space
PG#
Modify List
Date
Phase
49
change the resistance value of
pr173.from 4.42k to 3.83k
2008/08/08
DVT
49
Change pc116 and pc117 size
from 0402 to 0603
2008/08/08
DVT
PQ12 part number from
4835bdy to 483500y
46
44-50
Change resistance value
1.05V tranient fail
0.2
47
change resistance
for hdmi
0.2
45
DVT
2008/08/08
PQ4,PQ14,PQ16,PQ18,PQ19,PQ20,PQ27,PQ36,PQ37,PQ41,PQ42
change to sot323-3
PR94 from 60.4k to 59k
D
2008/08/12
DVT
2008/08/12
DVT
2008/08/14
DVT
5
pr41 change from 61.3k to 63.4k
6
7
C
8
C
9
10
11
12
13
14
B
15
B
16
17
18
19
20
21
22
A
A
23
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PIR (PWR)
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Thursday, November 20, 2008
Sheet
1
51
of
52
5
4
3
2
1
A --> C Change List
1120------------------Page 35,Chang
R1745,R1746 to 4.7K SD028470180
D
1120------------------Page 36,Add
R106,R109,R1846,R1847 to 0R
D
1120------------------Page 37,Add
R1845 to 10K
1120------------------Page 37,Add
R49 to 1K, JP24 to ACES_88266_02001
1217------------------Page 42,Delete
R1814,R1815,R1816,R1817,R1818,R1819
0106------------------Page 39, Delete D63 for Microsoft certification;
Page 36, Delelte R1773, modify value or R1774, R1775 for LED color.
C
C
B
B
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/11/10
Issued Date
Deciphered Date
2008/11/17
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
HW PIR1
Size Document Number
Custom
Rev
0.2
kAL90KALH0
Date:
Tuesday, January 06, 2009
Sheet
1
52
of
52

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