HOW TO CONTROL THE C2 CoolMOS and its EMI BEHAVIOR Abstract

HOW TO CONTROL THE C2 CoolMOSTM and
its EMI BEHAVIOR
by Marco Puerschel and Ilia Zverev, Infineon Technologies
Abstract
This article demonstrates the superior switching performance of CoolMOS C2 and shows how to control
the switching slopes through the external gate resistor. The EMI spectra benchmarking of industry
standard SMPS is shown.
New generation optimised for the fastest high voltage switch
The main focus of the development for the second generation of CoolMOS – which is called the C2 type
– was placed on the reduction of switching time. The combination of the low gate charge known from
the first generation and the drastic reduction of internal gate resistor for the second generation of
CoolMOS results in a switching time which is a new benchmark (Figure 1). This new generation of
CoolMOS has a completely different gate structure compared to the first generation (S5 type). In this
new gate structure the internal gate resistance has a value of less than 1Ω and is almost independent of
the chip size.
ID, [A]
VDS, [V]
500
12
400
Standard MOS
10
8
300
CoolMOSTM
6
200
4
100
2
0
0
0
25
50
75
100
125
time, [ns]
Figure 1: CoolMOS C2 - Fastest switching
device
As a result of fast switching, the energy losses will be reduced by 54% compared with a standard
MOSFET.
The main question in many applications is how can the switching times, delay times, di/dt- and dv/dtvalues be adjusted. The following investigations have been carried out to answer these questions.
Controllability of the new type of high voltage switch
The noise emission and oscillation (ringing) is proportional to the di/dt- and dv/dt-slopes during the turn
on and turn off transients. In order to control these current and voltage slopes different types of snubber
networks are used. Further investigations were made in the same test setup as described above by
changing only the external gate resistor values and using the 600V SiC Schottky diode (a prototype
SDP06S60) as a commuted diode.
Figure 2 demonstrate the drain current slope and drain to source voltage slope during the turn on
transient for various values of external gate resistor.
2000
25000
di/dt
2000
100000
di/dt
dv/dt
dv/dt
1600
20000
1600
80000
1200
15000
1200
60000
800
10000
800
40000
400
5000
400
20000
0
0
0
20
40
Rgate, [Ohm]
60
0
0
0
20
40
60
Rgate, [Ohm]
Figure 2: Drain current and drain to source Figure 3: Drain current and drain to source
voltage vs external gate resistance during turn voltage vs external gate resistance during turn
on of SPP11N60C2
off of SPP11N60C2
Turn off behavior is shown in Figure 3 – drain current slope and drain to source voltage slope.
As we can see the drain current and drain to source voltage slopes can be fully adjusted using the
external gate resistor during turn on and off transients.
Conducted EMI benchmarking in industry standard SMPS
In order to achieve the reproducible EMI measurements it is necessary to have a well-defined
environment. The test setup contains a Line Impedance Stabilization Network (LISN) with a
standardized impedance. The LISN is designed for measurements of conducted EMI in the frequency
range from 10kHz and 30MHz. To avoid radiation of the surrounding the setup was built up in an
insulated metal cage. An EMI test receiver is based on CISPR.
Investigation results with the standard MOSFET and the new CoolMOS SPW11N60C2 in a 600W
telecom power supply with 48V output voltage was done. This SMPS utilizes the state of the art full
bridge topology with zero voltage transitions (ZVT) and phase shift control mode. Active PFC circuit
uses the standard boost converter topology. Figure 4 shows the results with the standard MOSFET. The
spectrum exceeds the norm limit line at some frequencies as 200kHz and in high frequency region
around 2MHz.
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
0
0
10
100
1000
10000
10
100
1000
Spectrum
VDE 0872 norm limit
Figure 4: Spectrum with standard MOSFET
transistors
10000
f, [kHz]
f, [kHz]
Spectrum
VDE 0872 norm limit
Figure 5: Spectrum with CoolMOS
SPW11N60C2
The standard MOSFETs were replaced with a 11A/600V TO247 (SPW11N60C2). Some adjustments in
the gate resistors and the bridge leg delay times were made in order to achieve similar overall switching
performance regarding the control timing of relatively complicated ZVT phase shift control mode.
Results are shown in Figure 5. The spectrum looks smoother. The peak at 200kHz is below the norm’s
limit line. Even the peak at 2MHz is with CoolMOS much better than with a standard MOSFET. Due to
good controllability of switching behavior of CoolMOS it is possibly to achieve better EMI noise level
with same or even lower power losses.
As a second standard type of SMPS, investigations of a typical PC SMPS (“silver box”) were made. The
topology used is a hard switching single-transistor converter with an output power of 425W. The
switching frequency of the transistor is 50kHz. Due to the standard PC SMPS it contains a wide input
range and several output stages.
Comparison of the conducted EMI-behavior between a design with standard MOSFET and CoolMOS
were made under following operating conditions: load of 21A on the 5V output stage and an input
voltage of 230V/AC.
Figure 6 shows the measured conducted EMI spectra of PC SMPS with standard MOSFET. The
switching frequency of 50kHz and its harmonic can be seen. The spectrum is below the limit line in
frequency range from 150kHz.
Next Figure 7 demonstrates the conducted EMI spectrum with CoolMOS transistor with C2. The
spectrum is well below the limit line in the norm corresponded frequency range. These spectrum is very
similar to the spectrum with standard MOSFET.
dB uV
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
0
0
10
10
100
1000
1000
10000
f, [kHz]
f, [kHz]
VDE0872 norm limit
100
10000
Spectrum
Figure 6: Spectrum of 425 watt output power
SMPS with Standard MOSFET
VDE0872 norm limit
Spectrum
Figure 7: Spectrum of 425 watt output power
SMPS with CoolMOS SPP20N60C2
The investigations show that the EMI behavior of this PC SMPS almost does not depend on the
transistor type. There is no real difference between a design with CoolMOS C2 and standard MOSFET.
Conclusion
The fast switching of CoolMOS C2 leads to less switching energy losses and is a new benchmark
(Figure 1).
The theory says – the higher switching speed leads on the first hand to the lower switching energy
losses, but on the other hand it causes higher electrical noise spectrum. The electrical noise level can be
reduced by slowing down the switching transient of MOSFET.
The switching speed (dv/dt, di/dt) of MOSFET can be controlled by adjustment of the external gate
resistor. In case of CoolMOS C2 the switching speed can be varied in a very wide range. The designer
has a lot of adjustment possibilities – the switching speed can be increased in order to minimize the
switching energy losses, or the transistor can be slowed down to reduce the EMI noise.
The investigations of conducted EMI in industry standard SMPS demonstrate that the very fast
CoolMOS causes no problems regarding the EMI, even the spectra looks smoother with this new
adjustable transistor family.