32-Channel High Voltage Sample and Hold Amplifier Array HV257 Features

HV257
HV257
32-Channel High Voltage
Sample and Hold Amplifier Array
Demo Kit
Available
Features
General Description
❑ 32 independent high voltage amplifiers
The Supertex HV257 is a 32-channel high voltage sample and
hold amplifier array integrated circuit. It operates on a single high
voltage supply, up to 300V, and two low voltage supplies, VDD
and VNN.
❑ 300V operating voltage
❑ 295V output voltage
❑ 2.2V/µs typical output slew rate
All 32 sample and hold circuits share a common analog input,
Vsig. The individual sample and hold circuits are selected by a
5 to 32 logic decoder. The sampled voltage on the holding
capacitor is buffered by a low voltage amplifier and amplified by
a high voltage amplifier with a closed loop gain of 72V/V. The
internal closed loop gain is set for an input voltage range of 0V
to 4.096V. The input voltage can be up to 5.0V, but the output will
saturate. The maximum output voltage swing is 5V below the VPP
high voltage supply. The outputs can drive capacitive loads of up
to 3000pF.
❑ Adjustable output current source limit
❑ Adjustable output current sink limit
❑ Internal closed loop gain of 72V/V
❑ 12MΩ feedback impedance
❑ Layout ideal for die applications
Application
❑ MEMS (microelectromechanical systems) driver
The maximum output source and sink current can be adjusted by
using two external resistors. An external RSOURCE resistor
controls the maximum sourcing current and an external RSINK
resistor controls the maximum sinking current. The current limit
is approximately 12.5V divided by the external resistor value.
The setting is common for all 32 outputs. A low voltage silicon
junction diode is made available to help monitor the die
temperature.
❑ Piezoelectric transducer driver
❑ Optical crosspoint switches (using MEMS technology)
Typical Application
High Voltage
Power Supply
Supertex HV257
DAC
HVOUT0
VSIG
HVOUT1
Low Voltage
Power Supply
A0
A1
A2
A3
A4
HVOUT3
32
Low Voltage
Channel
Select
Sample
and Hold
High Voltage
OpAmp Array
EN
x
y
MEMS
Array
HVOUT30
RSOURCE
RSINK
Micro
Processor
HVOUT2
y
x
HVOUT31
AGND
DGND
VNN
A122104
A122104
1
HV257
Ordering Information
Device
Maximum Output
Voltage
HV257
Package Options
Nominal Closed
Loop Gain
295V
100Lead MQFP
Die
HV257FG
HV257X
72V/V
Absolute Maximum Ratings*
VPP, High voltage supply
310V
AVDD, Analog low voltage positive supply
8.0V
DVDD, Digital low voltage positive supply
8.0V
AVNN, Analog low voltage negative supply
-7.0V
DVNN, Digital low voltage negative supply
-7.0V
Logic input voltage
-0.5V to DVDD
VIN, Analog input signal
0V to 6.0V
Storage temperature range
-65°C to 150°C
Maximum junction temperature
150°C
*Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Electrical Characteristics
(Over operating conditions unless otherwise noted.)
Parameters
Symbol
Min
Typ
Max
Condition
Unit
Operating Conditions
VPP
High voltage positive supply
125
300
V
V DD
Low voltage positive supply
6.0
7.5
V
VNN
Low voltage negative supply
-4.5
-6.5
V
IPP
VPP supply current
0.8
mA
VPP = 300V, All HVOUT = 0V, No Load
4.3
mA
VDD = 6.0V to 7.5V
mA
VNN = -4.5V to -6.5V
I DD
VDD supply current
I NN
VNN supply current
-5.2
TJ
Junction temperature range
-10
125
0
VPP -5
V
±50
mV
Input referred.
˚C
High Voltage Amplifier
HVOUT
HVOUT voltage swing
VINOS
Input voltage offset
SR
HVOUT slew rate rise
2.2
V/µs
No Load
HVOUT slew rate fall
2.0
V/µs
No Load
BW
HVOUT -3dB channel bandwidth
4.0
KHz
VPP = 300V
AO
Open loop gain
70
100
AV
Closed loop gain
68.4
72.0
R FB
Feedback resistance from HVOUT to ground
9.6
12
CLOAD
HVOUT capacitive load
3000
pF
ISOURCE
HVOUT sourcing current limiting range
385
550
715
µA
RSOURCE = 25KΩ
ISINK
HVOUT sinking current limiting range
385
550
715
µA
RSINK = 25KΩ
0
dB
75.6
V/V
MΩ
External resistance range for setting current
RSOURCE source limit
25
250
KΩ
RSINK
External resistance range for setting current
sink limit
25
250
KΩ
CTDC
DC channel to channel crosstalk
-80
dB
PSRR
Power supply rejection ratio for VPP, VDD, and VNN
-40
dB
A122104
2
HV257
Sample and Hold
Symbol
Parameter
Min
Typ
Pedestal Voltage
1.0
RSW
Sample and Hold Switch resistance
5.0
C
Sample and Hold Capacitor
10
RDROOP
Droop rate during hold time relative to input
VSIG
Input voltage range
VPED
Max
Units
mV
Conditions
input referred
KΩ
0
12.0
pF
2.0
V/s
5.0
V
Max
Units
output referred
Logic Decoder
Symbol
TSU
Min
Parameter
Set-up time-address to enable
Typ
75
Conditions
ns
TH
Hold time-address to enable bar
75
VIH
Input logic high voltage
2.4
VDD
VIL
Input logic low voltage
0
1.2
V
V
ns
lIH
Input logic high current
1.0
µA
lIL
Input logic low current
-1.0
VIH = VDD
VIL = 0 V
µA
Diode
Symbol
Min
Parameter
PIV
Peak inverse voltage
VF
Forward diode drop
IF
Forward diode current
TC
VF temperature coefficient
Typ
Max
Units
5.0
V
cathode to anode
V
If = 100µA, anode to cathode@25OC
0.60
100
-2.20
Conditions
µA
anode to cathode
mV/ ˚C
anode to cathode
Power Up/Down Sequence
The device can be damaged due to improper power up / down
sequence. To prevent damage, please follow the acceptable
power up /down sequences and add two external diodes as
shown in the diagram below. The first diode is a high voltage
diode across VPP and VDD where the anode of the diode is
connected to VDD and the cathode of the diode is connected to
Vpp. Any low current high voltage diode such as a 1N4004 will
be adequate. The second diode is a schottky diode across VNN
and DGnd where the anode of the schottky diode is connected
to VNN and the cathode is connected to DGnd. Any low current
schottky diode such as a 1N5817 will be adequate.
VDD
VPP
1N4004
or similar
1) VPP
or
1) VNN
DGND
VNN
1N5817
or similar
Acceptable Power Up Sequences
2) VNN
3) VDD
4) Inputs & Anode
2) VDD
3) VPP
4) Inputs & Anode
Acceptable Power Down Sequences
1) Inputs & Anode
or
1) Inputs & Anode
2) VDD
3) VNN
4) VPP
2) VPP
3) VDD
4) VNN
A122104
3
HV257
Block Diagram
Byp-VPP
Byp-AVDD
Byp-AVNN
VPP
AVDD
Anode
To internal VPP bus
Bias Circuit
To internal analog VDD bus
AVNN
To internal analog VNN bus
DVDD
To internal digital VDD bus
DVNN
To internal digital VNN bus
VSIG
Cathode
AVDD
+
DVDD
CH
VPP
+
AVNN
Q1
AVNN
S/H - 0
A0
71R
A1
A2
A3
HVOUT0
-
Q0
R
5 to 32
Decoder
AVDD
+
A4
CH
VPP
+
-
HVOUT1
-
EN
AVNN
Q31
AVNN
S/H - 1
DGND
71R
R
AGND
AVDD
+
RSOURCE
RSINK
HVOUT
Current
Source
Limiting
HVOUT
Current
Sink
Limiting
To all HVOUT
amplifiers
CH
VPP
+
-
HVOUT31
AVNN
AVNN
S/H - 31
71R
To all HVOUT
amplifiers
R
A122104
4
HV257
Truth Table
A4
A3
A2
A1
A0
EN
Selected S/H
L
L
L
L
L
H
0
L
L
L
L
H
H
1
L
L
L
H
L
H
2
L
L
L
H
H
H
3
•
•
•
•
•
•
•
•
•
H
H
H
L
H
H
29
H
H
H
H
L
H
30
H
H
H
H
H
H
31
X
X
X
X
X
L
All Open
Pin Description
VPP
High voltage positive supply. There are two pads.
BYP-VPP
A low voltage 1.0 to 10nF decoupling capacitor across VPP and BYP-VPP is
required.
AVDD
Analog low voltage positive supply. This should be at the same potential as
DVDD. There are two pads.
BYP-AVDD
A low voltage 1.0 to 10nF decoupling capacitor across AVDD and BYP-AVDD is
required.
AVNN
Analog low voltage negative supply. This should be the same potential as
DVNN. There are two pads.
BYP-AVNN
A low voltage 1.0 to 10nF decoupling capacitor across AVNN and BYP-AVNN is
required.
DVDD
Digital low voltage positive supply. This should be the same potential as AVDD.
There are two pads.
DVNN
Digital low voltage negative supply. This should be the same potential as AVNN.
There are two pads.
DGND
Digital ground
AGND
Analog ground. There are three pads. They need to be externally connected
together.
A0 to A4
Decoder logic inputs. Addressed channel will close the sample and hold switch.
Sample and hold switches for unaddressed channels are kept open.
EN
Active logic high input. Logic low will keep sample and hold switches open.
Vsig
Common input signal for all 32 sample and hold circuits.
RSOURCE
External resistor from RSOURCE to VNN sets output current sourcing limit.
Current limit is approximately 12.5V divided by Rsource resistor value.
RSINK
External resistor from RSINK to VNN sets output current sinking limit. Current
limit is approximately 12.5V divided by RSINK resistor value.
Anode
Cathode
HVOUT0 to HVOUT31
Anode side of a low voltage silicon diode that can be used to monitor die
temperature.
Cathode side of a low voltage silicon diode that can be used to monitor die
temperature.
Amplifier outpu.ts
A122104
5
HV257
100
81
80
1
100-Lead MQFP
(top view)
51
30
31
50
Pin Configuration
DGND
AGND
AGND
VSIG
AGND
A122104
6
HV257
Pad Configuration (not drawn to scale)
DGND
DVDD
DVNN
AGND
VSIG
AVDD
Byp-AVNN
AVNN
Anode
Byp-AVDD
Do Not Bond.
For testing only.
Cathode
A4
RSINK
A3
RSOURCE
BYP-VPP
VPP
HVOUT31
A2
A1
A0
EN
HVOUT30
HVOUT29
HVOUT28
HVOUT27
HVOUT26
HVOUT25
HVOUT24
HVOUT23
HVOUT22
HVOUT21
HVOUT20
HVOUT19
HVOUT18
HVOUT17
Do Not Bond.
Leave Floating.
HVOUT16
HVOUT15
HVOUT14
HVOUT13
HVOUT12
HVOUT11
HVOUT10
HVOUT9
HVOUT8
HVOUT7
HVOUT6
HVOUT5
HVOUT4
HVOUT3
HVOUT2
HVOUT1
HVOUT0
VPP
DVDD
DVNN
AGND
AVDD
AVNN
AGND
A122104
7
HV257
Pad Coordinates
Chip size: 17004µm x 5480µm
Center of die is (0,0)
DOC. #: DSFP-HV257
A122104
A122104
8
Package Outlines
100 LEAD MQFP PACKAGE OUTLINE (FG)
0.913
(23.2)
70
0.787
(20.0)
51
0.063
(1.6)
71
50
100
31
0.551
(14.0)
0.677
(17.2)
0.063
(1.6)
1
30
0.0256
(0.65)
0.0118 ± 0.0031
(0.30 ± 0.08)
0.0346 ± 0.0059
(0.88 ± 0.15)
0.1063 ± 0.0079
(2.70 ± 0.20)
0.0067 ± 0.0024
(0.17 ± 0.06)
0.0111 ± 0.013
(2.825 ± 0.325)
Note: C ircle (e.g. B ) indicates J E DE C R eference.
Doc. #: DSPD-100MQFPFG
©2004 S upertex Inc. All rights res erved. Unauthorized us e or reproduction prohibited.
Meas urement Legend =
Dimens ions in Inches
(Dimens ions in Millimeters )
A052104
1235 B ordeaux Drive, S unnyvale, C A 94089
T E L: (408) 222-8888 / F AX : (408) 222-4895
www.s upertex.com
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