SATHYABAMA UNIVERSITY DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION LAB MANUAL

Transcription

SATHYABAMA UNIVERSITY
DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION
LAB MANUAL
III YEAR B.E (EIE) – VI SEMESTER
Academic Year 2013-2014
Batch (2011 – 2015)
SECX4028 – Microprocessor & Microcontroller Lab
Name : ---------------------------------------------------------------------------
Reg.No :----------------------------------------------------------------------------
SECX4028
MICROPROCESSOR AND MICROCONTROLLER LAB
LIST OF EXPERIMENTS:
1. Familiarization of 8085 trainer kit, 8086 trainer kit, 8051 trainer kit & 89C51
2. Addition & subtraction of 8 and 16 bits using 8085.
3. Multiplication & division 8 and 16 bits using 8085.
4. Interfacing of stepper motor using 8085.
5. Interfacing of traffic light using 8085.
6. Addition and subtraction of two 16 bit numbers using 8086.
7. Code converters using 8086.
8. Sorting of N numbers using 8086.
9. Arithmetic operation programs using 8051.
10. Interfacing of ADC using 8051.
11. Interfacing of DAC using 8051.
12. Addition and subtraction using 89C51.
13. Filling of internal memory using 89C51
EXPT.NO:1 FAMILIARIZATION OF 8085 TRAINER KIT, 8086 TRAINER KIT,
8051 TRAINER KIT & 89C51
1.1 Introduction of 8085:
1.1.1 Internal Block Diagram of 8085:
INTEL 8085 is one of the most popular 8-bit microprocessor capable of addressing
64 KB of memory and its architecture is simple. The device has 40 pins, requires +5 V
power supply and can operate with 3MHz single phase clock.
ALU (Arithmetic Logic Unit):
The 8085A has a simple 8-bit ALU and it works in coordination with the
accumulator, temporary registers, 5 flags and arithmetic and logic circuits. ALU has the
capability of performing several mathematical and logical operations. The temporary
registers are used to hold the data during an arithmetic and logic operation. The result is
stored in the accumulator and the flags are set or reset according to the result of the
operation. The flags are affected by the arithmetic and logic operation. They are as
follows:
 Sign flag
After the execution of the arithmetic - logic operation if the bit D7 of the
result is 1, the sign flag is set. This flag is used with signed numbers. If it is 1, it is
a negative number and if it is 0, it is a positive number.
 Zero flag
The zero flag is set if the ALU operation results in zero. This flag is
modified by the result in the accumulator as well as in other registers.
 Auxiliary carry flag
In an arithmetic operation when a carry is generated by digit D3 and
passed on to D4, the auxiliary flag is set.
 Parity flag
After arithmetic – logic operation, if the result has an even number of 1’s
the flag is set. If it has odd number of 1’s it is reset.
 Carry flag
If an arithmetic operation results in a carry, the carry flag is set. The carry
flag also serves as a borrow flag for subtraction.
Timing and control unit
This unit synchronizes all the microprocessor operation with a clock and generates the
control signals necessary for communication between the microprocessor and peripherals.
The control signals RD (read) and WR (write) indicate the availability of data on the data
bus.
Instruction register and decoder
The instruction register and decoder are part of the ALU. When an instruction is fetched
from memory it is loaded in the instruction register. The decoder decodes the instruction and
establishes the sequence of events to follow.
Register array
The 8085 has six general purpose registers to store 8-bit data during program execution.
These registers are identified as B, C, D, E, H and L. they can be combined as BC, DE and
HL to perform 16-bit operation.
Accumulator
Accumulator is an 8-bit register that is part of the ALU. This register is used to store 8-bit
data and to perform arithmetic and logic operation. The result of an operation is stored in the
accumulator.
Program counter
The program counter is a 16-bit register used to point to the memory address of the next
instruction to be executed.
Stack pointer
It is a 16-bit register which points to the memory location in R/W memory, called the
Stack.
Communication lines
8085 microprocessor performs data transfer operations using three communication
lines called buses. They are address bus, data bus and control bus.
 Address bus – it is a group of 16-bit lines generally identified as A0 – A15. The
address bus is unidirectional i.e., the bits flow in one direction from
microprocessor to the peripheral devices. It is capable of addressing 216 memory
locations.
 Data bus – it is a group of 8 lines used for data flow and it is bidirectional. The
data ranges from 00 – FF.
 Control bus – it consist of various single lines that carry synchronizing signals.
The microprocessor uses such signals for timing purpose.
1.2 Introduction of 8086:
Figure shows a block diagram of the 8086 internal architecture. As shown in the figure,
the 8086 microprocessor is internally divided into two separate functional units. These are the
Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU fetches instructions, reads data
from memory and ports, and writes data to memory and I/O ports. The EU executes instructions
that have already been fetched by the BIU. The BIU and EU function independently. The BIU
interfaces the 8086 to the outside world. The BIU provides all external bus operations. The BIU
contains segment registers, instruction pointer, instruction queue, and address generation bus
control circuitry to provide functions such as fetching and queuing of instructions, and bus
control.
The BIU’s instruction queue is a First-In First-out (FIFO) group of registers in which up
to six bytes of instruction code are perfected from memory ahead of time. This is done in order
to speed up program execution by overlapping instruction fetch with execution. This mechanism
is known as pipelining. If the queue is full and the EU does not request BIU to access memory,
the BIU does not perform any bus cycle. On the other hand, if the BIU’s is not full and if it can
store at least two bytes and the EU does not request it to access memory, the BIU may prefect
instructions. However, if BIU is interrupted by EU for memory access while the BIU is in the
process of fetching an instruction, the BIU first completes fetching and then services the EU: the
queue allows the BIU to keep the EU supplied with perfected instructions without typing up the
system bus. If an instruction such as Jump or subroutine call is encountered, the BIU will reset
the queue and begin refilling after passing the new instruction to the EU.
The BIU contains a dedicated adder, which is used to produce the 20-bit address. The bus
control logic of the BIU generates all the bus control signals such as read and writes signals for
memory and I/O.
The BIU has four 16-bit segment registers. These are the Code Segment (CS) register, the
Data Segment (DS) register, the Stack Segment (SS) register, and the Extra Segment (ES)
register. The 8086’s one-megabyte memory is divided into segments of up to 64K bytes each.
The 8086 can directly address four segments (256K byte within the 1 Mb memory) at a particular
time. Programs obtain access to code and data in the segments by changing the segment register
contents to point to the desired segments. All program instructions must be located in main
memory pointed to by the 16-bit CS register with a 16-bit offset in the segment contained in the
16-bit instruction pointer (IP). The BIU computes the 20-bit physical address internally using the
programmer-provided logical address (16-bit contents of CS and IP) by logically shifting the
contents of CS four bits to left and then adding the 16-bit contents of IP. In other words, the CS
is multiplied by 1610 by the BIU for computing the 20-bit physical address. This means that all
instructions of a program are relative to the contents of the CS register multiplied by 16 and then
offset is added provided by the 16-bit contents of IP.
The BIU always inserts four Zeros for the lowest 4-bits of the 20-bit starting address
(physical) of a segment. In the other words, the CS contains the base or start of the current code
segment, and IP contains the distance or offset from this address to the next instruction byte to be
fetched. Note that immediate data are considered as part of the code segment.
The SS register points to the current stack. The 20-bit physical stack address is calculated
from SS and SP for stack instruction such as PUSH and POP. The programmer can use the BP
register instead of SP for accessing the stack using the based addressing mode. In this case, the
20-bit physical stack address is calculated from BP and SS.
The DS register points to the current data segment; operands for most instructions are
fetched from this segment. The 16-bit contents of Source Index (SI) or Destination Index (DI)
are used as offset for computing the 20-bit physical address.
The ES register points to the extra segment in which data (in excess of 64k pointed to by
DS) is stored. String instructions always use ES and DI to determine the 20-bit physical address
for the destination.
The segment can be continuous, partially overlapped, fully overlapped, or disjoint. An
example of how five (segment 0 through segment 4) may be stored in physical memory are
shown.
In the above SEGMENTS 0 and 1 are contiguous (adjacent) ,SEGMENTS 1 an d 2 are
partially overlapped, SEGMENTS 2 and 3 are fully overlapped, and SEGMENTS 2 and 4 are
disjoint. Every segment must start on 16-byte memory boundaries.
Typical examples of values of segments should then be selected based on physical
addresses starting at 0000016, 0001016, 0002016, 0003016… FFFF016. A physical memory
location may be mapped into (contained in) one or more logical segments. Many applications
can be written to simply initialize the segment and then forget them.
A segment can be pointed to by more than one segment register. For example, DS and ES
may point to the same segment in memory if a string located in that segment is used as a source
segment in one string instruction and as a destination segment in another string instruction. Note
that for string instructions, ES must point to a destination segment.
It should be pointed out that codes should not be written within 6 bytes of the end of
physical memory. Failure to comply with this guideline may result in an attempted opcode fetch
from nonexistent memory, hanging the CPU if READY is not returned. One example of four
currently addressable segments is shown below:
The EU decodes and executes instructions. A decoder in the EU control system
translates instructions. The EU has a 16-bit ALU for performing arithmetic and logic operations.
The EU has eight 16-bit general registers. These are AX, BX, CX, DX, SP, BP, SI, and
DI. The 16-bit registers AX, BX, CS, and DX can be used as two 8-bit registers (AH, AL, BH,
BL, CH, CL, DH, DL). For example, the 16-bit register DX can be considered as two 8-bit
registers DH (high byte of DX) and DL (low byte of DX). The general-purpose registers AX,
BX, CX, and DX are named after special functions carried out by each one of them. For
example, the AX is called the 16-bit accumulator while the AL is the 8-bit accumulator. The use
of accumulator registers is assumed by some instructions. The Input/output (IN or OUT)
instructions always use AX or AL for inputting/outputting 16- or 8-bit data to or from and I/O
port.
Multiplication and division instructions also use AX or AL. The AL register is the same
as the 8085 A register.
BX register is called the base register. This is the only general-purpose register, the
contents of which can be used for addressing 8086 memory. All memory references utilizing
these register contents for addressing use Ds as the default segment register. The BX register is
similar to 8085 HL register. In other words, 8086 BH and BL are equivalent to 8085 H and L
registers, respectively.
The CX register is known as the counter register. This is because some instructions such
as shift rotate, and loop instructions use the contents of CX as a counter. For example, the
instruction LOOP START will automatically decrement CX by 1 without affecting flags and will
check if [CX] =0. If is zero, the 8086 executes the next instruction; otherwise the 8086 branches
to the label START.
The data register DX is used to hold high 16-bit result (data) in 16* 16 multiplications or
high 16-bit dividend (data) before a 32 16 division and the 16-bit remainder after the division.
The two pointer registers, SP (stack pointer) and BP (base pointer), are used to access
data in stack segment. The SP is used as an offset from the current SS during execution of
instructions. That involve stack segment in external memory. The SP contents are automatically
updated (incremented or decremented) due to execution of POP or PUSH instruction.
The base pointer contains an offset address in the current SS. This offset is used by the
instructions utilizing the based addressing mode.
The FLAG register in the EU holds the status flags typically after an ALU operation. The 8086
have six one-bit flags. AF (Auxiliary carry flag) is used by BCD bit) into the high nibble or
borrow from the high nibble into the low nibble of the low-order 8-bit of a 16-bit number. CF
(Carry Flag) is set if there is a carry from addition or borrow from subtraction. OF (Overflow
Flag) is set if there is an arithmetic overflow, that is, if the size of the result exceeds the capacity
of the destination location. An interrupt on overflow instructions is available which will generate
an interrupt in this situation. SF (Sign Flag) is set if the most significant bit of the result is one
(Negative) and is cleared to zero for non-negative result. PF (Parity Flag) is set if the result has
even parity; PF is zero for odd parity of the result. ZF (Zero Flag) is set if the result is zero; ZF is
zero for non-zero result. The 8086 has three control bits in the flag register which can be set or
reset by the programmer: setting DF (Direction Flag) to one causes string instructions to auto
decrement and clearing DF to zero causes string instructions to auto increment. Setting IF
(Interrupt Flag) to one causes the 8086 to recognize external mask able interrupts; clearing IF to
zero disables these interrupts. Setting TF (Trace Flag) to one places the 8086 in the single-step
mode. In this mode, the 8086 generate an internal interrupt after execution of each instruction.
The user can write a service routine at the interrupt address vector to display the desired registers
and memory locations. The user can thus debug a program.
ADDRESSING MODES OF 8086
Addressing mode indicates a way of locating data or operands. Depending upon the data
types used in the instruction and the memory addressing modes, any instruction may belong to
one or more addressing modes or some instruction may not belong to any of the addressing
modes. Thus the addressing modes describe the types of operands and the way they are accessed
for executing an instruction. Here, we will present the addressing modes of the instructions
depending upon their types. According to the flow of instruction execution, the instructions may
be categorized as
(i) Sequential control flow instructions and
(ii) Control transfer instructions.
Sequential control flow instructions are the instructions, which after execution, transfer
control to the next instruction appearing immediately after it (in the sequence) in the program.
For example, the arithmetic, logical, data transfer and processor control instructions are
sequential control flow instructions. The control transfer instructions, on the other hand, transfer
control to some predefined address somehow specified in the instruction after their execution.
For example, INT, CALL, RET and JUMP instructions fall under this category.
The addressing modes for sequential control transfer instructions are explained as follows:
1. Immediate: In this type of addressing, immediate data is a part of instruction, and appears in
the form of successive byte or bytes.
Example: MOV AX, 0005H
In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16bit in size.
2. Direct: In the direct addressing mode, a 16-bit memory address (offset) is directly specified
in the instruction as a part of it.
Example: MOV AX, [5000H]
Here, data resides in a memory location in the data segment, whose effective address may be
computed using 5000H as the offset address and content of DS as segment address. The
effective address, here, is 10H*DS+5000H.
3. Register: In register addressing mode, the data is stored in a register and it is referred using
the particular register. All the registers, except IP, may be used in this mode.
Example: MOV BX, AX.
4. Register Indirect: Sometimes, the address of the memory location, which contains data or
operand, is determined in an indirect way, using the offset registers. This mode of addressing
is known as register indirect mode. In this addressing mode, the offset address of data is in
either BX or SI or DI registers. The default segment is either DS or ES. The data is supposed
to be available at the address pointed to by the content of any of the above registers in the
default data segment.
Example: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset address is in BX. The
effective address of the data is given as 10H*DS+ [BX].
5. Indexed: In this addressing mode, offset of the operand is stored in one of the index registers.
DS and ES are the default segments for index registers SI and DI respectively. This mode is a
special case of the above discussed register indirect addressing mode.
Example: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS. The effective address, in this
case, is computed as 10H*DS+ [SI].
6. Register Relative: In this addressing mode, the data is available at an effective address
formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers
BX, BP, SI and DI in the default (either DS or ES) segment. The example given before
explains this mode.
Example: MOV Ax, 50H [BX]
Here, effective address is given as 10H*DS+50H+ [BX].
7. Based Indexed: The effective address of data is formed, in this addressing mode, by adding
content of a base register (any one of BX or BP) to the content of an index register (any one
of SI or DI). The default segment register may be ES or DS.
Example: MOV AX, [BX] [SI]
Here, BX is the base register and SI is the index register. The effective address is computed
as 10H*DS+ [BX] + [SI].
8. Relative Based Indexed: The effective address is formed by adding an 8-bit or 16-bit
displacement with the sum of contents of any one of the bases registers (BX or BP) and any
one of the index registers, in a default segment.
Example: MOV AX, 50H [BX] [SI]
Here, 50H is an immediate displacement, BX is a base register and SI is an index register.
The effective address of data is computed as 160H*DS+ [BX] + [SI] + 50H.
For the control transfer instructions, the addressing modes depend upon whether the
destination location is within the same segment or a different one. It also depends upon the
method of passing the destination address to the processor. Basically, there are two
addressing modes for the control transfer instructions, viz. inter-segment and intra-segment
addressing modes.
If the location to which the control is to be transferred lies in a different segment other than the
current one, the mode is called inter-segment mode. If the destination location lies in the same
segment, the mode is called intra-segment.
9. Intra-segment direct mode: In this mode, the address to which the control is to be transferred
lies in the same segment in which the control transfers instruction lies and appears directly in the
instruction as an immediate displacement value. In this addressing mode, the displacement is
computed relative to the content of the instruction pointer IP.
The effective address to which the control will be transferred is given by the sum of 8 or
16 bit displacement and current content of IP. In case of jump instruction, if the signed
displacement (d) is of 8 bits (i.e. –128<d<+128), we term it as short jump and if it is of 16 bits
(i.e. –32768<+32768), it is termed as long jump.
10. Intra-segment Indirect Mode: In this mode, the displacement to which the control is to be
transferred is in the same segment in which the control transfer instruction lies, but it is passed to
the instruction indirectly. Here, the branch address is found as the content of a register or a
memory location. This addressing mode may be used in unconditional branch instructions.
11. Inter-segment Direct Mode: In this mode, the address to which the control is to be transferred
is in a different segment. This addressing mode provides a means of branching from one code
segment to another code segment. Here, the CS and IP of the destination address are specified
directly in the instruction.
12. Inter-segment Indirect Mode: In this mode, the address to which the control is to be
transferred lies in a different segment and it is passed to the instruction indirectly, i.e. contents of
a memory block containing four bytes, i.e. IP (LSB), IP (MSB), CS (LSB) and CS (MSB)
sequentially. The starting address of the memory block may be referred using any of the
addressing modes, except immediate mode.
1.3 INTRODUCTION TO 8051:
MICROCONTROLLERS
i.
ii.
CPU + I/O + TIMER(S) [+ ROM] [+ RAM]
LOW TO MODERATE PERFORMANCE ONLY
iii.
LIMITED RAM SPACE, ROM SPACE AND I/O PINS
iv.
EPROM VERSION AVAILABLE
v.
vi.
vii.
LOW CHIP-COUNT TO IMPLEMENT A SMALL SYSTEM
LOW-COST AT LARGE QUANTITIES
DEVELOPMENT TOOLS READILY AVAILABLE AT REASONABLE
COST
PROGRAM STATUS WORD:
PSW (program status word) register summary
BIT
PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
SYMBOL
CY
AC
F0
RSI
RS0
ADDRESS
D7H
D6H
D5H
D4H
D3H
PSW.2
PSW.1
PSW.0
OV
-P
D2H
D1H
D0H
BIT DESCRIPTION
Carry flag
Auxiliary carry flag
Flag 0
Register bank select 1
Register bank select 0
00 = bank 0:addresses 00H01 = bank 0:addresses 08H10 = bank 0:addresses 10H11 = bank 0:addresses 18HOverflow flag
Reserved
Even parity flag
FOUR BANKS OF 8 BYTE-SIZED REGISTERS, R0 TO R7 ADDRESSES ARE:
1. 18 - 1F
FOR BANK 3
2. 10 - 17
FOR BANK 2
3. 08 - 0F
FOR BANK 1
4. 00 - 07
FOR BANK 0
(DEFAULT)
1.4 INTRODUCTION OF 89C51 MICROCONTROLLER:1.4.1 INTERNAL BLOCK DIAGRAM OF 89C51:-
The ATmel 89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash programmable and erasable read only memory (PEROM). The ATmel 89C51 device
is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with
the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By
combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful
microcomputer which provides a highly-flexible and cost-effective solution to many embedded
control applications.
The ATmel 89C51 provides the following standard features: 4K Bytes of Flash, 128 bytes of
RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex
serial port, on-chip oscillator and clock circuitry. In addition, the 89C51 is designed with static logic for
operation down to zero frequency and supports two software selectable power saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to
continue functioning. The AT89C51 Power-down Mode saves the RAM contents but freezes the
oscillator disabling all other chip functions until the next hardware reset.









Compatible with MCS-51 Products
4K Bytes of In-System Reprogrammable Flash Memory
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM 32
Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources Programmable Serial Channel
Low-power Idle and Power-down Modes 40-pin DIP
EXPT NO: 2a
ADDITION OF TWO 8 BIT & 16 BIT NUMBERS USING 8085
AIM:
To add two 8 bit numbers stored at consecutive memory locations.
ALGORITHM:
8 bit addition:
1. Load the addend into accumulator from memory.
2. Move the data into one of the registers.
3. Load the augend into accumulator from memory.
4. Perform addition operation.
5. Display the result.
16 bit addition:
1. Load the augend into HL registers pair.
2. Load the addend into another register pair.
3. Perform addition operation using DAD instruction.
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT NO: 2b SUBTRACTION OF TWO 8 BIT & 16 BIT NUMBERS USING 8085
AIM:
To perform subtraction of two 8 bit & two16 bit data using 8085.
ALGORITHM:
8 bit subtraction:
1. Load the subtrahend into accumulator from memory.
3. Load the minuend into accumulator from memory.
4. Perform subtraction operation.
16 bit subtraction:
1. Load the subtrahend into HL registers pair.
2. Load the minuend into another register pair.
3. Perform subtraction operation of least significant 8 bits.
4. Perform subtraction operation of most significant 8 bits taking borrow into account if any.
FLOW CHART.
PROGRAM:
ADDRESS
RESULT
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT NO: 3a MULTIPLICATION OF 8-BIT & 16-BIT NUMBERS USING 8085
AIM:
To perform multiplication of two 8 bit and 16 bit data using repeated addition method.
ALGORITHM:
8 bit multiplication:
1. Load the multiplicand into one register
2. Load the multiplier into another register.
3. Clear the accumulator.
4. Add the multiplier register with accumulator.
5. Decrement the multiplicand register.
6. Repeat step 4 & 5 until multiplicand register becomes zero.
1. Clear HL and another register pair, one for addition & another for carry.
2. Load the multiplicand and multiplier in two different register pairs.
3. Add the multiplier with HL.
4. If Carry occurs, increment the register pair for carry.
5. Decrement the multiplicand register pair.
6. Repeat steps 3, 4, 5 until the multiplicand register pair becomes zero.
7. Display the result and the carry.
FLOWCHART.
PROGRAM:
ADDRESS
RESULT :
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT NO: 3b
DIVISION OF TWO 8 BIT AND 16 BIT DATA USING 8085
AIM:
To perform division of two 8 bit data
ALGORITHM:
8 bit Division:
1. Load the divider into one register and accumulator.
2. Load the divisor into another register.
3. Perform subtraction operation with divisor register.
4. Increment the register meant for quotient.
5. Repeat the steps 3 and 4 until the accumulator is less than the divisor.
6. Display the quotient and remainder.
16-Bit Division
1. Load the divider into one register and accumulator.
2. Load the divisor into another register
3. Perform subtraction operation with divisor register.
4. Increment the register meant for quotient.
5. Repeat the steps 3 and 4 until the accumulator is less than the divisor
6. Display the quotient and remainder.
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT.NO: 4 INTERFACING OF STEPPER MOTOR WITH 8085
AIM:
To write a program for interfacing a stepper motor with 8085 microprocessor.
THEORY:
A motor in which the rotor is able to assume only discrete stationary angular position is a
stepper motor. The rotary motion occurs in a step-wise manner from one equilibrium position to
the next. Stepper Motors are used very wisely in position control systems like printers, disk
drives, process control machine tools, etc.
The basic two-phase stepper motor consists of two pairs of stator poles. Each of the four
poles has its own winding. The excitation of any one winding generates a North Pole. A South
Pole gets induced at the diametrically opposite side. The rotor magnetic system has two end faces.
It is a permanent magnet with one face as South Pole and the other as North Pole.
The Stepper Motor windings A1, A2, B1, and B2 are cyclically excited with a DC current
to run the motor in clockwise direction. By reversing the phase sequence as A1, B2, A2, B1,
anticlockwise stepping can be obtained.
2-PHASE SWITCHING SCHEME:
In this scheme, any two adjacent stator windings are energized. The switching scheme is
shown in the table given below. This scheme produces more torque.
ANTICLOCKWISE
CLOCKWISE
STEP
A1
A2
B1
B2
DATA
STEP
A1
A2 B1
B2
DATA
1
1
0
0
1
9h
1
1
0
1
0
Ah
2
0
1
0
1
5h
2
0
1
1
0
6h
3
0
1
1
0
6h
3
0
1
0
1
5h
4
1
0
1
0
Ah
4
1
0
0
1
9h
ADDRESS DECODING LOGIC:
The 74138 chip is used for generating the address decoding logic to generate the device
select pulses; CS1 & CS2 for selecting the IC 74175.The 74175 latches the data bus to the
stepper motor driving circuitry.
Stepper Motor requires logic signals of relatively high power. Therefore, the interface
circuitry that generates the driving pulses uses silicon Darlington pair transistors. The inputs for
the interface circuit are TTL pulses generated under software control using the Microcontroller
Kit. The TTL level of pulse sequence from the data bus is translated to high voltage output
pulses using a buffer 7407 with open collector.
ALGORITHM:
1. Initialize the memory mapped I/O address for control word to data pointer register.
2. The control word 80 is transferred to accumulator.
3. The content of accumulator is sent to memory mapped I/O address for control
word and the microprocessor gets programmed for port A, B, C as output port, I/O
mode, and simple I/O mode.
4. Initialize the memory mapped I/O address for Port A to data pointer register.
5. Initialize the Accumulator with the Hex code for rotating both motor in clockwise
direction.
6. The data is sent to Port A in order to move the stator from one step position to
other there would be some time taken so call for time delay routine.
7. Initialize the accumulator with the second hex code for rotation of stepper motor.
8. The data is sent to port A in order to move the stator from one step position to
other would be some time taken so call for time delay routine.
9. Initialize the accumulator with the third Hex code for rotation of stepper motor.
10. The data is sent to port A in order to retain the stator from one step position to
other there would be some time taken so call for time delay routine.
11. initialize the accumulator with the last hex code for rotation of stepper motor
12. The data is sent to Port A, in order to move the stator from one step position to
other there should be some time taken so call for time delay routine.
13. To make the motor rotate continuously we normally give an infinite loop so that
the loop repeats from step 4.
ALGORITHM FOR DELAY ROUTINE:
1. Initialize the register R1 with immediate data 33
2. Initialize the register Ro with immediate data 33
3. The content of R1 register is decremented by 1 until it reaches zero to attain desired
delay so repeat step 3.
4. The content of Ro register is decremented by 1 until it reaches zero to attain desired
delay so repeat step 2.
5. The called routine goes back after being executed to main program
6. Program comes to an end.
ALGORITHM FOR ANTICLOCKWISE DIRECTION:
The sequence of data is reversed so that the motor can be rotated in anticlockwise direction.
PROGRAM:
ADDRESS
RESULT:
OPCODE
MNEMONICS
COMMENT
EXPT.NO:5 INTERFACING OF TRAFFIC LIGHT USING 8085
AIM:
To write an Assembly language Program for traffic light controller.
EQUIPMENT REQUIRED:
8085 microprocessor kit, Power Supply.
ALGORITHM:
1. Start.
2. Write the control word to initialize 8085.Obtain the data for each
direction and store in the memory.
3. Initialize a counter to indicate the number of directions.
4. Initialize HL Pair to the starting address of the data.
5. Check the result.
6. Decrement the counter and repeat step 3 till counter becomes zero.
7. Stop.
PROGRAM:
ADDRESS
RESULT:
OPCODE
MNEMONICS
COMMENT
EXPT.NO: 6a ADDITION OF TWO 16 BIT NUMBERS USING 8086
AIM:
To add two 16 bit numbers using 8086.
ALGORITHM:
1. Move the addend into accumulator.
2. Add the accumulator data with augend in the specified memory
location.
3. Move the result into desired memory location.
4. Display the result
FLOWCHART:
PROGRAM:
ADDRESS OPCODE
RESULT:
MNEMONICS
COMMENT
EXPT.NO: 6b SUBTRACTION OF TWO 16 BIT NUMBERS
AIM:
To subtract two 16 bit numbers using 8086.
ALGORITHM:
1. Move the subtrahend into accumulator.
2. Subtract the minuend from accumulator content.
3. Complement the accumulator content
4. Increment the accumulator content
5. Move the result from accumulator to specified location
6. Stop the program.
FLOWCHART:
PROGRAM:
ADDRESS OPCODE
RESULT:
MNEMONICS
COMMENT
EXPT.NO:7a
CODE CONVERSION USING 8085
AIM:
To convert the given data in ASCII to HEX.
ALGORITHM:
1.
2.
3.
4.
5.
6.
7.
Load the given data in accumulator.
Compare the given data with 30 H.
If the given data is larger than 30 but less than 3A then go to step 5
If less than 30 or greater than 45, display invalid data FF.
Subtract 30 H from the given data.
Compare accumulator data with 0A, (A) > 0A subtract 07
Store the results
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT.NO:7b
CODE CONVERSION
AIM:
To convert the given data in HEX to ASCII
ALGORITHM:
1)
2)
3)
4)
5)
6)
7)
Load the given data in accumulator.
Compare the given data with 09 H.
If the given data is less than 09H
Add 30H, goto step 7
If the given data is greater than 09
Add 37H.
Store the result.
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT.NO:7c
CODE CONVERSION
AIM:
To convert the given data in BCD to HEX
ALGORITHM:
1)
2)
3)
4)
5)
6)
7)
8)
Load the given data in accumulator and two registers
To separate the Least significant 4 bits, perform AND operation with OF H.
Store the corresponding result (units place) in a register.
From the original data, separate the most significant 4 bits by performing AND operation
with FO.
To put these 4 bits in LSB position, perform Rotate Right operation 4 times.
Call Subroutine to multiply with data OAH.
The result of above operation will be in accumulator. (Tens place).
Add the two results (units place & tens place). Display the final result.
Subroutine:
1. Load the multiplicand into one register
2. Load the multiplier into another register.
3. Clear the accumulator.
4. Add the multiplier register with accumulator.
5. Decrement the multiplicand register.
6. Repeat step 4 & 5 until multiplicand register becomes zero.
7. Store the result
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT.NO:7d
CODE CONVERSION
AIM:
To convert the given data in HEX to BCD.
ALGORITHM:
1. Load the data into accumulator and another register.
2. To get the Hundredth place digit, perform division by repeated subtraction subtract 64H
(100)from the given data.
3. Perform subtraction until the result becomes less than 64H.
4. Count the number of subtractions performed, i.e, and the quotient gives the Hundredth
place value.
5. Once the result of subtraction becomes less than 64 H, get the tenth place digit by
dividing the obtained result with 0A. i.e, Perform repeated subtraction with 0A, until the
result of subtraction becomes less than 0A.
6. The remainder of the above division gives the units place digit. Store it in a register.
7. The quotient obtained is rotated left 4 times to obtain the tenth place digit.
8. Add the tenth & units place digits. Display the result.
9. Display the hundredth place digit.
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
OPCODES
COMMENTS
EXPT.NO: 8. SORTING OF N NUMBERS IN ASCENDING ORDER USING 8086
AIM:
To write an ALP for arranging the numbers in ascending order
ALGORITHM:
1.
2.
3.
4.
5.
6.
Move the counter which is the number of comparisons to CX register.
Initialize BX with starting address of array.
Decrement the counter value by one and store it to DX register.
Move the first element of array to accumulator.
Compare it with the next one.
If the succeeding element is not greater than the first, exchange the two
elements.
7. Increment BX twice.
8. Decrement counter register DX.
9. Repeat steps 4 to 8 till counter register DX =0.
10. Decrement counter CX.
11. Repeat steps 2 to 10 till CX=0.
12. Stop.
FLOWCHART:
PROGRAM:
ADDRESS OPCODE
RESULT:
MNEMONICS
COMMENT
EXPT.NO: 8b SORTING OF N NUMBER IN DESCENDING ORDER USING
8086
AIM:
To write an ALP for arranging the numbers in descending order.
ALGORITHM:
1. Move the counter value, which is the number of comparisons to CX register.
2. Initialize BX with starting address of array.
3. Decrement the counter value by one and store it to DX register.
4. Move the first element of array to accumulator.
5. Compare it with the next one.
6. If the succeeding element is greater than the first, exchange the
two
elements.
7. Increment BX twice.
8. Decrement counter register DX.
9. Repeat steps 4 to 8 till counter register DX =0.
10. Decrement counter CX.
11. Repeat steps 2 to 10 till CX=0.
12. Stop.
FLOWCHART:
PROGRAM:
ADDRESS OPCODE
RESULT:
MNEMONICS
COMMENT
EXPT.NO: 9a ADDITION OF TWO 8 BIT AND 16 BIT DATA USING
MICROCONTROLLER.
AIM:
To perform addition of two 8 bit and 16 bit data using microcontroller.
ALGORITHM:
8 bit addition:
1. Load the addend into accumulator from memory.
3. Load the augend into accumulator from memory.
4. Perform addition operation.
16 bit addition:
1. Add LSB of data
2. Store the result in the memory location pointed by DPTR
3. Increment DPTR
4. Add MSB of the data
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
COMMENTS
EXPT.NO: 9B SUBTRACTION OF TWO 8 BIT AND 16 BIT DATA USING
MICROCONTROLLERS
AIM:
To perform subtraction of two 8 bit and 16 bit data using
microcontroller.
ALGORITHM:
8 bit subtraction:
1. Load the subtrahend into accumulator from memory.
3. Load the minuend into accumulator from memory.
4. Perform subtraction operation.
16 bit subtraction:
1. Subtract LSB of data2 from LSB of data1
2. Store the result in the memory pointed by DPTR
3. Increment DPTR
4. Subtract MSB of data 2 from LSB of data1
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
COMMENTS
EXPT.NO:9c MULTIPLICATION AND DIVISION USING MICROCONTROLLERS
8051
AIM:
To perform multiplication of two 8 bit number using 8051.
ALGORITHM:
1. Load the multiplicand into one register (A).
2. Load the multiplier into another register (B).
3. Perform multiplication operation
4. Resultant LSB will be stored in A
5. Resultant MSB will be stored in B
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
COMMENTS
EXPT.NO: 9d DIVISION OF 8 BIT DATA USING MICROCONTROLLERS
AIM:
To perform division of 8 bit data
ALGORITHM:
8 bit division:
1. Store the dividend and divisor in location pointed to by R0 and R1
respectively.
2. Move them to accumulator and register B
3. Divide them using DIV instruction
4. Store quotient and remainder in desired locations
5. End the program
FLOWCHART:
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
COMMENTS
EXPT. NO: 10 INTERFACING OF ADC WITH MICROCONTROLLERS
AIM:
To study the operation of ADC and to write the ALP to convert analog to
digital values.
THEORY:
The ADC-01 analog to digital converter card interfaces with any
microprocessor kit. It is used to develop digital signal processing and real time process
control applications. The ADC-01 card incorporates monolithic CMOS 8 bit successive
approximation (microprocessor compatible) analog to digital converter ADC-0809.
This converter features a high impedance chopper stabilized comparator, its resolution
is 8 bits and conversion time is 100 microseconds. It has a programmable clock
oscillator which generates 100 KHz clock signal. The reference voltage is 5.12 Volts.
Power Connection:
Green : +12 V
Blue
: - 12 V
Black : Ground.
Block Diagram:
Since only one channel is used of the analog multiplexer, the channel select
address of ADC - 0809 are not interfaced with the 8255 IC. The 8255 is defined in
mode 0. Port A is used for reading the ADC data , defined in the Input mode, Port B is
used to apply control signals, and is defined in output mode and Port C is used to read
the status and it is defined in input mode.
PB2- Oscillator ( logic 1)
PB0-SOC
Pc0 / PC7 – EOC
DYNA -85 Address Details
Port A- 10
Port B -11
Port C- 12
Control Register – 13
ALGORITHM:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the ports of 8255.
Enable the start of conversion (SOC)
Latch the address for proper channel by making ALE high.
Check the end of conversion ( EOC)
Enable the output of ADC ( OE).
Read the converted digital data.
Call the display subroutine.
Call the delay subroutine.
Goto step 2 for taking the next sample.
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
COMMENTS
EXPT.NO: 11 INTERFACING OF DAC WITH MICROCONTROLLERS
AIM:
To study the DAC and to write the ALP to convert digital values to analog and to
generate the following waveforms: 1. Square 2.Ramp 3.Triangular.
THEORY:
The DMS- DAC 01 A Digital to Analog converter card interfaces with any
microprocessor kit. It is used to implement analog and digital signal processing and real time
process control applications on DAC -01 A interface card.
DAC-01 A is designed around DSC-0800 monolithic 8 bit high speed current output
digital to analog converter featuring 100 nsecs settling time, (typical). DAC -01 A has
adjustable voltage reference which permits full scale voltage. The Vref to full scale current
matching of better than ± LSB gives ± LSB full scale error.
RED
: + 5V.
GREEN
: +12 V
BLUE
YELLO
W
: -12V
BLACK
: +30 V
:GROUN
D
ALGORITHM:
Square waveform:
1.
2.
3.
4.
5.
6.
7.
8.
Initialise 8255 (for DAC)
Move the data 00 (low value)to accumulator
OUT through Port A
Call delay
Move the data FF (high value) to accumulator.
OUT through Port A
Call delay
Goto step 2.
Ramp Waveform:
1. Initialise the 8255 in mode 0.
2. Move the data 00 to the accumulator.
3. OUT the data through port.
4. Increment the accumulator.
6. If content of accumulator = FF, goto step 2
7. Otherwise goto step 4.
Triangular waveform
1. Initialise the 8255 in mode 0.
2. Move the data 00 to the accumulator.
4. Increment the accumulator.
6. If content of accumulator = FF, goto step 8
8. Decrement the contents of accumulator.
9. OUT through port.
10. If content of accumulator = 00, then goto step 4.
PROGRAM:
ADDRESS
RESULT:
LOOP
MNEMONICS
COMMENTS
EXPT.NO:12a ADDITION OF TWO 8-BIT NUMBERS USING 89C51.
AIM:
To write and execute an assembly language program to add two 8-bit
numbers using microcontroller 89C51.
APPARATUS REQUIRED
1. Microcontroller kit
2. PC with WinXtalk software
ALGORITHM:
1.
2.
3.
4.
5.
Start the program
Move the Data 1 to the accumulator
Add the Data 2 with the data 1 stored in the accumulator
Set the DPTR as 8300 in Ram address location.
Move the result which is in accumulator to the 8300 address
location.
6. Stop the program.
PROGRAM
ADDRESS
RESULT :
LOOP
MNEMONICS
COMMENTS
EXPT.NO:12b SUBTRACTION OF TWO 8-BIT NUMBERS
89C51.
USING
AIM:
To write and execute an assembly language program to subtract two 8-bit
numbers using microcontroller.
APPARATUS REQUIRED
1. Microcontroller kit
2. PC with WinXtalk software
ALGORITHM:
1. Load the subtrahend into accumulator from memory
2. Move the data into one of the registers
3. Load the minuend into accumulator from memory
4. Perform subtraction operations
PROGRAM
ADDRESS
RESULT:
LOOP
MNEMONICS
COMMENTS
EXPT.NO: 13 FILLING OF INTERNAL MEMORY USING 89C51
AIM:
To fill the internal memory 40 and subsequent locations with content of A
register.
ALGORITHM :
1.
2.
3.
4.
5.
6.
7.
8.
PROGRAM
ADDRESS
RESULT:
The register R0 is assigned with immediate data 06.
Store the content of Accumulator with 56.
Assign an internal data memory address 40 to register R1.
Transfer the content of Accumulator to internal l memory address
40.
Content of R1 register is incremented by one.
The content of data pointer register is incremented by one.
The loop executes until the content of R0 register reaches 0.
The program gets terminated.
LOOP
MNEMONICS
COMMENTS

SATHYABAMA UNIVERSITY DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION LAB MANUAL

Transcription

Similar documents

SoLait 100 - Product information

Data Sheet

Mobile Technology Cab Suspension FDE2

Panel 2

Accumulator Standard Range

TTCSI Services Talk final proposal

MobiCAN - temp.sie.de

Document 6510483