Document 6588952

Problem 1.
When the jr instruction is implemented in the 5-stage MIPS pipeline covered in the class, the PC
value is set in the ID stage. Would full forwarding help reduce the stall(s) for the following
instruction sequence? Justify your answer. Here “full forward” means that you can forward data
to anywhere on your datapath.
lw
$ra, 0($fp)
addi $fp, $fp, 4
jr
$ra
Problem 2. Consider a 6-stage (IF, ID, EX, MR, MW, WB ) MIPS pipelined processor with full
forwarding. Data memory is read in the MR stage, and written in the MW stage. The branch
target and branch decision are both resolved in the ID stage. For each case given below
indicate stall(s) (if any). Show your work. If there is no stall then indicate as “No stall”.
Case-1:
lw
$a0, 4($a0)
lw
$t0, 0($a0)
Case-2:
lw
$t0, 0($a0)
beq
$t0, $t1, skip
Case-3:
lw $1, 4($1)
sw $2, 0($1)
Problem 3.
As shown below, pipelined datapath includes a multiplier circuit. Due to the latency of
performing a multiply, the multiplier circuit has been pipelined across 3 stages (EX, MEM, and
M3, which stands for the Multiplier’s 3rd stage); and the multiply completes at the end of the M3
stage. To accommodate this 3-stage multiplier, the whole pipeline has been extended to six
stages (IF, ID, EX, MEM, M3, WB). Assume that forwarding unit is available in each stage of the
pipeline except Fetch. How many stall cycles are required (if any) for the following instruction
sequence? Show your work.
mult $4, $2,$1
sw $4, 0($3)
Problem 4. Consider the datapath illustrated below (note that the PC update logic and all
control logic is intentionally omitted). This pipelined datapath is similar to the one in the book,
but has several differences. BE SURE TO STUDY THE DATAPATH CAREFULLY! Assume that
registers are written during first half and read during second half of the clock.
Recall that R-format instructions have the form:
opcode rd, rs, rt
and I-format instructions have the form
opcode rt, imm(rs) or opcode rt, rs, imm
For simplicity, forwarding unit is not sown in the figure. This is a pipelined processor that
supports forwarding from “memory access” and “write back” stages to the “execution” stage.
Your friend claims that there is a bug in this design and argues that the following code cannot
be executed correctly even though bypassing wires are in place from memory access and write
back stages for both RSmux and RTmux. Is this claim correct? Justify your answer.
add
$1, $2, $8
sw
$1, 4($7)
Problem 2 (20 pts)– Consider the single-cycle datapath from lecture. Assume that you are
wearing your ISA and Datapath Designer suits. You are asked to implement a new I-type MIPS
instruction (push $rt) which first grows the stack by 4 bytes (opens new space for a new value in
the stack) and then stores $rt into this new space in stack.
Example: Compiler will generate a 32 bit instruction by interpreting “push $a0” instruction as:
$sp = $sp – 4
Memory[$sp] = $a0
Show your way of implementing the push instruction and be sure to indicate the value of all
control signals, including any new control signals.
You are free to only add wire(s), control signal(s) and/or mux(es) to the datapath. Do not modify
the main functional units themselves (the memory, register file and ALU). Try to keep your
diagram neat! You are also free to come up with your own specification for the “push” instruction
based on the following instruction format:
opcode
rs
rt
rd
imm
31-26
25-21
20-16
15-11
10-0
While we’re primarily concerned about correctness, full points will only be rewarded to
fastest solution with minimal hardware overhead. Assume that the ALU, Adder, Memory,
and Register file all take 2ns, and a 2:1 MUX takes 1ns, everything else is instantaneous.
Adding a new input line to a mux introduces additional 1ns latency. Your modification(s) should
not affect the functionally of the other types of instructions.
Problem 2. (25pts): Some of the following instructions can not be carried out in the provided
datapath. Explain why in the space after each instruction that can’t be implemented.