Fairchild Reference Design RD-407 www.fairchildsemi.com

Transcription

www.fairchildsemi.com
Fairchild Reference Design RD-407
The following reference design supports inclusion of FNx5xx60Tx in design of
Application Motion Control. It should be used in conjunction with the
Device_FNx5xx60Tx datasheets as well as Fairchild’s application note AN-9096 and
technical support team. Please visit Fairchild’s website at https://www.fairchildsemi.com.
Application
Fairchild
Device
Type
IGBT
Rating
Rated Output
(1)
Power
Refrigerator, Fan, Pump,
Dish Washer
FNB50560Tx
General
5 A / 600 V
0.7 kW
Air Conditioner
FNA51060Tx
Low VCE(sat)
10 A / 600 V
Washing Machine
FNB51060Tx
Low EOFF
10 A / 600 V
Air Conditioner
FNA51560Tx
Low VCE(sat)
15 A / 600 V
Washing Machine
FNB51560Tx
Low EOFF
15 A / 600 V
1.2 kW
2.0 kW
Isolation
Voltage
VISO =
1500 VRMS
(Sine 60 Hz,
1-min
All Shorted
Pins Heat
Sink)
Notes:
1. This rated output power is a typical value and may change depending on the operating
conditions.
Key Features
 600 V, 05~15 A 3-Phase IGBT Inverter Including Control ICs for Gate Driving and





Protections
Full Mold Package
Divided Negative DC-Link Terminals for Inverter Three-Leg Current Sensing
Single DC Power Supply Compatible Using External Bootstrap Circuit
Isolation Rating of 1500 VRMS / min
Functions
-
Input interface: Active HIGH
Compatible for 3.3 / 5 V Controller Outputs
High Side Under-Voltage Lockout without Fault Signal
Low Side Under-Voltage Lockout with Fault Signal
Short-Circuit, Over-Current Protection by Detecting Sense Current from External
Resistor
Temperature Sensing
Shut Down Function
Inter Lock Function
Soft Turn-off to Prevent Excessive Surge Voltage
© 2014 Fairchild Semiconductor Corporation
1
RD-404 • Rev. 0.0.1
1. Block Diagram
VIN(L)
Shut down
input
3Ø
3Ø VIN(H)
V-supply
V-supply
Reference Design
For Motion SPM® 55 Series
Master
Board
BLDC
Controller
/ MCU
CP15
LPF
RBS
CBS CBSC
DBS
5V
DP15
DBSZD
3Ø
3Ø
3Ø
RPF
COM
VF
VDD
IN(L)
IN(H)
VB
Motion SPM® 55 Series Test Board
5V 15V
CP05
CP15
CSC
NU NV
Motion SPM 55
Gate
Drive
IC
CSC
RSC
P
3Ø
NW
3Ø
V
U
W
RSHUNT
CDCS
U
V
W
V
VDC BUS
Hall IC
Signal
Motor
U
3Ø
RD-407 • Rev. 0.0.1
2
VDD
VSP
Fault out
& Temp.
monitoring
GND
N
Block Diagram of General Application Circuit (Direct Coupling)
Figure 1.
2. Schematic
15 V
D1 ES1J
R7
ZD2
C1
20R 1/8W 33uF/35V MMSZ5252B
(20) VB(U)
C2
104
OUT(UH)
R1 100R 1/8W
(9) IN(UH)
R2 100R 1/8W
R3 100R 1/8W
D2 ES1J
C8
102
C9
102
R8
ZD3
C3
20R 1/8W 33uF/35V MMSZ5252B
C7
102
Gating UH
(19) VB(V)
C4
104
(11) IN(VH)
D3 ES1J
Gating VH
R9
ZD5
C5
20R 1/8W 33uF/35V MMSZ5252B
Gating WH
(18) VB(W)
C6
104
(13) IN(WH)
5V line
R11 100 1/8W
Gating VL
Gating WL
(15) COM
IN(UH)
UVS
VS(U)
U,VS(U) (2)
W
V,VS(V) (3)
V
VB(V)
IN(VH)
OUT(VH)
VVS
VS(V)
VB(W)
C20
104 630V
IN(WH) OUT(WH)
VS(W)
VDD
W,VS(W) (4)
U
COM
OUT(UL)
C13
102
Gating UL
(14) VDD
C15
104
C16
ZD1
220uF/35V MMSZ5252B
R13
10K 1/8W
P
P (1)
VB(U)
C14
102
(17) VF
R4 100 1/8W
(8) IN(UL)
R5 100 1/8W
(10) IN(VL)
R6 100 1/8W
(12) IN(WL)
C12
102
C11
102
NU (5)
VF
IN(UL)
OUT(VL)
R14
20mR 5W
NV (6)
IN(VL)
N
IN(WL)
OUT(WL)
C10
102
(16) CSC
Fault Out
Shut Down input
Temp. Monitoring
CSC
NW
(7)
R11 1.8kO 1/8W
C17
102
Figure 2.
Schematic of Reference Design for 3-Phase Inverter Part (Direct Coupling)
3. Key Parameter Design
3.1.
Temperature Monitoring from VF Pin
The bootstrap capacitor value can be calculated by Equation (1):
THVIC 
(Vctr  VF )  20µA  R1)
R1  2.76µA
(1)
where:
THVIC
= Temperature of gate drive IC
Vctr
= Pull up voltage
VF
= Voltage of VF pin
R1
= Pull up resistance
3
RD-407 • Rev. 0.0.1
3.2.
Selection of Bootstrap Capacitance (CBS)
The bootstrap capacitor value can be calculated by Equation (2):
C BS 
I Leak  t
VBS
(2)
where:
Δt
= maximum ON-pulse width of high-side IGBT;
ΔVBS
= the allowable discharge voltage of the CBS (voltage ripple);
ILeak
= maximum discharge current of the CBS consisting of:






Gate charge for turning the high-side IGBT on
Quiescent current to the high-side circuit in the IC
Level-shift charge required by level-shifters in IC
Leakage current in the bootstrap diode
CBS capacitor leakage current (can be ignored for non-electrolytic capacitors)
Bootstrap diode reverse recovery charge
Practically, 2 mA of ILeak is recommended for FNA51560Tx (IPBS, operating VBS supply
current at 20 kHz, is max. 0.8 mA in the datasheet of FNA51560Tx).
 Calculation examples of CBS:
ILeak = 2 mA
ΔVBS
= 1.0 V (recommended value)
Δt = 5 ms (depends on user system)
CBS _ min 
I Leak  t 2mA  5ms

 10  10 6
VBS
1.0V
More than 2~3times  20 ~ 30 μF  standard nominal capacitance 22 ~ 35 μF
Notes:
2. In case of trapezoidal control for BLDC motor or 2-phase modulation, long ON time periods of
the high-side IGBT may exist. Attention should be paid to the bootstrap supply voltage drop.
3. The above result is only a calculation example. It is recommended that actual PWM patterns
and lifetime of components should be considered in the design.
4
RD-407 • Rev. 0.0.1
3.3. Selection of Bootstrap Resistor (RBS)
A resistor must be added in series with the bootstrap diode to slow down the dVBS/dt and
determine the time to charge the bootstrap capacitor. If the minimum ON pulse width of
low-side IGBT or the minimum OFF pulse width of high-side IGBT is tO; the bootstrap
capacitor must be charged to increase the voltage by ΔV during this period. Therefore,
the value of bootstrap resistance can be calculated by Equation (1):
RBS 
(VCC  VBS )  to
CBS  ΔVBS
(1)
where:
VCC
= Supply voltage;
VBS
= Minimum bootstrap voltage;
tO = Minimum ON pulse width;
CBS
= Bootstrap capacitor value; and
ΔVBS
= Ripple voltage of VBS.
 Calculation Examples of RBS:
VDD
= 15 V, VBS = 13 V (minimum voltage)
tO = 200 µs (if carrier frequency is 5 kHz, 1-cylce is 200 µs)
CBS
= 20 µF (obtained bootstrap capacitor value)
ΔVBS
= 1 V (recommended value)
RRS 
(VDD  VBS )  to 15  13V  200s

 20
CBS  ΔVBS
20F  1V
If the rising dVBS/dt is slowed significantly, it could cause missing pulses during the
startup phase due to insufficient VBS voltage.
3.4. Selection of Shunt Resistor (One Shunt)
The value of shunt resistor is calculated by the following equations.
Maximum Short-Circuit (SC) current trip level (depends on user selection):
ISC(max) = 1.5  IC(max)
SC Trip Reference Voltage (depends on datasheet):
VSC = min. 0.43 V, typ. 0.5 V, max. 0.57 V
Shunt Resistance:
ISC(max) = VSC(max) / RSHUNT(min)  RSHUNT(min) = VSC(max) / ISC(max)
If the Deviation of the Shunt Resistor is Limited below ± 5%:
RSHUNT(typ) = RSHUNT(min) / 0.95, RSHUNT(max) = RSHUNT(typ)  1.05
5
RD-407 • Rev. 0.0.1
Actual SC Trip Current Level becomes:
ISC(typ) = VSC(typ) / RSHUNT(typ), ISC(min) = VSC(min) / RSHUNT(max)
Inverter Output Power:
POUT =
where:
MI = Modulation Index;
VO,LL = Line to Line Voltage =
VDC_Link = DC link voltage;
IRMS = Maximum load current of inverter; and
PF = Power Factor
Average DC Current:
IDC_AVG = VDC_Link / (Pout  Eff)
where:
Eff = Inverter efficiency
The power rating of shunt resistor is calculated by the following equation:
PSHUNT = (I2DC_AVG  RSHUNT  Margin) / Derating Ratio
where:
RSHUNT = Shunt resistor typical value at TC = 25°C
Derating Ratio = Derating ratio of shunt resistor at TSHUNT = 100°C
(From datasheet of shunt resistor); and
Margin = Safety margin (determined by user)
 Shunt Resistor Calculation Examples
Calculation Conditions:
 DUT: FNA51560Tx
 Tolerance of shunt resistor: ±5%
 SC Trip Reference Voltage:
o VSC(min) = 0.45 V, VSC(typ) = 0.50 V, VSC(max) = 0.55 V
 Maximum Load Current of Inverter (IRMS): 7 Arms
 Maximum Peak Load Current of Inverter (IC(max)): 15 A
 Modulation Index (MI): 0.9
 DC Link Voltage (VDC_Link): 300 V
 Power Factor (PF): 0.8
 Inverter Efficiency (Eff): 0.95
 Shunt Resistor Value at TC = 25°C (RSHUNT): 25 mΩ
6
RD-407 • Rev. 0.0.1

Derating Ration of Shunt Resistor at TSHUNT = 100°C: 70%

Safety Margin: 20%
 Calculation Results:

ISC(max): 1.5  IC(max) = 1.5 x 15 A = 22.5 A

RSHUNT(min): VSC(max) / ISC(max) = 0.55 V / 22.5 A = 25 mΩ

RSHUNT(typ): RSHUNT(min) / 0.95 = 25 mΩ / 0.95 = 26 mΩ

RSHUNT(max): RSHUNT(typ) x 1.05 = 40 mΩ x 1.05 = 28 mΩ

ISC(min): VSC(min) / RSHUNT(max) = 0.45 V / 28 mΩ = 16.1 A

ISC(typ): VSC(typ) / RSHUNT(typ) = 0.5 V / 26 mΩ = 19.2 A

POUT =

IDC_AVG = (POUT/Eff) / VDC_Link = 6.5 A

PSHUNT = (I2DC_AVG  RSHUNT  Margin) / Derating Ratio = (72  0.026 
1.2) / 0.7 = 1.88 W (Therefore, the proper power rating of shunt resistor is
over 2.0 W)
=
0.9  300  7  0.8 = 1852 W
To prevent malfunction, it is recommended that an RC filter be inserted at the CSC pin.
To shut down IGBTs within 2 µs when over-current situation occurs, a time constant of
1.5 ~ 2 µs is recommended.
7
RD-407 • Rev. 0.0.1
Isolation distance
between high voltage
block and low voltage
block should be kept
+5V
+15V
/FO
VTS
101
101
101
ES1J
ES1J
ES1J
101
202
101
101
101
101
101
101
Z24V 0.5W
Z24V 0.5W
Z24V 0.5W
Capacitor and Zenner diode should
be locate closely to terminal
VIN(WH)
VIN(WL)
VIN(VH)
VIN(VL)
GND
The capacitor between
VCC and COM should be
placed to SPM as close
as possible
From Power
Source
To MCU
From Power
Source
To MCU
VIN(UL)
35V
35 V
VIN(UH)
Signal GND Copper
220 uF
33uF
35 V
33uF
8
35 V
Figure 3.
33uF
Z24V 0.5W
The VIN RC filter should
be placed to SPM as
close as possible
VB(U)
VB(V)
VB(W)
CSC
VF
COM
VDD
VIN(UH)
VIN(VL)
VIN(VH)
VIN(WL)
VIN(WH)
)
VIN(UL)
P
U,VS(U)
P
Main Electrolytic
capacitor
Snubber
capacitor
N
The main electrolytic capacitor
should be placed to snubber
capacitor as close as possible
Power Source Copper
Connect to
Motor
Shunt
resistor
Power GND Copper
Wiring between Nu, Nv, Nw
and shunt resistor should be
as short as possible
Place Sunbeber
capacitor
between P and
N and closely
to terminal
CSC Wiring should be as
short as possible
202
V,VS(V)
W,VS(W)
NU
NV
NW
It is recommended to connect Signal GND and Power GND at
only a point. (Not copper pattern and don’t make a loop in
GND pattern) And this wiring should be as short as possible.
3.5. Print Circuit Board (PCB) Layout Guidance
PCB Layout Guidance
RD-407 • Rev. 0.0.1
4. Related Resources
FNA51560T3 Motion SPM® 55 Series
FNB50560T1 Motion SPM® 55 Series
FNA51060T3 Motion SPM® 55 Series
AN-9096 Motion SPM® 55 Series User Guide
\
Reference Design Disclaimer
Fairchild Semiconductor Corporation (“Fairchild”) provides these reference design services as a benefit to our customers. Fairchild has made a good
faith attempt to build for the specifications provided or needed by the customer. Fairchild provides this product “as is” and without “recourse” and
MAKES NO WARRANTY, EXPRESSED, IMPLIED OR OTHERWISE, INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Customer agrees to do its own testing of any Fairchild reference designs in order to ensure design meets the customer needs. Neither Fairchild nor
Customer shall be liable for incidental or consequential damages, including but not limited to, the cost of labor, requalifications, rework charges, delay,
lost profits, or loss of goodwill arising out of the sale, installation or use of any Fairchild product.
Subject to the limitations herein, Fairchild will defend any suit or proceeding brought against Customer if it is based on a claim that any product
furnished hereunder constitutes an infringement of any intellectual property rights. Fairchild must be notified promptly in writing and given full and
complete authority, information and assistance (at Fairchild’s expense) for defense of the suit. Fairchild will pay damages and costs therein awarded
against Customer but shall not be responsible for any compromise made without its consent. In no event shall Fairchild’s liability for all damages and
costs (including the costs of the defense by Fairchild) exceed the contractual value of the products or services that are the subject of the lawsuit. In
providing such defense, or in the event that such product is held to constitute infringement and the use of the product is enjoined, Fairchild, in its
discretion, shall procure the right to continue using such product, or modify it so that it becomes noninfringing, or remove it and grant Customer a credit
for the depreciated value thereof. Fairchild’s indemnity does not extend to claims of infringement arising from Fairchild’s compliance with Customer’s
design, specifications and/or instructions, or the use of any product in combination with other products or in connection with a manufacturing or other
process. The foregoing remedy is exclusive and constitutes Fairchild’s sole obligation for any claim of intellectual property infringement and Fairchild
makes no warranty that products sold hereunder will not infringe any intellectual property rights.
All solutions, designs, schematics, drawings, boards or other information provided by Fairchild to Customer are confidential and provided for
Customer’s own use. Customer may not share any Fairchild materials with other semiconductor suppliers.
9
RD-407 • Rev. 0.0.1

Fairchild Reference Design RD-407 www.fairchildsemi.com

Transcription

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