May 3 - Illinois Institute of Technology

Illinois Institute of Technology
Extra Credit Lab 9
Switches, Transistors, and Circuits
CS 350: Computer Organization & Assembler Language Programming
Due Wed Apr 29 *
[Solved]
This lab is optional; if you turn it in, its score will replace your lowest lab score
(unless it is your lowest lab score, in which case we'll ignore it).
A. Why
• We can represent binary data using voltage and on/off switches; transistors act
as switches; logic gates represent logical computations. Combinatorial logic
circuits correspond to pure (state-free) calculations on booleans.
• Storage elements are the basic circuits that store data, which is used in logic
circuits that have a state (i.e., use memory).
B. Outcomes
After this lab you should be able to
• Read and write simple voltage and transistor-level circuit diagrams.
• Translate between simple combinatorial logic
circuits and boolean expressions.
• Recognize whether a circuit can be said to
remember or store data.
• Describe how R-S latches work.
A
B
C
For Problems 1 – 4, consider the voltage diagram to
the right; the inputs are A, B, and C and the output
B
is Z. (If you're confused about which switches are
p-type transistors and which are n-type, re-read the
part of the lecture notes on CMOS circuits.)
Z
C. Problems
*
A
C
Plus possible 2-day extension for attending lab Apr 30 or May 1
CS 350: Comp Org & Asm Pgm’g
–1 –
© James Sasaki, 2015
Illinois Institute of Technology
1.
Extra Credit Lab 9
[21 = 7 × 3 pts] Complete the table below, which describes when the output Z
is connected to power and/or ground. The table should have eight rows.
A
B
C
Power to Z
0
0
0
Y
0
0
1
Z to Ground Circuit state
N
Z = 1
…
1
1
1
2.
[8 pts] State a combination of inputs A, B, and C that causes a short circuit;
redraw the voltage diagram indicating which switches are open/closed for these
values of A, B, and C.
3.
[6 pts] Consider the three n-type transistors. If we swap two of them, we’ll get
a purely logical circuit (one without short or open circuits). Which two? (I.e.,
A and B, B, and C, or A and C ?)
4.
[9 pts] Redraw the voltage diagram as a transistor diagram. (Show the
transistors after being swapped in the previous question.)
5.
[10 pts] Take the logic P
NOR
circuit diagram to the Q
right and label its
wires with boolean
expressions describing
AND
the outputs of the
R
different gates. Do a
S
direct translation
(don't simplify the expressions as you go).
6.
OR
NAND
Z
OR
[10 = 2×5 pts] (a) Using logical transformations (such as distribution and
DeMorgan's laws), translate ¬(X̅ ̅ + Y̅ )̅ + ¬(X + Z) to full DNF (show the
transformations). (b) Draw a PLA implementation of your expression from
part (a) [you can omit unused AND gates].
CS 350: Comp Org & Asm Pgm’g
–2 –
© James Sasaki, 2015
Illinois Institute of Technology
7.
Extra Credit Lab 9
[12 = 3×4 pts] Consider the circuit to the right. X
(a) Describe the new value of Y as a function of
X and the current value of Y. (b) When (if ever)
OR
Y
does this circuit have a logically stable values for Y? A logically unstable
value for Y ? (c) Can this circuit be used to remember a bit?
8.
[24 = 8×3 pts] Consider the following partial statements about R-S latches.
Complete each of (a) – (d) by matching it with one or more of (A) – (C).
Similarly, match each of (e) – (h) with one or more of (D) – (H).
(a) Q₀ Q̅ ̅₁ represents …
(A) an output of logical true
(b) Q̅ ₀̅ Q ₁ represents …
(B) an output of logical false
(c) Q₀ Q₁ represents …
(C) neither logical true or false
(d) Q̅ ₀̅ Q̅ ̅₁ represents …
(D) Q₀ Q̅ ̅₁ is stable
(e) If R S then …
(E) Q̅ ̅₀ Q₁ is stable
(f) If R̅ S
̅ then …
(F) Q₀ Q̅ ̅₁ → Q₀ Q₁ → Q̅ ̅₀ Q₁
(g) If R S̅ ̅ then …
(G) Q̅ ̅₀ Q₁ → Q₀ Q₁ → Q₀ Q̅ ̅₁
(h) If R̅ ̅ S̅ ̅ then …
(H) all three of Q₀ Q̅ ̅₁ and Q̅ ̅₀ Q₁ and Q ₀ Q ₁ →
Q₀ Q₁, which is stable
Turning in this lab
You're certainly welcome to write up your answers using a drawing program and
submit a pdf to Blackboard. You may also write everything on paper and submit
an electronic scan to Blackboard. Or you may hand in the paper at lecture on
Wed Apr 29 or at Lab on Thu Apr 30 or Fri May 1, or to the instructor’s mailbox
in the CS office [SB 236] (but only when the office is open, during regular business
hours).
CS 350: Comp Org & Asm Pgm’g
–3 –
© James Sasaki, 2015
Illinois Institute of Technology
Extra Credit Lab 9
Lab 9 Solution
1.
2.
3.
(Transistor/voltage circuit states)
A
B
C
Power to Z
Z to Ground Circuit state
0
0
0
Y
N
Z=1
0
0
1
Y
N
Z=1
0
1
0
Y
Y
Short circuit
0
1
1
N
Y
Z=0
1
0
0
N
N
Z=0
1
0
1
N
Y
Z=0
1
1
0
N
Y
Z=0
1
1
1
N
Y
Z=0
A̅ ̅ B C̅ ̅ causes a short circuit. (There's a PowerA
to-Z connection when A̅ (̅ B̅ ̅ + C̅ )̅ and a Z-toGround connection when B + A C, so when
(A̅ (B̅ ̅ + C̅ )̅ )(B + A C) holds (i.e., A̅ ̅ B C̅ )̅ ,
B
there's a short circuit.)
Swapping the n-type transistors for A and B
will get rid of the short circuit. (Not asked:
B
Swapping their p-type transistors works also; it
would make Z = B̅ (̅ A̅ ̅ + C̅ )̅ .)
CS 350: Comp Org & Asm Pgm’g
–4 –
C
Z
A
C
© James Sasaki, 2015
Illinois Institute of Technology
4.
Extra Credit Lab 9
(Transistor diagram)
A
C
B
Z
B
A
C
5.
(Labeled logic gate circuit)
P
NOR
Q
P+Q
P+Q+Q R
OR
NAND
QR
AND
R
¬(P+Q+Q R) (Q R+S)
OR
S
Z
Q R+S
6a. ¬(X̅ ̅ + Y̅ )̅ + ¬(X + Z) = X Y + X̅ ̅ Z̅ ̅ (by DeMorgan's law, twice). This is in
DNF but not full DNF; to get full DNF, we have to add (Z + Z̅ )̅ to the first
term and (Y + Y̅ )̅ to the second term:
X Y + X̅ ̅ Z̅ ̅
= X Y (Z + Z̅ ̅) + X̅ ̅ (Y + Y̅ ̅) Z̅ ̅
= X Y Z + X Y Z̅ ̅ + X̅ ̅ Y Z̅ ̅ + X̅ ̅ Y̅ ̅ Z̅ ̅
CS 350: Comp Org & Asm Pgm’g
–5 –
© James Sasaki, 2015
Illinois Institute of Technology
Extra Credit Lab 9
6b. The PLA implementation is below. (For fun, it includes the unconnected
AND gates).
X
Y
Z
AND
X
Y
Z
AND
X
Y
Z
AND
X
Y
Z
AND
OR
X
Y
Z
AND
X
Y
Z
AND
X
Y
Z
AND
X
Y
Z
7.
AND
(a) The new Y = X + Y̅ ̅. (b) If X = 1, then Y settles at 1, but when X = 0,
Y logically oscillates between 0 and 1. (c) The circuit does not remember a
bit: It only has one stable state.
CS 350: Comp Org & Asm Pgm’g
–6 –
© James Sasaki, 2015
Illinois Institute of Technology
8.
Extra Credit Lab 9
(Statements about R-S latches.)
(a) Q₀ Q̅ ₁̅ represents …
(A) an output of logical true
(b) Q̅ ₀̅ Q₁ represents …
(B) an output of logical false
(c) Q₀ Q₁ represents …
(C) neither logical true or false
(d) Q̅ ₀̅ Q̅ ̅₁ represents …
(C) neither logical true or false
(e) If R S then … (D) Q₀ Q̅ ₁̅ is stable and (E) Q̅ ₀̅ Q₁ is stable
(f) If R̅ S
̅ then … (E) Q̅ ₀̅ Q₁ is stable and (F) Q ₀ Q̅ ̅₁ → Q₀ Q₁ → Q̅ ₀̅ Q₁
(g) If R S̅ ̅ then… (D) Q ₀ Q̅ ̅₁ is stable and (G) Q̅ ₀̅ Q₁ → Q₀ Q₁ → Q₀ Q̅ ₁̅
(h) If R̅ ̅ S̅ ̅ then … (H) all three of Q₀ Q̅ ₁̅ and Q̅ ₀̅ Q₁ and Q ₀ Q ₁ → Q ₀ Q ₁, which
is stable
CS 350: Comp Org & Asm Pgm’g
–7 –
© James Sasaki, 2015