forbidden pattern free codec in crosstalk elimination

Transcription

International Journal of Advances in Applied
Science and Engineering (IJAEAS)
ISSN (P): 2348-1811; ISSN (E): 2348-182X
Vol. 2, Issue 4, Dec 2015, 01-09
© IIST
FORBIDDEN PATTERN FREE CODEC IN CROSSTALK ELIMINATION
USING NAT, OTEE, SEE METHODS
1
VANGA SRAVANTHI , G.ANAND BABU
2
1
PG Student (M.Tech), Dept. Of ECE, at Universal college of Engineering & Technology, Guntur
2
Assistant Professor, Dept. Of ECE at Universal college of Engineering & Technology, Guntur
ABSTRACT— Code words designed to eliminate crosstalk show a highly structured nature. Code words with common most significant bit patterns can
be classified into various sets. Cardinality of each set can be mathematically determined. During every time frame, the codeword is calculated using the data
word using a graph-based recursive procedure. The process is formally introduced in the mentioned Algorithms in this paper. Real-time on-chip
implementation of encoder and decoder can be achieved by backtracking such a procedure so that the code words can be formed and mapped in a fast and
effective manner without explicitly enumerating them. The pipelined architecture of encoder/decoder results in an implementation that avoids stalling of a
microprocessor due to codec delay. The procedure described in this paper can be extended to implement many different kinds of encoding schemes.
Implementation of three such codes is described in this paper.
KEYWORDS—Crosstalk, Forbidden Pattern Free, Fibonacci series .
I. INTRODUCTION
With shrinking feature size and increasing frequency,
power dissipation on data bus has become the most
predominant factor than the power dissipation in other parts of
the circuitry. The large intrinsic capacitance associated with
buses is responsible for a substantial fraction (approx 40%) of
total power dissipated, because the bus power dissipation is
proportional to switching activity. The main disadvantage of
the existing power aware encoding schemes such as Bus
Invert and Bus Invert Transition Signaling is the extra bus line
used to indicate the receiver that the data is encoded or
uncoded.
A methodology has been proposed in this project to get
rid of this extra bus line. To support this claim, detailed
implementation of such additional logic is presented. A
logical model of data buses is presented and a family of
techniques is proposed that can reduce average power
consumption of the bus by 34% With new implemented
technique defined, we present technique for the synthesis of
encoding and decoding interface logic that minimizes the
average number of transitions on heavily-loaded global bus
lines at no cost in communication throughput. The
distinguishing feature of our approach is that it does not rely
on designer’s intuition, but it automatically constructs lowtransition activity codes and hardware implementation of
encoders and decoders, given information onward-level
statistics. We propose an accurate method that is applicable to
low-width buses, as well as approximate methods that scale
well with bus width. The advent of portable digital devices
such as laptop personal computers has made low power
CMOS circuit design an increasingly important research area.
It has been shown that in CMOS technology a large portion of
power dissipation on chip is due to dynamic power
consumption. In whole system buses are major culprit for
dynamic power dissipation. OFF-CHIP and ON-CHIP global
bus lines in very large scale Integrated (VLSI) circuits are
generally loaded with large Capacitances, approximately three
orders of magnitude larger than the average on-chip
interconnects capacitance.
As Dynamic power dissipation is directly proportional to
the capacitance power consumed by off-chip driving becomes
dominant as devices are scaled down, because off-chip
capacitance does not depend on process technology, but
depends on the package and printed circuit board (PCB)
technologies. OFF chip buses accounts 60% of total power
dissipation. Further because of shrinkage of technology we are
entering a system on chip era and in these applications it is
very much important to save the power dissipation of buses.
Since the power consumption is proportional to the switching
International Journal of Advances in Engineering and Applied Science (IJAEAS) Vol-2 Iss-4, 2015
1
Forbidden Pattern Free Codec In Crosstalk Elimination Using Nat, OTEE, See Methods
activity, thus reducing the bus switching in an efficient way to
reduce the bus power consumption.
Based on this some basic techniques are available in
literature like BI (bus invert), BITS (bus invert transition
signaling) are the most commonly used. But there use is
limited because of extra line needed to indicate the receiver
that data is encoded or uncoded. The extra bus line used in
these coding makes the coding difficult to use in real circuit
design because it implies changes to the interface specification
of the chip. Also this extra bus line takes extra area also.To
get rid from this problem a methodology has been proposed
here which reduce the switching activity on the buses without
the need of extra bus line and also encoder and decoder has
very small hardware which itself consume very less power. In
this paper we compared the result of BI and BITS with our
new technique and the hardware of new technique is also
presented.
Once negligible, capacitive crosstalk has become a major
determinant of the total power consumption and delay of onchip busses. Figure 1 illustrates a simplified on-chip bus
model with crosstalk. In the figure, CL denotes the load
capacitance, which includes the receiver gate capacitance and
also the parasitic wire-to-substrate parasitic capacitance. CI is
the inter-wire coupling capacitance between adjacent signal
lines of the bus. In practice, this bus structure is typically
modeled as a distributed RC network, which includes the nonzero resistance of the wire as well It has been shown that for
DSM processes, CI is much greater than CL [61]. Based on
the energy consumption and delay models given in the bus
energy consumption can be derived as a function of the total
crosstalk over the entire bus. The worst case delay, which
determines the maximum speed of the bus, is limited by the
maximum crosstalk that any wire in the bus incurs. It has been
shown that reducing the crosstalk boosts the bus performance
significantly Different approaches have been proposed for
crosstalk reduction in the context of bus interconnects. Some
schemes focus on reducing the energy consumption, some
focus on minimizing the delay and other schemes address
both.
The simplest approach to address the inter-wire crosstalk
problem is to shield each signal using grounded conductors.
Khatri et al. in [61, 62] proposed a layout fabric that
alternatively inserts one ground wire and one power wire
between every signal wire, i.e., the wires are laid out as . . .
VSGSVSGSVS . . . , where S denotes a signal wire, G
denotes a ground wire and V denotes a power wire. Any
signal wire has a static (V or G) wire on each side, and hence,
when it switches, it needs to charge a capacitance of value of
2CI . This fabric also enforces a design rule that metal wires
on a given layer run perpendicular to wires on layers above or
below. The fabric has the advantage of improved
predictability in parasitic capacitance and inductance. It
automatically provides a low resistance power and ground
network as well. Such a fabric results in a decrease in wiring
density.
Figure 1 On-Chip Bus Model with Crosstalk
II. BUS ENCODING FOR CROSSTALK AVOIDANCE
Figure 2 shows the data bus encoding and decoding, here
because data lines are always bi-directional so we need
encoder and decoder on both the sides, when source wants to
transmit a data then it will pass into the encoder, encoder will
encode the data so that number switching activity will reduce.
And at the other end it will pass through the decoders, which
decode data in original form. And we are getting original data
at the receiver side with much reduction in switching power.
Electrical Design Methodology Fully-hierarchical verilog
coding in RTL-to-netlist generation by synthesis has been
done in this project. To design this project we followed the
top-down methodology. Firstly the idea of whole system was
made on paper and then the system was further divided into
hierarchical components which are encoder and decoder.
Further these components were divided into the basic
components. These encoder and decoder has been designed
which can be used where data is being transmitted from
source to destination. this encoder will encode the data before
placed onto data bus in such a way so that number of
transition will reduce hence it will save switching power
dissipation depending on the number of switching reduction.
And other side decoder will decode the data into original
form. These encoder and decoder can be used for off chip data
2
transfer also. It is not a separate chip; it can be a part of the
system
Figure 2 Basic steps in on bus encoding
Compared to an uncoded bus, a crosstalk avoidance
encoded bus requires an encoder on the transmitter side and a
decoder on the receiver side. The original data is the input to
the encoder and is referred to as the data word, while the
output of the encoder is referred to as the codeword in this
thesis. The input to the decoder is the codeword, and its output
is the recovered data word
Typically, the number of bits of the codewords is higher
than that of the datawords, i.e., m > n. This is not always the
case, however, as we will show in Chap. 6. The additional
wires used for a coded bus are considered as area overhead
because of the additional routing space these wires occupy.
Note that the area of the encoder and decoder (CODEC)
circuit are not included in the calculation of the area overhead.
Instead, the encoder and decoder size are evaluated separately.
The basic operation of on-chip bus encoding for crosstalk
avoidance is illustrated in An n-bit input vector Vunc =
b1b2 · · · bn is first encoded into an m-bit encoded vector,
Venc = d1d2 · · · dm, which is transmitted over the bus. The
received vector is decoded to recover the original data
b1b2 · · · bn. The encoded data consists of specially designed
codewords which guarantee that some high classes of
crosstalk transition patterns never occur. By eliminating these
classes of crosstalk patterns, the bus can be operated at a
higher speed, while consuming lower power. Such techniques
to improve bus speed/power are referred to as Crosstalk
Avoidance Encoding techniques, and the encoded data are
referred to as Crosstalk Avoidance Codes (CACs).
This allows us to evaluate the code efficiency and CODEC
efficiency separately.
OH(n) = (m – n)/n
In this monograph, we use the following set of rules as unified
criteria to evaluate the the performance of different CACs:
• Bus speedup: The ratio of the maximum speed of the coded
bus to the maximum speed of the uncoded bus.
• Area overhead: The ratio of the additional wires needed for
the coded bus to the number of wires of the original uncoded
bus.
• CODEC performance: This is quantified by measuring the
complexity, power consumption and speed of the CODEC.
• Bus power: The power saving achieved by the coded bus
compared to the uncoded bus.
Forbidden Pattern Free CAC
The forbidden pattern free codes are the most area
overhead efficient 3C-free memory CACs [36]. These codes
guarantee that transitions between any two codewords satisfy
2−δj, j−1−δj, j+1 < 3 for all bits. The detailed design of the
code and its performance analysis are given as follows.
Code design
Definition Forbidden patterns are 3-bit binary patterns
vj−1vjvj+1 that satisfy vj−1 = vj+1 = vj . The only patterns that
satisfy Definition 3.1 are 010 and 101.
Definition A vector that contains no forbidden pattern in any
three consecutive bits is a forbidden-pattern-free (FPF) vector.
For example, 11100110 and 11000110 are FPF vectors,
11010011 and 11110110 are not FPF vectors.
If all vectors in a set are forbidden pattern free, transitions
among these vectors satisfy maxj(Ceff , j) = 2 × CI .
Theorem 1 states that if forbidden patterns are not allowed on
the bus, then max(Ceff ) = 2 × CI , i.e., the bus is 3C-free. It is
possible to prove Theorem 3.1 by an exhaustive examination
of all transition patterns. The following gives the
mathematical proof.
Proof We prove that both 4C and 3C transitions require
forbidden patterns on dj−1djdj+1. Let the bit patterns be vk
j−1vk j vk j+1 and vk+1 j−1 vk+1 j vk+1 j+1 in the kth and (k +
1)th cycles respectively.
• we know that for Ceff , j = 4 × CI , it is required that δj, j−1
= −1
3
and δj, j+1 = −1, i.e., vj−1 and vj transit in opposite directions
and vj
and these logic relations result in vk j−1 = vk j = vk j+1 and
vk+1 j−1 = vk+1 j = vk+1 j+1 . So in both cycles forbidden
patterns appear on dj−1djdj+1.
To generate a complete set of m-bit FPF codewords,
a simple-minded approach is to remove all codewords that
contains forbidden patterns from the 2m entries. However,
such an exhaustive search approach is impractical when m is
large. Instead, the FPF-CAC can be generated using an
inductive procedure Satisfied so that we can map each input
(n-bit) vector uniquely to one distinct output (m-bit) vector
that is an FPF vector. To minimize the area overhead, for a
given input bus size, n, we want to find the smallest m so that
Tg(m) ≥ 2n is satisfied
III.
0
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
Fig 3 Correlation graph of OTEE Fibonacci algorithm
OTEE,NAT,SEE CODEC DESIGN
OTEE Codec:
Opposite transition elimination encoding is the
codec does not contain the forbidden pattern in opposite
transition 10 & 01.the correlation graph is shown in the fig 3
.the Fibonacci algorithm is drawn at fig 3(a) and fig 3(b).the
Xilinx simulation result is shown in fig .7.
Fig 3(a) Encoder of OTEE
OTEE encoder & decoder block is implemented by using
fibonacii series. Here fibonacii series used is 3 2 1 1. the
xilinx simulation result is shown in fig .8
Fig 3(b) Decoder of OTEE
4
Numerical Example:
Fig 5(a) Encoder of NAT
The above numerical example is developed on Fibonacci
series .the j is the number of input bits of considered bus
width. The j series Fibonacci number is considered for
algorithm. Comparison of input data with series is done which
results the resultant binary and the other represents the next
input for the successive comparison.
Fig 5(b) Decoder of NAT
Numerical Example:
NAT Codec
Non adjacent codec minimizes the power of
transmission by reducing the number of one's in the
transition .the codec correlation graph is shown in fig 4 .as
well its Fibonacci algorithm is mentioned in fig 5(a) and
decoding 5(b).
SEE CODEC
Slowdown elimination codec is to remove the
forbidden pattern containing 101 and 010. As the crosstalk
was discussed the correlation graph was mentioned in the
fig 6.the code in discussed in the results section. Xilinx
simulation result is shown in fig 9.
Fig 4.Correaltion graph of NAT encoding
5
0
0
0
0
0
0
0
0
1
1
1
Fig 6 Correlation Graph of SEE
1
1
1
Fibonacci binary numeral system (FNS) was first
mentioned in the context of CAC designs by Mutyam in [7]. 1
The author proposed an inductive codeword generation 1
algorithm for the forbidden transition free code. The algorithm 1
is similar to those proposed in [6, 10]. However, [7] failed to
1
address the mapping scheme and CODEC design. We next
describe our FNS-based mapping, and the resulting CODEC 1
1
designs.
A numeral system is “a framework where numbers
are represented by numerals in a consistent manner” [5]. The
most commonly used numeral system in digital design is the
binary numeral system, which uses powers of two as the basis.
For a number v, its binary representation is defined in the
below Equation. The binary numeral system is complete and
unambiguous, which means that each number has one and
only one representation in the binary numeral system.
In order to reduce the Processing speed and to avoid
interference between consecutive bits we opt karnaugh maps
Method on reconfigurable hardware to avoid cross talk. The
functional table for the Proposed method is shown in the
Following Table.
Table 1 functionality of the OTEE, SEE and NAT
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
0
1
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
0
0
1
1
1
0
1
0
The above truth table is the functionality of the
OTEE SEE and NAT encoding and decoder continues as the
same in conventional .the outputs mentioned are k map
designed to obtain the equation and then to hardware
architectures
Output1
Ab\cs1s
2
00
01
11
10
kmap
00 00
0
1
1
01
1
1
01
0
11
0
1
1
1
11
1
10
1
10
0
1
1
1
1
10
10
encoding and decoder
Inp
1
0
0
0
0
Inp
2
0
0
0
0
Inp
3
0
0
0
1
S
1
0
0
1
0
S
2
0
1
0
0
Opt
1
0
0
0
0
Opt
2
0
0
0
0
Opt
3
0
0
0
0
Opt
4
0
0
0
1
Kmap equation
abs2  abcs1  cs1a  abcs1s2
For output 2
Kmap
Ab\cs1s 00
00
01
01
11
11
6
2
00
01
11
10
0
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
Equations
bound. We gave the corresponding modification in the
CODEC design as well.
Through this paper, we showed that data can be
coded to a forbidden pattern free vector in the Fibonacci
numeral system. We first give a straightforward
mapping algorithm that produces a set of FPF codes
with near-optimal cardinality
OTEE simulation
ab(cs 2)  a b(s1s 2)  s1s2b  cs1s2
For output3
Ab\cs1s 00
2
0
00
01
1
11
10
Equations
00
1
01
1
1
01
0
11
0
1
1
11
1
10
1
10
0
1
1
Fig 7. Simulation of OTEE for all the 3 input bus
1
inputs
NAT simulation
ab(cs 2)  ab(cs1)  a bcs1s2  abcs1s2  ab(cs1s 2)
For output 4
Ab\cs1s 00
2
0
00
1
01
11
1
10
1
00
1
1
1
01
1
01
0
1
1
1
11
0
1
11
1
10
1
1
1
1
10
0
1
Fig 8. Simulation of the NAT encoding for all the 4 input bus
SEE simulation
Equation
acs1  abcs2  abs1s 2  cs1s2b  cs1s2a  abcs 2
.
IV.
RESULTS AND CONCLUSIONS
This paper discusses various issues associated with
CODEC implementations. We proposed a modified coding
scheme that eliminates the MSB stage in the encoder and
simplifies the decoder side as well. The modification reduces
the total gate count and improves the CODEC speed. We can
further propose an improved coding scheme which yields a set
of FPF codes with maximum cardinality. The area overhead of
this optimal coding scheme matches the theoretical lower
Fig 9 Simulation result for the SEE encoding for 6 as given input
7
Table-2 Comparisons of Proposed Encoders
REFERENCES
1.
2.
Fig 10 Simulation result for the encoding based on reconfigurable
system
The above simulation is the codeword generated
by NFF simulation when input is 110 the output is 1001.
The above simulation is the codeword generated by NFF
simulation when input is 111 the output is 1010.
The area overhead of this coding scheme is near the
theoretical lower bound. The CODEC based on this
coding scheme is systematic and has very low
complexity. The size of the CODEC grows quadratic
ally with the data bus size as opposed to exponentially in
a brute forced implementation. Our systemic coding
scheme allows the code design of arbitrarily large busses
without having to resort to bus partitioning.
The three methods stated OTEE,NAT,SEE were
implemented in xilinx and the synthesized report has
been generated .the synthesis was done for 4 input data
bus .the lut count increases for certain extent of bus
width but later the count remains constant as the
Fibonacci series has an exponential increase.
Further implementation can be processed to decrease
the delay .as the front end process has been accurately
designed the backend process i.e. CMOS design is to be
concentrated .
3.
4.
5.
6.
D. Pamunuwa and H. Tenhunen, “Repeater insertion to
minimise delay in coupled interconnects,” in Proc. Int. Conf.
VLSI Design, Jan. 2001, pp. 513–517.
D. Rossi, C. Metra, A. K. Nieuwland, and A. Katoch, “New ECC
for crosstlk impact miimization,” IEEE Design Test Comput.,
vol. 22, no. 4, pp. 340–348, Jul.–Aug. 2005.
D. Rossi, A. K. Nieuwland, A. Katoch, and C. Metra, “Exploiting
ECC redundancy to minimize crosstalk impact,” IEEE Design
Test Comput., vol. 22, no. 1, pp. 59–70, Jan. 2005.
M. Ghoneima and Y. Ismail, “Delayed line bus scheme: A lowpower bus scheme for coupled on-chip buses,” in Proc.
ISLPED, Aug. 2004, pp. 66–69.
K. Karmarkar and S. Tragoudas, “Scalable codeword generation
for coupled buses,” in Proc. Design Autom. Test Eur., Mar.
2010, pp. 729–734.
“On-Chip Codeword Generation to Cope With Crosstalk” Kedar
Karmarkar, Student Member, IEEE, and Spyros Tragoudas,
Member, IEEE
S. Sinha, R. Kar, and A. K. Bhattacharjee, “Bus encoding
technique using forbidden transition free algorithm for crosstalk reduction for on-chip VLSI interconnect,” in Proc. ACE.
8. P. Subrahmanya, R. Manimegalai, V. Kamakoti, and M.
Mutyam, “A bus encoding technique for power and crosstalk
minimization,” in Proc. 17th Int. Conf. VLSI Design, 2004, pp.
443–448.
9. M. Mutyam, “Preventing crosstalk delay using fibonacci
representation,” in Proc. 17th Int. Conf. VLSI Design, 2004, pp.
685–688.
10. M. Mutyam, “Selective shielding: A crosstalk-free bus encoding
technique,” in Proc. IEEE/ACM Int. Conf. Comput. Aided
Design, Nov. 2007, pp. 618–621.
7.
8
AUTHOR’S PROFILE
Vanga Sravanthi is pursuing his Master degree
M.Tech in VLSID of ECE department at
Universal college of Engineering & Technology,
Guntur.
G.Anand Babu is working
as
an Assistant
Professor in at Universal college of Engineering
& Technology, Guntur. He has completed his
Masters from JNTUH. His area of interest
includes communications, signal and image
processing.
********
9

forbidden pattern free codec in crosstalk elimination

Transcription

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