Chapter 3 Semiconductor Memories

Transcription

Chapter 3
Semiconductor Memories
Jin-Fu Li
Department of Electrical Engineering
National Central University
Jungli, Taiwan
Outline





Introduction
Random Access Memories
Content Addressable Memories
Read Only Memories
Flash Memories
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
2
Overview of Memory Types
Semiconductor Memories
Read/Write Memory or
Random Access Memory (RAM)
Read Only Memory (ROM)
Random Access
Memory (RAM)
Non-Random Access
Memory (RAM)
•Static RAM (SRAM)
•Dynamic RAM (DRAM)
•Register File
•FIFO/LIFO
•Shift Register
•Content Addressable
Memory (CAM)
Jin-Fu Li, EE, NCU
•Mask (Fuse) ROM
•Programmable ROM (PROM)
•Erasable PROM (EPROM)
•Electrically EPROM (EEPROM)
•Flash Memory
•Ferroelectric RAM (FRAM)
•Magnetic RAM (MRAM)
3
Memory Elements – Memory Architecture
 Memory elements may be divided into the
following categories
Random access memory
Serial access memory
Content addressable memory
 Memory architecture
2m+k bits
row decoder
row decoder
2n-k words
row decoder
row decoder
column decoder
k
n-bit address
2m-bit data I/Os
Jin-Fu Li, EE, NCU
column mux,
sense amp,
write buffers
4
1-D Memory Architecture
S1
S2
S0
Word0
S1
Word1
S2
Word2
A0
S3
Decoder
S0
A1
Ak-1
Sn-2
Sn-1
Wordn-2
Sn-1
Wordn-1
Word2
Wordn-2
Wordn-1
m-bit
Input/Output
m-bit
Input/Output
n select signals: S0-Sn-1
Word1
S3
Sn-2
Storage
element
Word0
n select signals are reduced
to k address signals: A0-Ak-1
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Memory Architecture
S0
A0
A1
Ak-1
Wordi-1
Row Decoder
S1
Word0
Sn-1
A0
Aj-1
Wordni-1
Column Decoder
Sense Amplifier
Read/Write Circuit
m-bit Input/Output
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Block
Column
Row
Hierarchical Memory Architecture
Input/Output
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SRAM Block Diagram
[A. Pavlov and M. Sachdev, “Power-Aware
SRAM Design and Test”, 2008, Springer.]
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Address
Row Decoder
Conceptual 2-D Memory Organization
Memory Cell
Column decoder
Data I/Os
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9
Memory Elements – RAM
Generic RAM circuit
Bit line conditioning
Clocks
RAM Cell
n-1:k
k-1:0
Address
Sense Amp, Column
Mux, Write Buffers
write data
Jin-Fu Li, EE, NCU
Write
Clocks
read data
10
RAM – SRAM Cells
6-T SRAM cell
word line
bit
- bit
bit
- bit
4-T SRAM cell
word line
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11
RAM – DRAM Cells
4-T dynamic RAM (DRAM) cell
word line
bit
- bit
3-T DRAM cell
Read
Write
Read
data
Write
data
Jin-Fu Li, EE, NCU
12
RAM – DRAM Cells
1-T DRAM cell
word line
word line
Vdd or
Vdd/2
bit
bit
Layout of 1-T DRAM (right)
Vdd
word line
bit
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13
RAM – DRAM Retention Time
Write and hold operations in a DRAM cell
WL=1
+
on
Cs
+
WL=0
Input Vdd
-
+
off
Vs
Cs
-
Vs
Write Operation
Hold
Vs  Vmax  VDD  Vtn
Qmax  C s (VDD  Vtn )
Jin-Fu Li, EE, NCU
14
RAM – DRAM Retention Time
Charge leakage in a DRAM Cell
Vs(t)
WL=0
Vmax
IL
+
off
Cs
-
Minimum logic 1
voltage
V1
Vs(t)
th
t
dQs
)
dt
dVs
I L  C s (
)
dt
Vs
I L  C s (
)
t
C
t h | t | ( s ) Vs
IL
I L  (
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15
RAM – DRAM Refresh Operation
As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the
hold time is
50 10 15
t h
1  0.5s
9
110
Memory units must be able to hold data so long as the power is
applied. To overcome the charge leakage problem, DRAM arrays
employ a refresh operation where the data is periodically read from
every cell, amplified, and rewritten.
The refresh cycle must be performed on every cell in the array with a
minimum refresh frequency of about
1
f refresh
2t h
Jin-Fu Li, EE, NCU
16
RAM – DRAM Read Operation
WL=1
IL
+
on
Cbit
Cs
+
-
Vbit
-
Vs
Vf
Vf
Qs  C sV s
Qs  C sV f  CbitV f
Vf  (
Cs
)Vs
C s  Cbit
This shows that Vf<Vs for a store logic 1. In practice, Vf is usually
reduced to a few tenths of a volt, so that the design of the sense
amplifier becomes a critical factor
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17
RAM – SRAM Read Operation
Vdd precharge
precharge
precharge
bit, -bit
word line
word
data
- bit
bit
data
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18
Vdd-Vtn precharge
precharge
precharge
Vdd
bit, -bit
word line
word
data
- bit
bit
data
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bit, -bit
word
data
- bit
bit
load
V2
sense +
pass
sense -
V1
sense common
Jin-Fu Li, EE, NCU
pulldown
20
RAM – Write Operation
N5
N6
write data
word
write
N3
N4
word
- bit
write
bit
N1
bit, -bit
N2
cell, -cell
write data
Jin-Fu Li, EE, NCU
21
RAM – Write Operation
- bit
Pbit
5V -cell
bit
cell 0V
Nbit
- write
write
ND
PD
write-data
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RAM – Read Stability
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23
RAM – Write Stability
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24
RAM – Row Decoder
a<1> a<0>
word<3>
word<0>
word<2>
word<1>
word<1>
word<2>
word<0>
word<3>
a<1> a<0>
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25
RAM – Row Decoder
word
a1
a0
a0
a1
Complementary AND gate
a2
a3
Pseudo-nMOS gate
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26
RAM – Row Decoder
Symbolic layout of row decoder
output
Vss
Vdd
Jin-Fu Li, EE, NCU
Vss
27
RAM – Row Decoder
Symbolic layout of row decoder
Vdd
output
Vss
a3
-a3
a2
-a2
a1
-a1
a0
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28
RAM – Row Decoder
Predecode circuit
word<7>
word<6>
word<5>
word<4>
word<3>
word<2>
word<1>
word<0>
a2
a1
a0
Jin-Fu Li, EE, NCU
29
RAM – Row Decoder
Actual implementation
a0
a4
a3
a2
a1
word
-a0
clk
Pseudo-nMOS example
a0
word
a1
a2
en
Jin-Fu Li, EE, NCU
30
RAM – Column Decoder
bit<7>
bit<6>
bit<5>
bit<4>
selected-data
bit<3>
bit<2>
bit<1>
bit<0>
to sense amps and write ckts
-bit<7>
-bit<6>
-bit<5>
-bit<4>
-selected-data
-bit<3>
-bit<2>
-bit<1>
-bit<0>
a0
-a0
a1
-a1
a2
Jin-Fu Li, EE, NCU
-a2
31
RAM – Multi-port RAM
write
read0
read1
-rbit1 -rbit0 -rwr_data
rwr_data rbit0
-rbit1 -rwr_data
rwr_data rbit0
rbit1
write
read0
read1
Jin-Fu Li, EE, NCU
32
RAM – Expandable Reg. File Cell
wr-b addr<3:0>
rd-a addr<3:0>
rd-b addr<3:0>
write-data
write-data
read-data 0 read-data 1
write-enable(row)
read0
read1
Write-enable (column)
Jin-Fu Li, EE, NCU
33
Specific Memory – FIFO
Two port RAM
Write-Data
Read-Data
Write-Address
Read-Address
Write-Clock
Read-Clock
Full
Empty
FIFO Write (Read) address control design
WP (RP)
0
0
1
Write
(Read)
rst
clk
1
1
incrementer
Jin-Fu Li, EE, NCU
34
Specific Memory – LIFO
LIFO (Stack)
Require:
Single port RAM
One address counter
Empty/Full detector
Algorithm:
Address
Write: write current address
Address=Address+1
Read: Address=Address-1
read current address
Empty: Address=0
Full : Address=FFF…
Jin-Fu Li, EE, NCU
35
Specific Memory – LIFO
LIFO address control design
-1
0
1
0
decrementer
0
1
Write
1
1
rst
clk
incrementer
Empty
Read
Write
Full
Jin-Fu Li, EE, NCU
36
Specific Memory – SIPO
SIPO cell design
Read
Parallel-data
Sh-In
Sh-Out
Clk
-Clk
SIPO
Read
Sh-In
Clk
Jin-Fu Li, EE, NCU
37
Specific Memory – Tapped Delay Line
delay<5>
din
Clk
delay<4>
delay<3>
delay<2>
delay<1>
delay<0>
0
0
0
0
0
0
1
1
1
1
1
1 dout
32-stage SR
16-stage SR
8-stage SR
4-stage SR
Jin-Fu Li, EE, NCU
2-stage SR
1-stage SR
38
Read-Only Memories
 Read-Only Memories are nonvolatile
 Retain their contents when power is removed
 Mask-programmed ROMs use one transistor per
bit
 Presence or absence determines 1 or 0
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39
Non-volatile Memory – ROM
4x4 NOR-type ROM
Vdd
WL0
GND
WL1
WL2
GND
WL3
BL0
BL1
BL2
Jin-Fu Li, EE, NCU
BL3
40
Non-volatile Memory – ROM
4x4 NAND-type ROM
Vdd
BL0
BL1
BL2
BL3
WL0
WL1
WL2
WL3
Jin-Fu Li, EE, NCU
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ROM Example
 4-word x 6-bit ROM
 Represented with dot diagram
 Dots indicate 1’s in ROM
weak
pseudo-nMOS
pullups
A1 A0
Word 0: 010101
Word 1: 011001
Word 2: 100101
Word 3: 101010
2:4
DEC
ROM Array
Y5
Y4
Y3
Y2
Y1
Y0
Looks like 6 4-input pseudo-nMOS NORs
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ROM Array Layout
 Unit cell is 12 x 8 (about 1/10 size of SRAM)
Unit
Cell
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Row Decoders
 ROM row decoders must pitch-match with ROM
 Only a single track per word!
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44
Complete ROM Layout
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Building Logic with ROMs
 Use ROM as lookup table containing truth table
 n inputs, k outputs requires 2n words x k bits
 Changing function is easy – reprogram ROM
 Finite State Machine
 n inputs, k outputs, s bits of state
 Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
inputs
n
ROM Array
2n wordlines
DEC
inputs
n ROM k
s
outputs
k
s
state
k outputs
Jin-Fu Li, EE, NCU
46
Specific Memory – CAM
Content addressable memories (CAMs) play an
important role in digital systems and applications
 such as communication, networking, data compression,
etc.
Each storage element of a CAM has the hardware
capability to store and compare its contents with
the data broadcasted by the control unit
CAM types
 dynamic or static
 binary or ternary
Jin-Fu Li, EE, NCU
47
Difference Between RAM and CAM
Address
RAM
Data
R/W
Data
Hit
CAM
Cmd
Jin-Fu Li, EE, NCU
Address
48
CAM – Applications
CAM architecture
CAM Memory Array
NxM-bit words
Data
Match
Cache architecture
CAM
Match 0
Match 1
Data In
CAM Memory Array
NxM-bit words
Match 2
Match 3
Match 4
Match 5
Jin-Fu Li, EE, NCU
RAM
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Data I/Os
49
CAM – Architecture
Comparand Register
Responder
Memory Array
Valid Bit
Address
Input
Address Decoder
Mask Register
Hit
Address
Output
I/O Register
Jin-Fu Li, EE, NCU
50
CAM – Basic Components
Comparand Register
 It contains the data to be compared with the content of the memory
array
Mask Register
 It is used to mask off portions of the data word(s) which do not
participate in the operations
Memory Array
 It provides storage and search (compare) medium for data
Responder
 It indicates success or failure of a compare operation
Jin-Fu Li, EE, NCU
51
CAM – Binary Cell
NAND-type BCAM cell
NOR-type BCAM cell
bit
-bit
bit
-bit
WL
WL
-d
d
-d
d
M2
M1
M2
M1
Match
M3
Jin-Fu Li, EE, NCU
M3
Match
52
CAM – Ternary Cell
A ternary CAM (TCAM) cell stores one of the
following values
 0, 1, and X (don’t care)
A typical TCAM cell structure
 Let (QL,QR)=(CL,CR)=(0,1), (1,0), and (0,0) denote the
ternary data 0, 1, and X
WL
Vss
QL
QR
ML
CR
CL
Jin-Fu Li, EE, NCU
53
CAM – Ternary Cell
NAND-type TCAM cell
NOR-type TCAM cell
Jin-Fu Li, EE, NCU
54
CAM – Word Structure
bit[0]
bit[0]
bit[w-1]
bit[w-1]
Wi
1
0
Vdd
P
Mi
10
0
1
comparison logic
Jin-Fu Li, EE, NCU
55
CAM – Organization
CAM circuit
Match Data In
Read Data (Test)
Normal RAM Read/Write Circuitry
Hit
Match0
Match1
Match2
Match3
precharge
Jin-Fu Li, EE, NCU
56
Non-volatile Memory – Flash Memory
Flash memory
 A nonvolatile, in-system-updateable, high-density memory
technology that is per-bit programmable and per-block or perchip erasable
In-system updateable
 A memory whose contents can be easily modified by
the system processor
Block size
 The number of cells that are erased at the same time
Cycling
 The process of programming and erasing a flash
memory cell
Jin-Fu Li, EE, NCU
57
Flash Memory – Definition
Erase
 To change a flash memory cell value from 0 to 1
Program
 To change a flash memory cell value from 1 to 0
Endurance
 The capability of maintaining the stored information
after erase/program/read cycling
Retention
 The capability of keeping the stored information in time
Jin-Fu Li, EE, NCU
58
Basics
How can a memory cell commute from one state
to the others independently of external condition?
 One solution is to have a transistor with a threshold voltage that can
change repetitively from a high to a low state
 The high state corresponding to the binary value “1”
 The low state corresponding to the binary value “0”
Threshold voltage of a MOS transistor
 VT  K  Q' / Cox
 K is a constant depending on the gate and substrate material,
doping, and gate oxide thickness
 Q’ is the charge in the gate oxide
 Cox is the gate oxide capacitance
Jin-Fu Li, EE, NCU
59
Floating Gate Transistor
Floating gate (FG) transistor
Control Gate
CFC
Floating Gate
CFS
CFB
Source
CFD
Drain
Substrate
Energy band diagram of an FG transistor
Substrate
Floating
Gate
Jin-Fu Li, EE, NCU
Control
Gate
60
Flash Memory – Threshold Voltage
 When the voltages (VCG & VD) are applied to the control
gate and the drain, the voltage at the floating gate (VFG) by
capacitive coupling is expressed as
 V FG  Q FG  C FC VCG  C FD V D
C
C
C
 C  Ctotal  Ctotal  C total
C FD
total
FC
FS
FB
 The minimum control gate voltage required to turn on the
control gate is
C
Q
C
total
FG
FD
 VT (CG )  C VT ( FG )  C  C VD
FC
FC
FC
 where VT(FG) is the threshold voltage to turn on the floating gate
transistor
 The difference of threshold voltages between two memory
data states (“0” and “1” ) can be expressed as
 VT (CG )   QFG
C FC
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61
Flash Memory – Structures
[R. Micheloni, L. Crippa, and A. Marelli, “Inside NAND Flash Memories”, 2010, Springer.]
Jin-Fu Li, EE, NCU
62
Flash Memory – Structures
Basic
unit
Bit line
Bit line
WL 1
Select
gate
(drain)
WL 2
WL 1
Basic
unit
WL 2
WL 3
WL 3
WL 4
WL N
WL N
Select
gate
(source)
Source line
NOR structure
NAND structure
Jin-Fu Li, EE, NCU
63
Flash Memory – Program Operation
 Program operation of the Intel’s ETOX flash cells (NOR structure)
 Apply 6V between drain and source
 Generates hot electrons that are swept across the channel from source
to drain
 Apply 12 V between source and control gate
 The high voltage on the control gate overcomes the oxide energy
barrier, and attracts the electrons across the thin oxide, where they
accumulate on the floating gate
 Called channel hot-electron injection (HEI)
+12V
Control Gate
GND
+6V
Floating Gate
Source
Drain
Substrate
Jin-Fu Li, EE, NCU
64
Flash Memory – Erase Operation
 Erase operation of the Intel’s ETOX flash cells (NOR
structure)
 Floating the drain, grounding the control gate, and applying 12V to the
source
 A high electric field pulls electrons off the floating gate
 Called Fowler-Nordheim (FN) tunneling
GND
Control Gate
+12V
Floating Gate
Source
Drain
Substrate
Jin-Fu Li, EE, NCU
65
Flash Memory – Erase Operation
 Threshold voltage depends on oxide thickness
 Flash memory cells in the array may have slightly
different gate oxide thickness, and the erase
mechanism is not self-limiting
 After an erase pulse we may have “typical bits” and
“fast erasing bits”
VT
typical bit
fast erasing bit
log t
0
Jin-Fu Li, EE, NCU
66
Flash Memory – Read Operation
 Read operation of the Intel’s ETOX flash cells (NOR
structure)
 Apply 5V on the control gate and drain, and source is grounded
 In an erased cell, the VC>VT
 The drain to source current is detected by the sense amplifier
 In a programmed cell, the VC<VT
 The applied voltage on the control gate is not sufficient to turn it on.
The absence of current results in a 0 at the corresponding flash
memory output
+5V
GND
Control Gate
+5V
Floating Gate
Source
Drain
Substrate
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67
Flash Memory – Array
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68
Flash Memory – Dual-Plane NAND Flash
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69
Flash Memory – NAND Flash Organization
[C.-W. Chou and J.-F. Li, IEEE VLSI-DAT 2011.]
Jin-Fu Li, EE, NCU
70

Chapter 3 Semiconductor Memories

Transcription

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