AIM, IIT

Device-Circuit Co-Design,
Analog/Mixed-Signal/HF/HS Design & Testing
AIM, IIT-Bombay
December 2011
M. Shojaei Baghini
Associate Professor
Department of Electrical Engineering
IIT-Bombay
Outline
Overview of available expertise
Overview of research activities in the area of
device-circuit co-design
Overview of research activities in the area of
analog, mixed-signal and RF design
Facilities available in IIT-Bombay
Funding resources
Dec. 1, 2011
AIM, IIT-Bombay
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Available Expertise
o Device-circuit interaction in emerging
technologies
o Device design, modeling, efficient simulation
techniques and optimization
o Integrated circuit design, efficient simulation
techniques and optimization methodologies in
emerging technologies
o CMOS analog and mixed-signal design and
test for variety of emerging applications
o HF and HS CMOS/BiCMOS design and test
for variety of emerging applications
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Associated Faculty Members
Juzer Vasi (Process/Device/Modeling)
o V. Ramgopal Rao (Process/Device/Modeling)
o Dinesh K. Sharma (Process/Device/Design/Test)
o Arun C. Chnadorkar (Process/Device/Design)
o M. Shojaei Baghini (Device/Design/EDA/Test)
o Anil Kottantharayil (Process/Device/Design)
o Swaroop Ganguly (Process/Device/Modeling)
o Madhav P. Desai (Design/Verification/Test)
o Mahesh B. Patil (Modeling/Optimization/EDA)
o Shalabh Gupta (Design/Test)
o Jayanta Mukherjee (Design/Test)
o Girish Kumar (Design/Test)
o H. Narayanan (EDA)
o Sachin Patkar (EDA/High Performance Computing)
o
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Associated Ph.D./M.Tech./DD Students
Current Students
25 Ph.D. students (Mostly supported by
research funds)
o 30 M.Tech and DD students (also average per
year)
o
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Device-Circuit Co-Design –
Three Examples of ongoing Projects
• HV I/O, ESD and RF device and circuit
optimization (Collaborator: Intel Mobile
Communications)
• Ultra low-voltage logic design using TFETs
(Collaborator: Intel Mobile Communications)
• Novel HV devices (Collaborator: Maxim
Integrated Circuits)
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Example Project: HV I/O, ESD and RF device
and circuit optimization – Team Members
• IIT-Bombay
V. Ramgopal Rao, Maryam Shojaei, Dinesh K. Sharma
(faculty members)
Ankur Gupta, Peeyush S. Swain and Ketankumar Tailor
(Ph.D. students)
• Intel Mobile Communications
Mayank Shrivastava, Harald Gossner, Jens Schneider,
Christian Russ (all Ph.D.)
• Institute for Solid State Electronics, Vienna
University of Technology, Austria
S. Bychikhin, D. Pogany, E. Gornik
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Facts
Understanding physical phenomena is a requirement in
many physical systems.
To verify the understanding and make a unified model
well-calibrated models, matching measurement results,
are needed.
Many events though look simple but they can be
explained in many ways out of which majority may not be
correct.
Industry is interested in understanding and analysis,
increasing yield, improving productivity and novel costeffective solutions.
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HV I/O and ESD in Nanometer
Technologies - Motivation
SEM Image of failed device
Challenge: ESD reliability
trades with performance
as CMOS technology scales
down.
H. Gossner, Int. VLSI Design Conf. 2009.
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Experimental Techniques for ESD
Characterization - TLP
Transmission Line Pulse Testing
ECN, Nov. 2007
Transient Characterization
Avoiding Strong DC Self-Heating
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Experimental Techniques for ESD
Characterization - TIM
Transient Interferometric Mapping (TIM)
S. Voldman, ESD Physics and Devices: John Wiley & Sons, Ltd., 2004
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Comparison of HV Devices in Planar
CMOS Technology
Proposed device
- M. Shrivastava, M. S. Baghini, H. Gossner, V. R. Rao, Part I and Part II,
IEEE Trans. on ED, Feb. 2010.
- M. Shrivastava, H. Gossner, V.R. Rao, M.S. Baghini, United States
Patent , Application No: 12/408,839, 2008P51967US
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Simulation of HV Devices
• Sentaurus TCAD tool from Synopsys
• Device realization using well-calibrated
process simulation deck
• Calibration with measured data
• 2D and 3D simulations
• Comparison of measurement results of
fabricated devices with simulation results
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Simulation of HV Devices – Calibrating
Simulator Parameters and Models
Simulation of HV devices after
calibration
Calibration based on measurement
data
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Failure Model of STI DeMOS – Behavior of STI
DeNMOS Device Under ESD Conditions
• Technology: 65nm
• Realized for 1.8–5V I/O or HV CMOS applications up to 10V.
• Actual device on Si has a folded structure sharing N-Well region
between two fingers.
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Behavior of DeNMOS Device Under ESD
Conditions – TLP Measurements
Investigation, understanding and finding the
solution starts here!
Fails in the range of
1.3-1.7 mA/µ
µm
100ns TLP
Reversibility:
Up to 90% of IT2
Gate and substrate
bias lead to no
considerable
change.
M. Shrivastava, J. Schneider, M. S. Baghini, H. Gossner, V. R. Rao,
Proc. of IRPS 2009, Canada.
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3D TLP Simulation of STI DeMOS
Device
3D TLP (HBM) characteristics of STI DeNMOS
device at two different values of “DL”
(Simulation).
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TLP Simulation of STI DeMOS Device Conduction Current Density (A/cm2)
DL=200nm
Junction Breakdown
Initially the device current is dominated by junction breakdown.
The parasitic bipolar is yet not triggered at I=0.1 mA/µm.
M. Shrivastava , H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao,
IEEE Transactions on Electron Devices, September 2010.
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TLP Simulation of STI DeMOS Device Conduction Current Density (cont’d)
DL=200nm
Bipolar Triggering
The parasitic bipolar is triggered at 0.2 mA/µm.
Dec. 1, 2011
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TLP Simulation of STI DeMOS Device –
Space Charge (1/cm3)
• Junction Breakdown
DL=200nm
• Bipolar Triggering
• Space Charge
Formation
• Base Push-Out
• Impact Ionization
and Base Length
Modulation
• Thermal Failure
M. Shrivastava , H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao,
IEEE Transactions on Electron Devices, September 2010.
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TLP Simulation of STI DeMOS Device –
Base Push Out
Electric
Field
(V/cm)
Impact
Ionization
(cm−3.s−1)
Dec. 1, 2011
longer
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Outcomes (last 5 years)
• Solution to Industry problems
• 15 filed Indian and US patent applications
• 40 journal papers (IEEE TED and EDL, IEEE
TIM, Elsevier Journals, etc.)
• 80 conference papers (IEDM, IEEE-IRPS, IEEE
A-SSCC, EOS/ESD Symposium, IEEE ISQED
Details are available from:
http://www.ee.iitb.ac.in/~nanoe
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Overview of research activities in the area of
analog, mixed-signal and RF design
Test chips (fabricated and tested in last 5
years)
• Uni/Bi-directional low-power, PVT-compensated
high-speed CM signaling
• Fully integrated signal conditioning with on-chip
drivers, Ultra low-noise (50nV/Hz1/2) ULP (5.5 µA
INA) (0.18µm CMOS) (used in system
prototyping)
• Unidirectional low-power high-speed CM
signaling (0.18 µm CMOS)
• Process and Temperature Compensated Current
Reference Circuit
• 2GHz differential oscillator (0.18 µm CMOS)
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Overview of research activities in the area of
analog, mixed-signal and RF design (cont’d)
Test chips (fabricated and tested)
7. 4.2MHz comparator with automatic on-chip
offset compensation
8. 16.8 GHz Distributed oscillator (0.18 µm CMOS)
9. 3.1 GHz oscillator (0.18µm CMOS)
10. Three-channel ECG signal conditioning chips
with 66 µA current dissipation (0.35 µm CMOS)
(used in system prototyping)
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Outcomes of Research on Analog/Digital/MS/RF
Design and EDA (last 5 years)
• Solution to Industry problems
• One startup company
• 10 filed Indian and US patent applications
• 20 journal papers (IEEE, Elsevier Journals, etc. )
• 40 conference papers (IEEE A-SSCC, IEEE
ISCAS, IEEE ISQED)
Details are available from:
http://www.ee.iitb.ac.in/faculty.html
Dec. 1, 2011
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Facilities Available in IIT-BombayAnalog, Digital, Mixed-Signal and RF Design and Test
VLSI Design Lab
Design Environments (Complete Flow)
•Cadence Virtuso Custome IC Design Flow
(Anlaog/Mixed-Signal/RF Design, Simulation and
Layout and Verification Environment)
•MentorGraphics ICflow 2006.1
•Synopsys Galaxy
o Logic Synthesis Tools (ASIC)
• Cadence Encounter
• Synopsys Design Compiler
Hardware Accelarator
• IMAGE Hardware Emulator - IMAGE,
Powailabs
http://www.ee.iitb.ac.in/~vlsi/
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Hardware Acceleration
IMAGE 4 FPGA Board
Capacity: 5 to 100 million gate
Acceleration: From 100X to 1000X acceleration over pure
simulation for [Verilog, VHDL, mixed] language designs.
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Facilities Available in IIT-BombayDie Level Testing
40 GHz, 4 Probe SUSS Microtec pm5
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Facilities Available in IIT-BombayAnalog, Mixed-Signal and RF IC/System Test
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Facilities Available in IIT-BombayAnalog, Mixed-Signal and RF IC/System Test
Pulse Generator (Avtech
Electrosystems Ltd): 10V, 1nsec
DSA (Tektronix): 20GHz
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Funding resources
• DIT and DST, Government of India.
• IIT-Bombay
• Industry
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End of Presentation
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