WBS 1 3 Electronics WBS 1.3 Electronics KLM readout: RPCs

Transcription

WBS 1.3 Electronics
WBS
1 3 Electronics
KLM readout: RPCs, TARGETX + PCBs
Gary Varner
University of Hawai’i
2
WBS 1 3 Scope
WBS 1.3 Scope
• Readout electronics for the iTOP (WBS 1.2), KLM (WBS 1.4) detector (iTOP
(
)
(
reviewed separately)
– Design, prototype and evaluation of ASICs and Design prototype and evaluation of ASICs and
readout boards within Belle‐II DAQ environment
– Procurement of all components
P
t f ll
t
– Assembly, integration and test of subdetector
readout modules – Delivery to subdetector assembly sites
12/13/2013
Gary Varner, US Belle II pre‐CD‐2/3 KLM Readout Technical Review
3
WBS 1 3 Scope (2)
WBS 1.3 Scope (2)
• Firmware for real‐time ASIC operation and data flow control and monitoring g
• FPGA/DSP microcoding for waveform data reduction
• Documentation and support of ASICs and readout modules
• Low‐level software modeling of trigger (tsim) Low‐level software modeling of trigger (tsim)
and event buffer overflow prevention logic
12/13/2013
4
RPC readout upgrade
pg
Superlayer = 2× RPC sandwiched between “microstrip” planes
48 channels z
48 channels Φ
• Belle: 15 superlayers
• Belle II: 13 superlayers
Endcap‐KLM
 1 Motherboard => 150 channels
 7 Motherboards/Data Concentrator board
 2 Data Concentrator boards/quadrant
2 Data Concentrator boards/quadrant
Existing cables and crates will be re‐used.
Barrel‐KLM (13 RPC layers and 2 scintillator layers)
 1 superlayer => 1 Front‐End board => 96 channel
 13 Front‐End boards/crate
 2 cables/Front‐End board
2 cables/Front End board
 1 Data Concentrator board/crate
 2 scintillator layers/Concentrator board
 16 “octants” => 16 crates
12/13/2013
5
bKLM RPC Readout System
(Indiana Univ.)
•
•
•
•
•
•
 Same Data Concentrator board used in eKLM with only fiber inputs
 Cannot share backplane with cards that use VME signals (only power)
12/13/2013
•
System comprised of 16 crates.
y
p
Crate contains 13 Front‐End boards (FEB) and 1 Data Concentrator board
Boards are connected by standard VME backplane with repurposed signals – 5‐bits point‐
point for each FEB’s hit data plus shared signals for slow control.
C t
Crates are connected to the DAQ and Global t d t th DAQ d Gl b l
Trigger systems by way of Data Concentrator board.
Scintillator electronics connect to two data fiber
Scintillator electronics connect to two data fiber transceivers.
The FEB executes time‐to‐digital conversion (TDC) and hit time ordering.
The Data Concentrator prepares and transmits data to trigger system (augments time, matches hits/tracks), as well as buffering data to send to DAQ
DAQ system upon triggers.
i
6
RPC Front End Board
RPC Front‐End Board
• Two production Front‐End boards were manufactured.
• The boards were received on 12/14/2012
•
•
•
12/13/2013
THRESH
TDC CLR
DATA
J2
DISC.
CHANNELS
1-48
Spartan-6
Spartan
6
XC6SLX25
FPGA
CLK
BACKPLANE
INTFC
J1
SLOW
CTRL
TEST
PULSER
A
DATA
•
Contains 96 line receivers and discriminator channels.
Channels 1‐48 will connect to negative g
RPC pulses while channels 49‐96 connect to positive RPC pulses.
Discriminator threshold controlled by DAC.
Analog test pulser provides independent built in test of each channel.
T FPGA for discriminator control Two FPGAs
f di i i t
t l
and TDC generation.
THRESH
J3
DISC.
CHANNELS
49-96
SLOW CTRL
•
Spartan-6
XC6SLX25
FPGA
TEST
PULSER
CLK
ADDR
7
Existing Cables and FEB f
FEB from Belle I
B ll I
12/13/2013
8
Prototype Front End Board
Prototype Front‐End Board
•
•
•
•
•
Discriminator input polarity is jumper p p
y j p
selectable.
One board‐board connector is input (J3), the other is output (J2) allowing data to be moved between boards.
db
b d
The board‐board connectors are high‐speed so the signal integrity will be similar to final 96 channel board
96‐channel board.
JTAG, clock, and data are multiplexed so there is one master in the stack.
At least one board in stack may contain a
At least one board in stack may contain a Ethernet module (serial‐Ethernet device server).
Nano LANReach 3 Mbps Ethernet module with server.
12/13/2013
9
RPC Signals
Z0= 50 Ω
microstrip
Z0= 113 Ω
twisted pair
50 Ω
Length 5.1 – 6.1 m
50 Ω
Existing scheme (above) – NOTE ground at both ends of cable.
Voltage/noise externally imposed between these grounds will simply add to signal+threshold input to comparator. Not great.
Preferred scheme would break this ground connection at FEE boards:
Z0= 50 Ω
microstrip
Z0= 113 Ω
twisted pair
50 Ω
Length 5.1 – 6.1 m
50 Ω
50 Ω
12/13/2013
10
RPC Receiver/Discriminator
•Prototype TDC board discriminator circuit b dd
shown below
•Prototype circuit generated from lab tests yp
g
that generated scope captures on right
Input (P6247 probe, averaged)
Output @ threshold = 3.3 mV
12/13/2013
11
Prototype Front‐End Board Stack
•
•
A prototype board with ½ the channel count is stacked for increased channel count
Ethernet interface is used to receive control and transmit TDC data
Board 4
Board 3
Board 2
Board 1
•
•
12/13/2013
Data Flow
Master is on the bottom Master
is on the bottom
– JTAG and TDC clear connect here.
Data and control signals
Data and control signals are passed up through the stack.
12
Prototype Front End Board Stack Test Setup
Prototype Front‐End Board Stack Test Setup
• Function
Function generator provides 30 ns NIM pulse every 100 μs
generator provides 30 ns NIM pulse every 100 μs
• Two NIM modules generate ECL signals that are connected to twisted pair flat cable as used in Belle
• Second NIM module input is delayed by adding 8 ns cable sections
Second NIM module input is delayed by adding 8 ns cable sections
• Discriminator threshold set to 272 mV
12/13/2013
13
Prototype Front End Board Stack Test Results
Prototype Front‐End Board Stack Test Results
Boards 1 and 3
300
8 ns cable
16 ns cable
24 ns cable
250
Frequency
200
150
100
50
0
0
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4
8
12
16
20
TDC Difference (ns)
24
28
32
36
14
Data Concentrator Board
Data Concentrator Board
• Four Data Concentrator boards were manufactured.
Four Data Concentrator boards were manufactured.
• The boards were received 08/22/2013
•
•
•
•
One timing and trigger distribution (TTD) interface.
Transceivers for DAQ and trigger link
Seven SFP transceivers used for data fiber link input from scintillator layers – 2 barrel or 7 endcap.
Onboard clock for test without FTSW
One Virtex‐6 FPGA for data One Virtex‐6 FPGA
for data
processing – scintillator coincidence, RPC time ordering, and RPC trigger window.
12/13/2013
GTP
CLK
•
15
KLM Hardware Test Setup
KLM Hardware Test Setup
• Two Concentrator boards connected with fiber patch cords.
• One RPC board moved to each of 13 slots.
O RPC b d
dt
h f 13 l t
• Test data continuously transmitted and checked on each interface.
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16
FEB to Concentrator Data Transfer
FEB to Concentrator Data Transfer
45 Ω
“EYE DIAGRAM”
(P6247 probe)
(P6247 probe)
VME bus linee
• All FEE boards feed data to one concentrator board
q
y
• We require to do this transfer with minimal latency
• Use a simple, synchronous protocol
• Don’t share any resources
• → Thirteen independent point‐to‐point links is best
• But we should re‐use old backplane (VME‐J1)!
• → Dedicate 5 VME lines (selected by slot ID) for each FEE to 5 VME lines (selected by slot ID) for each FEE to
communicate to concentrator, and run them as fast as possible
• → GTL allows for proper termination and can run at over 100 MHz (total 775 MB/s to concentrator board)
• → Use diodes to isolate non‐driving boards
• Also: use NMOS mux to control the diodes & to lower costs (fewer GTL devices required)
• Concentrator board drives local clock to backplane, all boards (including concentrator) receive clock from backplane
g
• FEE boards skew their received clocks according to slot ID in order to deskew data received at concentrator board
OFF = 0.5 pF
45 Ω
12/13/2013
(P6247 probe)
17
KLM Hardware Test Status
KLM Hardware Test Status
• Major
Major hardware interfaces: backplane, serial optical, and hardware interfaces: backplane, serial optical, and
TTD.
• These interfaces have been tested for mechanical compatibility and electrical integrity:
• Backplane RPC Front‐End FPGA configuration.
• Backplane RPC Front‐End detector data.
B k l
RPC F
E dd
d
• Backplane RPC Front‐End UART status/control
• Nine serial optical links
Nine serial optical links
• These interfaces have not been tested:
• Timing and Trigger Distribution (Trigger and JTAG)
Timing and Trigger Distribution (Trigger and JTAG)
12/13/2013
18
KLM Hardware Test Results
KLM Hardware Test Results
• RPC
RPC Front
Front‐End
End Board Issues:
Board Issues:
• The ‐12V to 5V power supply requires a resistor value change and another capacitor to reliably turn‐on.
• The SERB signal series termination value incorrect.
• Copper and solder mask need to be removed from a resistor array keep out area.
out area.
• The front panel needs to re‐designed to use one without ESD pins.
• Data Concentrator Board Issues:
• An SFP cage pin interferes with an integrated circuit.
• Two reference designations are swapped in the silkscreen.
• The front‐panel cutout for the RJ45 connectors is wrong.
Th f t
l t t f th RJ45
t i
• The backplane clock feedback comparator needs to use a 3.3V supply.
12/13/2013
19
Single Prototype FEB Test Results
Channel Difference Histogram
120
100
Frequenccy
80
60
40
20
0
-4
-3
12/13/2013
-2
-1
0
Bin (TDC Counts)
1
2
3
4
o Setup
• Burst of 40 pulses with 30 ns width and 80 ns period.
• Input pulse amplitude after attenuation l
li d f
i
is 6.2 mV
• Discriminator threshold is 5.9 mV
o Results
• Channel 1 and 2 TDC difference does y
not vary more than 2 counts
• Suspect better results when channels are not connected together
20
Prototype FEB Performance
Prototype FEB Performance
•
•
EExisting design –
i i d i
no board stack
b d
k
• 4 ns time resolution
• 10 +/‐ 2 ns double pulse resolution
• 528 ns maximum single channel latency due processing and pipelining
• Simultaneous hit on each channel processed with 948 ns latency
• Simultaneous hit on 4 channels processed with 347 ns latency
• Data output is 8‐bit microsecond/board channel, followed 8‐bit discriminator channel, followed by 8‐bit TDC value
Board stack
• Single channel latency increases to (528+4)*4 = 2128 ns if Ethernet module is used.
l h
ll
(
)*
f h
d l
d
• Simultaneous hit latency will increase accordingly.
• Data output is 4‐bit board address then 8‐bit channel values followed by 8‐bit time values.
l
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21
Production Front End Board
Production Front‐End Board
•
•
•
•
•
12/13/2013
Contains 96 High performance differential line g p
receivers and discriminator channels.
Channels 1‐48 will connect to negative RPC pulses and channels 49‐96
and channels 49
96 connect to positive RPC connect to positive RPC
pulses.
Discriminator threshold controlled by DAC.
Analog test pulser to provide independent built in
Analog test pulser to provide independent built in test of each channel.
Two FPGAs:
• Create fine time (TDC)
• Time order hit TDC values
• Transmit TDC values to Concentrator board
22
Production Front End Board FPGA
Production Front‐End Board FPGA
•
•
•
Controls the discriminator threshold and test pulser
Controls
the discriminator threshold and test pulser
Creates fine time (TDC) with a resolution of 3.94 ns
Time orders TDC values to simplify intra‐layer coincidence finding on Data C
Concentrator board
b d
• Transmits TDC values to Data Concentrator board over custom backplane
TIME DIGITAL
TIME-DIGITAL
DISC 1
CHANNEL 1
TIME ORDER
COMPARE
BUFFER
PULSER
CONTROL
COMPARE
BUFFER
DISC 2
CHANNEL 2
CONTROL
COMPARE
BUFFER
COMPARE
BUFFER
BACKPLANE
INTERFACE
DATA
COMPARE
BUFFER
DISC 48
12/13/2013
CHANNEL48
COMPARE
BUFFER
THRESHOLD
CONTROL
23
Production Data Concentrator Board
Production Data Concentrator Board
•
•
•
•
12/13/2013
One timing and trigger distribution (TTD) O
i i
d i
di ib i (TTD)
interface.
Two transceivers for “standard” Belle‐II links (B2Link and GDL)
(B2Link and GDL)
Seven transceivers used for data fiber link input from scintillator layers – 2 barrel or 7 endcap.
One FPGA:
One FPGA:
• Implements nine serial interfaces
• Finds coincident hits in orthogonal strips gg y
and forwards to trigger system
• Buffers data for >5.2 μs
• Forwards events in trigger time window to DAQ system
24
Data Concentrator Board FPGA
Data Concentrator Board FPGA
•
•
•
•
•
Implements 7 serial interfaces for scintillator data
Fi d
Finds coincident hits in orthogonal scintillator strips
i id t hit i
th
l i till t t i
Time orders RPC data
Combines scintillator and RPC data for transmission to trigger and DAQ systems
Forwards events in triggered time windows of max 5.2 μs to DAQ
d
i i
d i
i d
f
system
•
•
•
12/13/2013
RPC data will always be y
coincident
Scintillator electronics forward trigger packet first and DAQ
p
packet (s) later
()
Scintillator trigger window found on SCROD using TTD
input
25
RPC Electronics Status
RPC Electronics Status
• Firmware (FPGA) development ongoing
(
)d l
y
g
• Currently testing Data Concentrator TTD
interface with FTSW
COPPER (PocketDAQ) setup is complete so
• COPPER (PocketDAQ) setup is complete so that the B2Link can be tested on Data Concentrator
• Layout and drawing updates associated with th
the previously listed hardware issues should i l li t d h d
i
h ld
take less than 160 hours (Brandon Kunkler).
12/13/2013
26
KLM scintillator upgrade
•
RPC-based
RPC
b d KLM ddemonstrated
t t d nice
i performance
f
att Belle
B ll (efficiency
( ffi i
endcap
d
>
90%, barrel ~ 99%, stable operation, low bg)
•
With SuperKEKB luminosity,
luminosity it is still possible to use RPC in the barrel,
barrel
however the efficiency of endcap KLM becomes unacceptably low due to high
neutron background and large RPC dead time.
Requirements to keep (and improve) KLM performance
Low dead time:  sec for a typical channel (strip) area 1000 cm2
Large acceptance:  95%
High efficiency: ~99% for MIP
Low bg (neutron bg + electronic noise)
Proposed solution
Scintillator based detector with WLS readout
Fast p
photodector: Si photo
diode in Geiger
p
g mode ((Hamamatsu MPPC))
Independent operation of x-y layers
27
Configuration
<1% of total square dead zone due to
inscription
p
of rectangular
g
strips
p in circle
(similar to RPC)
■
■
■
■
■
■
ONE ENDCAP KLM SECTOR LAYER
75 strips (4 cm width)/sector 16800 strips for F&B endcap KLM
16800 strips for F&B endcap KLM
the longest strip 2.8 m; the shortest 0.6 m
WLS fiber in each strip
SiPM t
SiPM at one fiber end fib
d
mirrored far fiber end
< 1% of total square dead zone due to support structure
+ insensitive area due to reflective cover 0.3%
~4% of total square dead zone due to cables
and frugality on short strips (similar to RPC)
12/13/2013
endcap
barrel
28
Arrangement and support
structure
5‐9 mm
Strips are arranged in segments (15
strips/segment 5 segment/layer)
Net of x-y I-bars, where segments are
inserted.
After installation of segments the
whole
h l structure is
i fixed
fi d to the
h existing
i i
frame with L-bars, screwed (welded) to
the frame.
P
Preamplifier
lifi boards
b d are fixed
fi d to the
h
frame.
Al (polyethylene) covers are screwed
t the
to
th net.
t
Cables are interlaid in the gap between
I-bars net and cover
y I‐bar
welding
at junction
frame
x I‐bar
12/13/2013
29
Cosmic muon test setup
triggers
SiPM
studied strips
mirrors
25cm
2.8m
30
Longitudinal profile of light yield
corrected for SiPM internal interpixel xtalk and non-perpendicular incidence
Far end efficiency depending on the
threshold
thickness=10 mm
= 7 mm
value in TDR
for both Fermilab and
Vladimir
Light yield is slightly better than reported
in TDR due to improved production
technology.
Setting threshold at 7.5
7 5 pixels: SiPM noise 
neutron bg rate even after 10 years of SiPM
irradiation!
31
2 assy methods
check geometrical compatibility with
support structure, electronics and cabling (fix
strip sizes) and rigity of the construction;
elaborate
l b t operations
ti
for
f mass production,
d ti
assembly and installation.
fiber cutting and milling of both ends
cover far end with silver shine
gluing near end in the SiPM holder
gluing fiber to the strip groove
cover
the grove with reflective
film
12/13/2013
32
Strips into segment gluing
gluing
l i 15 strips
t i on the
th polysterene
l t
substrates
b t t (both
(b th sides)
id )
air bag
b
strips
substrate planes
substrate planes
use air-bag
air bag press
press, that
provides pressure >1000
kg/segment
12/13/2013
33
Module assembly
Insert segments one by one in the
support net structure
Lift outer
t frame
f
to
t the
th nett plane
l
Screw net structure to the outer frame
Fix 150 SiPMs
Fix 10 preamplifier boards
Cabling
12/13/2013
34
34
Close-up view
polysterene substrate
status
Production November-December 2010
Cosmics tests January 2011
Transportation to KEK February 2011
Assembly at KEK March 2011
Installation April 2011
35
Requirements for electronics
Very moderate requirements for MuID
Main concern is to improve KL reconstruction using looser KL-cluster requirements.
Need to suppress random coincidences in x- and y- strips
- good time matching of x and y hits: scintillator time resolution ~ 1ns; keeping this
accuracy by read out and DAQ electronics allows to suppress bg
- amplitude information is useful: according to GEANT
GEANT-44 simulation particles from
hadronic showers release more energy in scintillator; also for SiPM calibration
- digitizer in the radiation safe place (access for replacement)
- need preamplifiers to avoid electronics noise (should be radiation hard)
- provide HV adjustment
Evaluation (oscilloscope on chip) board
with 1 GHz sampling
SiPM signal ~ 8 p.e.
from LED
from LED
12/13/2013
36
EKLM electronics
EKLM electronics consists of three parts:
- In-detector amplification;
- Digitalization;
- COPPER (common for all subdetectors).
Preamplifiers are required to avoid electronic noise: moderate amplification is sufficient.
Digitization is done outside the detector.
150 × IDL_10_004
BS_eKLM_amp_RevA
KLM R
Readout
d t
(150 channels)
10×2×34-cond
Ribb cables
Ribbon
bl
12/13/2013
37
Electronics development
All carrier boards (15 amplifiers on each) have been produced, testing at Wayne State
Assembled modules ready to test with Rev. 2 readout
radiation
d o hardness
d ess w
wass cchecked
ec ed at ITEP proton
p o o synchrotron
sy c o o (summer
(su
e 2011),
), Indiana
d
All barrel modules installed – to be tested in January with
Rev. 2 & then pre-production readout.
Digitization based upon the TARGET ASIC family,
family
developed for the CTA project.
Performance Requirements:
Common
• Operate within Belle‐II Trigger/DAQ environment
• >= 30kHz L1
• Gbps
Gb fiber Tx/Rx
fib
/
• COPPER backend
• Super‐KEKB clock/timing
l k/ti i
12/13/2013
39
Common (2)
• Belle2link for data
• Custom links for trigger data (common UT3 HW)
Custom links for trigger data (common UT3 HW)
12/13/2013
40
System Requirements (3)
y
q
• Belle‐like timing primitives for GDL (trigger)
New KLM New
KLM
trigger elements
12/13/2013
41
Performance Requirements (daq)
q
( q)
• High efficiency triggering, ns‐level timing
Setting threshold at 7.5 pixels: SiPM
noise  neutron bg rate even after 10
years of SiPM irradiation
A small degradation of the MIP detection
efficiency (99%  97% at 10 Belle
Belle-II
II years) is
due to smearing of the threshold by noise coadditon. Can be recovered by fitting the signal
p to waveform data in SRM FPGA.
shape
12/13/2013
42
Performance Requirements (trigger)
• Merge streams to reduce # of links
• Implement algorithms in a common trigger Implement algorithms in a common trigger
module (UT3)
• Trigger algorithm finds 2D track(s) in each l
h f d
k( )
h
projection
12/13/2013
43
Design Constraints
• Pre‐amps inside module
4x iterations of
Carrier Card design
Temp sensor for
each 15 ch.
12/13/2013
44
KLM Scintillator Readout (2)
• Waveform sampling to maintain/understand g
gain and MPPC response after neutron damage p
g
12/13/2013
45
Technical Status: Pre‐amplifiers
 will be installed inside the detector
 were tested for radiation hardness at
ITEP proton (200 MeV) beam.
Photo-electron peaks
obtained with
irradiated amplifier
Amplifiers
A
lifi gain
i andd noise
i measuredd
before (blue) and after (red) irradiation
No effect was observed with radiation doses 5
times higher than expected at Belle II.
12/13/2013
46
Technical Status: ASIC (1)
Initial TARGET design  BLAB architecture
Die Overview
Pre‐production TARGET specifications
p
p
• 16 channels
• 1‐2 GSa/s (cosmic, beam ~2.5GSa/s)
• 12‐bit digitization
12 bit di iti ti
• Samples stored, digitized in groups of 32
• 16k samples per channel (8us at 2GSa/s)
• Event sequencing/timing off‐chip [firmware] 12/13/2013
TSMC 0 25
TSMC 0.25m CMOS process
CMOS
47
Technical Status: ASIC (2)
• Sampling: 128
(2x 64) separate
transfer lanes
Recording in one set 64, R
di i
t 64
Very similar to transferring other BLAB:
(“ping‐pong”)
• 2x more channels
• No precision timing requirement
• Storage: 64 x 512 (32k per ch.)
ch )
• Wilkinson ADC (64 at once)
• 64
6 conv/channel
/ h
l (512
(
iin parallel)
ll l)
12/13/2013
48
Technical Status: SRM (1)
Though looks very different, same framework
same framework as iTOP readout
12/13/2013
49
Technical Implementation
h
• Pre‐amps and TARGET ASIC
Al
Depletion
Region
2 m
R 50
Substrate
Ubias
• 16 channels
• 10.5
10.5‐2.5
2.5 GSa/s GSa/s
• 10‐12‐bit digitization
Noise is 500kHz − 2MHz not a problem: • Samples stored, digitized in groups of 32
5 p.e. threshold reduces rate to < 1kHz • 16k samples per channel (8us at 2GSa/s)
16k samples per channel (8us at 2GSa/s)
while maintaining ~ 99% MIP efficiency
while maintaining ~ 99% MIP efficiency
• Event sequencing/timing off‐chip [firmware] 12/13/2013
50
First prototype (2011)
p
yp
• Rev. A module prototype
DAC_MON
(10x)
TARGET1 DC
(10x – replace with
TARGET3 DC)
SCROD
Re-package card as
9U form factor
12/13/2013
51
TARGET6 ASIC D i R i
Design Review
12‐OCT‐2012 @ SLAC
TARGET6 TARGET5 TARGET4
TARGET6 = TARGET5 + TARGET4 triggering
• No significant issues
• Agreed to release for fabrication
52
Scint. KLM Readout 36 HSLB FINESSE
36
HSLB FINESSE
9 COPPER
112+32 DAQ fiber transceivers
TARGET6
Dec. 3 submit 20k channels
20k
h
l
1.25k 16‐channel
Waveform sampling
(TARGET) ASICs
112+32 SRM
Pre‐amp Production
Complete by end of JFY
12/13/2013
FTSW for programming/ timing/trigger
Trigger is common with RPC/barrel :
Use a common
Use a common merge board
53
KLM/SciFi Preamp Test Setup
Example Optical Test Card
Test Setup Overview
Software Trigger
MPPC Dark Box
LED + MPPC Pair
Generate Test Pulses
Test Signals Sent to 16 Preamps
TARGET4 Pulse Sampling
Example Test Pulse
Preamplifier Testing Card
Test system uses TARGET4 based
readout to send either MPPC or
Emulated pulses to preamplifiers
Intended
I
d d to characterize
h
i KLM and
d
SciFi preamplifiers
54
Scintillating Fiber KLM Readout (v.2)
SCROD (same as TOP)
15‐channel Daughercards
15‐channel Daughercards
Ribbon cable connectors
12/13/2013
10 daughercards, 15 ch.
= 1 quadrant endcap
1
d
d
55
KLM Readout v3
Revised 10 Daughter Card Mother Board
Ribbon cables and HV distribution placed on separate RHIC board
RHIC Board
d
MPPC Signals
TARGET6 Daughter g
Card with Transformers
TARGET6 daughter cards TARGET6
daughter cards
with transformers for noise reduction
56
KLM Readout Test at Tsukuba Hall
•
Test Setup Layout
PC
USB
RHIC
Tested KLM MB + RHIC in Tsukuba Hall with assembled scintillator module
Used USB connection to SCROD with
Used USB connection to SCROD with command interpreter interface Verified power distribution, ASIC DAC control
on the motherboard
on the motherboard
Waveform sampling firmware is very preliminary, measured sample pedestal distribution with RMS of 2 5 ADC
distribution with RMS of 2.5 ADC
•
1
6
2
7
3
7
4
9
SCROD
•
Measured Sample Pedestal Distribution
5
10
HV + MPPC Ribbon Cables to KLM Module
ADC
57
KLM Readout Test at Tsukuba Hall
Example MPPC Pulse on TARGET6 Input
Example MPPC Pulse on TARGET6 Input
MPPC signals correctly routed to TARGET6 inputs on test setup
~100mV pulses @ 71.5V, ~6m cables
Coherent noise not observed
Trigger signals detected when MPPCs on
wide can be configured
o ~600ns
600ns wide, can be configured
•
•
•
58
EB1
EB0
EB2
EB3
BF2
BB4
RPC Readout
RPC Readout
BF0
BF5
Spartan-6
XC6SLX25
FPGA
CLK
BF7
BF6
TDC CLR
DATA
J2
BF1
BF4
THRESH
DISC.
CHANNELS
1-48
BF3
BACKBACK
PLANE
INTFC
J1
EF1
SLOW
CTRL
EF0
DATA
THRESH
J3
DISC.
CHANNELS
49-96
SLOW CTRL
L
TEST
PULSER
EF2
Spartan-6
XC6SLX25
FPGA
EF3
CLK
Scintillator Readout
TEST
PULSER
ADDR
59
Manpower Issue
p
• No dedicated postdoc on the firmware
– 1 grad student (formerly engineer), who has done 1 grad student (formerly engineer), who has done
the board designs
– Dedicated effort needed on firmware/software
Dedicated effort needed on firmware/software
– Some overlap with needed SciFi trackers for iTOP
cosmic ray commissioning, but further manpower i
i i i b t f th
needed
12/13/2013
60
Summary
• Applying
Applying experience in high‐speed waveform experience in high speed waveform
sampling ASICs (“oscilloscope on a chip”) and fast readout
• Same basic infrastructure common to all Same basic infrastructure common to all
detector upgrades: common DAQ system
• Functional prototypes under test
F ti
l
t t
d t t
• Pre‐production prototypes in early 2014
p
p
yp
y
• Production in mid‐late 2014, funding‐dependent
12/13/2013
61
BACKUP
62
Prototype Front‐End Board Test Software
• Configures Ethernet Ethernet
Module
• Controls threshold C t l th h ld
and built‐in pulser
• Creates separate
thread for reading TDC data 12/13/2013
63
Scintillator Slow Control
Scintillator Slow Control
• The scintillator electronics require configuration values that are expected to be transmitted over each Belle2link
• Number of bKLM
N b
f bKLM parameters if passed through Concentrator:
t if
d th
hC
t t
• 300 MPPC channel bias voltage settings
• 600 ASIC
00 S trigger threshold and DAC
i
h h ld d
values
l
• Number of eKLM parameters if passed through Concentrator:
• 1050 MPPC channel bias voltage settings
• 2100 ASIC trigger threshold and DAC values
12/13/2013
64
FPGA Configuration
•
The Concentrator supports two methods for FPGA
h C
h d f
G configuration of the RPC fi
i
f h
C
boards in the bKLM:
1) Using SPI PROMs that are indirectly programmed with JTAG on C
Concentrator
t t
2) Downloading the MCS programming file to Concentrator using the B2Link.
NOTE: The Concentrator design incorporates a triple modular redundant PROM NOTE:
The Concentrator design incorporates a triple modular redundant PROM
scheme that includes error checking.
12/13/2013
65
Serial Number and Address
Serial Number and Address
•
•
•
•
Each RPC board has a 4‐bit address –
h Cb dh
bi dd
13 RPC boards per crate so each crate 3 Cb d
h
repeats addresses.
The Concentrator board has a 4‐bit address that can be used to address each crate.
t
There are 16 Concentrator boards in the Barrel and 16 in the End‐cap – unique address in each system.
Both the RPC and Concentrator board contain a 64‐bit serial number chip that can be used if necessary.
12/13/2013
66
RPC Slow Control
RPC Slow Control
•
The RPC Front‐End board requires configuration values and (optionally) built‐in‐
h
C
db d
i
fi
i
l
d( i
ll ) b il i
test control that is expected to be transmitted over each Belle2link:
• Threshold value ‐ 1248 values/Concentrator, 8‐bits per value
• Test pulser
T t l ‐ 1248 built‐in‐test values/Concentrator, 1‐bit per value
1248 b ilt i t t l /C
t t 1 bit
l
• Test pulser control – some number of bits to turn test pulser on/off
12/13/2013
67

WBS 1 3 Electronics WBS 1.3 Electronics KLM readout: RPCs

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