implementation of audio decoder muhammad amirul bin mohamad

IMPLEMENTATION OF AUDIO DECODER
MUHAMMAD AMIRUL BIN MOHAMAD KHALID
UNIVERSITI TEKNOLOGI MALAYSIA
PSZ 19:16 (Pind. 1/07)
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Author’s full name : MUHAMMAD AMIRUL BIN MOHAMAD KHALID
Date of Birth
: 10 OCTOBER 1990
Title
: IMPLEMENTATION OF AUDIO DECODER
Academic Session : 2013/2014
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IMPLEMENTATION OF AUDIO DECODER
MUHAMMAD AMIRUL BIN MOHAMAD KHALID
A report submitted in partial fulfillment of the
requirements for the award of the degree of
Bachelor of Engineering (Electrical – Electronics)
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
JUNE 2014
ii
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iii
To my supervisor, lecturers, technicians and staff,
And also fellow friends that steered with me through ups and downs,
Also my parents that I looked to when it’s rough,
May all of you live in peace and sound.
iv
ACKNOWLEDGEMENT
In the name of Allah, The Most Gracious and The Most Merciful whom with His
willing, allows me to complete this thesis. In preparing this report,I was lucky to be
given opportunity to explore various things that could not learn in lecture halls or classes.
I would like to express my appreciation to my supervisor, Associate Professor
Muhammad Mun’im bin Ahmad Zabidi for giving me the guidance, critics, support and
encouragement during working on this project. I would like to give my sincere thanks to
all lecturers, technicians and staffs for all wonderful experiences and cooperation for my
project, especially Dr Musa bin Mohd Mokji, and Mr. Izam bin Kamisian.
Finally, with memorable, to my fellow friends Muhammad Shaufil Adha bin
Shawkany Hazim, Mohd Hakim bin Jamdun Akirah, Ahmad Talib bin Ab Rahman,
Saiful Lizan bin Abidin, Tan Wei Choon, Pang Chun Chet, and others who were
together with me through difficulties, as well as those who contribute directly or
indirectly in preparing and finishing this report, your kindness means a lot to me.
Thank you.
Muhammad Amirul Mohamad Khalid, June 2014
v
ABSTRACT
The purpose of this study is to implement the audio decoding design in hardware
inside a field programmable gate array (FPGA) tools. Today, the audio format MP3 file
is the most popular standard for audio compression, used in playback device such as
audio players and mobile phones. While MP3 decoding is one of the essential parts in
multimedia system, most of the decoding designs are software-based, particularly
because of the design of the system, which is easier compared to the hardware part.
However, the software decodersrequire higher clock speeds, hence higher power
consumption. There are projects that combine both hardware and software approaches
for MP3 decoding, but the standalone hardware intellectual property (IP) core is still not
well explored.
This paper will introduce a brief overview on the fundamentals of the project, as
well as the required details needed in working on the project. The target of this project is
to build the hardware environment of the project, implementing the audio decoding layer
process and run the combination hardware and software needed together to run the
project.
vi
ABSTRAK
Tujuan projek ini dilaksanakan ialah untuk mereka bentuk dan membina
penyahkod bunyi (audio decoder) menggunakan field programmable gate array
(FPGA). Pada masa kini, fail audio berformat MP3 adalah fail audio yang paling popular
dalm sistem pemain audio serta pemampatan audio (audio compression), yang
digunakan dalam peranti seperti pemain audio dan telefon bimbit. Walaupun MP3
penyahkodan adalah salah satu bahagian yang penting dalam sistem multimedia,
kebanyakan reka bentuk penyahkodan adalah dalam bentuk perisian (software),
terutamanya kerana reka bentuk sistem yang lebih mudah diprogramkan berbanding
dalam bentuk perkakasan (hardware). Walau bagaimanapun, reka bentuk perisian
mempunyai kitaran jam yang lebih tinggi, oleh itu penggunaan kuasa dalam perisian
juga tinggi. Terdapat projek-projek yang menggabungkan kedua-dua perkakasan dan
perisian reka bentuk dalam mereka cipta penyahkodan audio, tetapi perkakasan yang
menggunakan sepenuhnya perkakasan belum dapat diterokai sebaiknya.
Tesis ini akan memperkenalkan serba sedikit maklumat ringkas mengenai asas
penyahkodan audio, dan juga butiran yang diperlukan dalam melaksanakan projek ini.
Sasaran projek ini adalah untuk membina satu alat penyahkod audio yang
menggabungkan kedua-dua perkakasan danperisian yang diperlukan untuk menjayakan
projek ini.
vii
TABLE OF CONTENTS
CHAPTER
1.0
TITLE
PAGE
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENTS
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF FIGURES
x
LIST OF TABLES
xii
LIST OF APPENDICES
xiii
LIST OF ABBREVIATIONS
xiv
Introduction
1.1
Project Background
1
1.2
Problem Statement
2
1.3
Objective
2
viii
2.0
1.4
Scope of the Project
2
1.5
Outline of the Thesis
3
Literature Review
2.1
Related Studies and Previous Work
4
2.2
Introduction to the MP3 Decoding Core
6
2.2.1
Synchroniser
7
2.2.2
Huffman Decoding
8
2.2.3
Requantiser
9
2.2.4
Reordering
10
2.2.5
Antialiasing
11
2.2.6
Inverse Modified Discrete Cosine
12
Transform (IMDCT)
2.2.7
2.3
3.0
Synthesis PolyphaseFilterbank
Psychoacoustics Theory
13
14
Research Methodology
3.1
Introduction
16
3.2
Visual Representation of Research Methodology
16
3.3
Tools Used for Project
17
3.3.1
Altera DE2 Board
18
3.3.2
Altera Quartus II
19
ix
4.0
5.0
3.3.3
NIOS II
19
3.3.4
Peripheral Devices
20
3.4
Getting the SOPC Running
21
3.5
Downloading the Decoder into DE2
26
Results and Discussion
4.1
Introduction
31
4.2
Observation and Analysis
31
4.3
Discussion
33
Conclusion& Recommendation
5.1
Chapter Overview
35
5.2
Recommendation
35
5.3
Conclusion
36
REFERENCE
38
APPENDIX A
41-62
x
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
2.1
The MP3 bitstream format
7
2.2
The three parts of frequency line
8
2.3
The reordering process (the darker colour represents
11
higher frequencies)
2.4
The antialias butterfly
11
2.5
Types of window sequences in a subband
12
2.6
The IMDCT operation flow
13
2.7
The hearing range for human and several animals
15
3.1
The project workflow
17
3.2
The Altera DE2 board
18
(source:http://www.terasic.com.tw/)
3.3
The Quartus II workbench environment
19
3.4
The NIOS II workbench environment
20
3.5
The Video Graphic Accelerator (VGA) monitor
20
3.6
Speaker used in the project
21
3.7
The New Project Wizard window
22
3.8
Adding CPU in the system
23
xi
3.9
Complete Nios II system
23
3.10
The pin assignment window
24
3.11
The compilation report
25
3.12
The programmer window
25
3.13
The hardware architecture
26
3.14
New C/C++ application project window
27
3.15
The system library properties window
28
3.16
The NIOS II IDE workspace window
29
3.17
The setup of the decoding project
29
4.1
The represented decoded data in “equalizer mode”
32
4.2
The flow summary of Quartus II compilation
33
xii
LIST OF TABLES
TABLE NO.
TITLE
PAGE
3.1
The header files created for software decoding process
30
4.1
The analysed time for decoding process
32
xiii
LIST OF APPENDICES
APPENDIX.
TITLE
PAGE
A
Source code for the hardware part top level design
“DE2_SD_Card_Audio.v”
41
B
Source code for the software part C code for file
“hello_world.c”
56
xiv
LIST OF ABBREVIATIONS
ASIC
Application-Specific Integrated Circuit
CD
Compact Disc
CISC
Complex Instruction Set Computing
CPU
Central Processing Unit
CRC
Cyclic Redundancy Check
DE2
Development and Education 2
DSP
Digital Signal Processing
FP
Floating Point
FPGA
Field Programmable Gate Array
FPS
Frames Per Second
FYP
Final Year Project
HDL
Hardware Description Language
IMDCT
Inverse Modified Discrete Cosine Transform
ISO
International Organisation for Standardisation
MDCT
Modified Discrete Cosine Transform
MP3
MPEG-1/2 audio layer-3
MPEG
Moving Pictures Experts Group
PCM
Pulse Code Modulation
RISC
Reduced Instruction Set Computing
xv
RTL
Register Transfer Level
SD
Secure Digital
SoC
System on Chip
SOPC
System on Programmable Chip
VGA
Video Graphic Accelerator
VHDL
VHSIC Hardware Descriptive Language
VLSI
Very Large Scale Integration
CHAPTER 1
INTRODUCTION
1.1
Project Background
The MPEG-1/2 audio layer-3, properly known as MP3format is a very popular
format for compressing high quality audio.In recent years the application of the MP3
audio codec has exploded. Typically MP3 files are played back using software (CPU or
DSP), but recent trends have witnessed the emergence of portable devices, such as
mobile phones andMP3 players.While DSP architecture is the most flexible for running
MP3 player, the challenges of the more power efficient FPGA implementation of MP3
decoding are less understood.
Field Programmable Gate Array (FPGA), is one type of integrated circuit that is
programmable outside the factory, thus it is called “field programmable”. This integrated
circuit uses hardware description language (HDL) to configure. Nowadays, the FPGA
has been applied to solve many problems in embedded systems. It can be employed as
standalone System on Chip (SoC) or as powerful accelerators in multi-chip systems.
2
The target of the project is to implement the MP3 decoding core by utilizing the
FPGA properties. First, the software decoder is implemented on the softcore CPU on the
FPGA. Then another decoder is implemented in hardware. The different decoders are
then compared in terms of minimum clock speed and resource requirements.
1.2
Problem Statement
Most of the MP3 decoders are implemented in software. However, hardware
decoders offer much power consumption which will be beneficial in embedded systems.
This paper will assess the implementation of audio decoder using FPGA board, as well
asanalysing the time requirement to decode the files.
1.3
Objective
The objectives of this project are:
i.
To implement an audio decoder on an FPGA board, along with its
peripherals needed to run the process
ii.
To analyse the time requirement of the audio decoding process needed to
produce the output
iii.
To test and assess the effectiveness of both software decoder and
hardware decoder design
3
1.4
Scope of the Project
The scope of the project includes combination of several elements such as
hardware, software and electronic parts. Below are the scopes for the project.
i.
Uses Verilog HDL language as its main basis for programming
ii.
Explore the application of Verilog using Altera DE2 Board
iii.
Include software programming such as C and C++
iv.
Implement the application (partial) using downloaded software for
software implementation (Quartus II 9.1, Nios II 9.1)
1.5
Outline of the Thesis
This thesis consists of five chapters where in the first chapter, discusses the
problem statement, objectives and the scope of this project. Chapter 2 explains more on
the literature reviews based on the related studies and previous work of other researcher.
This chapter also includes any references that are relevant to the project, whether they
involve audio decoding, or FPGA-related projects.
Chapter 3 describes the methodology of hardware and software implementation
on this project. The result and the discussion about this project is explained in detail in
chapter 4. The final chapter illustrates the conclusion of this project,as well as the
recommendation and further work that can be done.
CHAPTER 2
LITERATURE REVIEW
In 1988, Hiroshi Yasuda (Nippon Telegraph and Telephone) and Leonardo
Chiariglione had initiated the working group Moving Pictures Experts Group (MPEG) to
set the standards for audio and video compression and transmission. The group, formed
by
International
Organisation
for
Standardisation
(ISO)
and
International
Electrotechnical Commission (IEC), has since developed into an organization joined by
members from various industries, universities and research institutions. One of the
standards that have created is the MPEG-1 Layer 3, or better known as MP3. MP3 is the
standard format used for digital audio compression, in which the design have 12:1
compression ratio, from 1.4Mbps 128kbps bitrate for compact disc (CD) music.
2.1
Related Studies and Previous Work
It is known that MP3 decoding process is a difficult process, but several
researchers have attempted to design the decoder for this specific format. For instance,
Faltman et al. (2003) have stated that incorporating of MP3 decoders in portable and
stand-alone players have gained in popularity. In the report, Faltman also stated the
importance in the performance of these hardware MP3 decoding based on the clock
5
cycles and power usage. It also includes an attempt to to create an MP3 decoder in
hardware, by using Xilinx FPGA board. Thuong et al. (2005) have proposed the
architecture of the MP3 decoding core, in which the subcores of the architecture can be
individually designed, coded and tested easily. The design of the core is coded using
VHDL.
Ko and Nicolici (2007) have tested the implementation of the core using Altera
DE2 board and Xilinx multimedia board. It also has results including the number of
logic elements, flip-flops, memories and multipliers involved. Bhargav and Yang (2008)
have introduced the usage of Linux-run interface on the decoding core. Their research
has also opened the possibilities of recreating the popular piece of consumer technology
using existing hardware available in the lab. The design utilizes both hardware and
software component in their design architecture. It has few general slowdowns due to
system clock and debugging process.
Singh et al.(2008) have proposed that the demand of handheld players and
multimedia in mobile phone have raised a need for a dedicated hardware to decode the
file formats with low power consumption and faster acceleration. Papakonstantinou et
al. (2008) have researched case study on the implementation of floating point math in
decoder implementation to achieve real time and faster decoding process. In the case
study, the authors introduce floating-point (FP) unit in their architecture to assess the
operation speed; thus calling it the FP implementation of MP3 decoding.
Moslehpour et al.(2013), the project uses the Nios II softcore processor to read
files and produces output from the decoding process. By using secure digital (SD) card
as input devices, the system uses Altera DE2 board and plays back different file format:
wave files, or .wav extension files. The report have shown that running the decoder in
software is possible, particularly because of software features use Altera SOPC builder
6
in Altera Quartus 9.1 environment, which is the platform widely used in tertiary
education.
Tsai et al. (2004) have proposed a specific architectural structure of MP3
decoder in very large scale integration (VLSI) approach. It achieves a high throughput
with a reduced memory requirement and hardware complexity. Meanwhile, Kalpana et
al.(2012) have tried to implement the algorithm on the 32-bit reduced instruction set
computing (RISC) ARM processor, which uses more hardware than necessary.
All of the previous work mentioned haveproposed new approaches in building
the MP3 decoding core, either in hardware or software.
However, the hardware
implementation of MP3 decoding IP core in Verilog HDL is not well understood.
Therefore, the focus is the report is to tackle the design of MP3 decoding core, on the
surface at least.
2.2
Introduction to the MP3 Decoding Core
According to Kalpana et al.(2012), all MP3 files are divided into fragments
called frames. Each frames stores 1152 samples, lasting for 26ms, which the frame rate
is approximately 38 frames per second (fps). The first step to decode MP3 file format is
by finding the start of the frame, which is called synchronization process, or else called
initial reading.
7
2.2.1
Synchroniser
Before decoding, the start of the frame must be found. If the frame is interrupted,
we cannot find the exact position of the next frame (Thuong et al., 2007). The structure
of the frame consists of 5 parts; header, cyclic redundancy check (CRC), side
information, main data and ancillary data.
Header
CRC
32-bit
16-bit
Side Information
Figure 2.1
Main data
Ancillary Data
The MP3 bitstream format
The details about the frame header is as follows:
i.
Frame Header
It is a 32-bit long and has description of the frame, together with the
synchronisation word to distinguish the beginning part of the bitstream.
ii.
CRC
Use to check if there is any transmission error for the most sensitive data. The
CRC will only exists when the protection bit in the header is set.
iii.
Side Information
Includes the important information needed to decode the main data. This depends
on the channel mode. For single channel, 136 bits are allocated, while for dual
8
channel, 256 bit allocated (this is equivalent to 17 bytes in single channel, 32 bytes
in dual-channel)
iv.
Main Data
The main data part consists of the frames that includes scalefactors, Huffman
coded bits and ancillary data
v.
Ancillary Data
This data can hold user-defined information. This frame area can hold optional
data such as song name or song information.
2.2.2
Huffman Decoding
This section contains one of the most important task in MP3 decoding. The task
of Huffman decoding is to transform and mapping the data into scalefactors and symbols
representing the 576 original frequency lines for each granule. These frequency line is
divided into three partition; Big-values, Count1 and Rzero.
576 scaled frequency lines
Big-values
Count1
Rzero
2*Big-values
2*Big-values + 4*Count1
Figure 2.2
The MP3 bitstream format
9
Details on the Huffman code partition are as follows:
i.
Big-values
Represents the lowest frequency lines and are coded with the highest precision,
scaled from values between -15 to 15. When the decoder finds the value 15, it
assumes that the higher precision is needed. This can be done by using the value 15
as an escape code, then reads additional bits from the imput stream. The numbers
specified in the Huffman table are called linbits.
ii.
Count1
Represent the higher frequency lines; not need the higher precision scaled value.
Ranging from -1 to 1.
iii.
Rzero
Represent the highest frequency lines, and not part of the bitstream. It contains the
the frequency lines that are removed by the encoder. These values are filled with
zeros by the decoder.
2.2.3
Requantiser
The symbols generated from Huffman decoding is then reconstructed into the
original frequency line by using the scalefactors provided in the side information of the
frame. The low frequency scalefactor band contains less values than the high frequency.
10
The descaling equation for both short blocks and long blocks are defined as
Short blocks:
(
) |
[
(
|
[
[
][
]
][
)
][
][
]
]
Long blocks:
(
) |
|
[
(
[
[
]
[
]
][
)
][
]
]
The denoted scalefactorsscalefactor_s and scalefactor_l used by requantiser are
provided by Huffman decoder. Parameters global_gain, subblock_gain and preflag can
be found in the frames, provided by the Synchroniser block. The notation
output from the Requantiser block, while
2.2.4
defines
is the Huffman decoded value at index i.
Reordering
This block only has one task: it reorders the frequency lines within a granule.
When the short block is decoded, a short window will be used. The output is then sorted
into subbands, then on frequencies and at last by windows to increase the efficiency of
Huffman coding.
11
Figure 2.3
2.2.5
The reordering process (the darker colour represents higher frequencies)
Antialiasing
Antialiasing is the process where its function is to reduce the inevitable alias
effects because of the usage of non-ideal bandpass filtering. The alias reconstruction is
based on the butterfly calculation, consisting of eight butterfly calculation for each
subband.
Figure 2.4
The antialias butterfly
12
2.2.6
Inverse Modified Discrete Cosine Transform
Inverse Modified Discrete Cosine Transform, known as IMDCT, reproduce time
samples from the frequency lines, together with synthesis polyphase filterbank. The
time samples can be obtained from the frequency lines by using the following equation.
∑
*
(
)(
)+
The IMDCT operation flow begins by taking 18 input frequency lines and
generates 36 polyphase filter subband samples. The samples then multiplied with with a
36-point window before passed into next decoding process. Windowing is the process
of multiplying and overlapping addition operation of IMDCT’s output with the sine
window coefficient. Based on the length of each window, four types of block is used;
they are start, stop, short and long. The decision of block type is based on the analysis
of the psychoacoustic model.
Figure 2.5
Types of window sequences in a subband
However, producing 36 samples from 18 input means that there are only 18
samples are unique, thus the IMDCT method uses a 50% overlap. In this case, the 36
output samples is then divided into 2 groups, low group and high group, which has 18
samples each. The overlapping process is then carried out by adding values from the
higher group, previous frame with the lower group, corresponding frame. Then, the
13
frequency inversion is then taken place to achieve correct phase difference. This was
done by multiplying every odd subband with (-1).
Figure 2.6
2.2.7
The IMDCT operation flow
Synthesis PolyphaseFilterbank
This block is the last step in decoding process. It converts all 32 subbands to
produce 32 Pulse Code Modulation (PCM) samples at a time The filterbank exploits
aliasing and windowing to move the subbands back into their frequency domain. This
block is divided into two parts; Modified Discrete Cosine Transform (MDCT) and
windowing.
i.
Modified Discrete Cosine Transform
Each time frame of the subband samples are ordered so that the first 32
values are the first sub-sample from each subband, and so forth. The
MDCT processes 32 values at a time by using the equation:
14
∑
where
*
(
The resultant output values,
ii.
)(
)+
is then stored in the barrel shifter.
Windowing
The windowing process runs by multiplying the values
from the barrel
shifter with the window function. This window function is specified in the
ISO standard. The PCM generated are then computed for each iteration.
The MDCT and windowing together run 18 times for each granule,
producing 576 PCM samples (27ms at 44.1kHz).
2.3
Psychoacoustic Theory
The basic component of audio compression is removing redundant information
exists in the audio signal. A normal human being can hear frequencies of between 20
Hz and 20kHz. Audio coding aims to discard signal components that are inaudible to
the human listener.
15
Figure 2.7
The hearing range for human and several animals
A very important property of psychoacoustics and human hearing is that the loud
signal will shadow the less loud signal sufficiently close in frequency domain or time
domain, modifying the threshold of hearing. This process is called masking. This
property is important and can be utilize in optimum way in compressing audio signal.
The masking technique can subsequently reduce the audio signal transmitted by
removing the masked data shadowed by the loud signal, hence the files can be
compressed further. Using the properties of the human auditory system, lossy codecs
remove inaudible signals to reduce the information content, thus compressing the signal.
The MP3 standard does not dictate how an encoder should be, and codec developers
have plenty of freedom to remove content they deemed unusable. One encoder may
decide a particular frequency is inaudible and should be removed, while another encoder
keeps the same signal. Different encoders use different psychoacoustic models, models
describing how humans listen to sound, hence what information may be removed.
CHAPTER 3
RESEARCH METHODOLOGY
3.1
Introduction
This chapter discusses the approach taken during the project’s timeline to ensure
that the project is well organized and run efficiently. The methodology is represented
into a flow chart for ease of understanding.
3.2
Visual Representation of Research Methodology
The workflow for the project is shown, in Figure 3.1.
17
Figure 3.1
The project workflow
The project begins by researching any previous works related to the MP3
decoding and FPGA-based architecture implementation. Besides that, several resources
on hardware description language and software programming tutorial have also looked
at. The process involved in building the core is studied and briefly elaborated to give
extra knowledge in order to fulfill the research. The importance and purpose of the
project is also discussed in the first stage.
3.3
Tools Used for Project
This section will explain the tools and software supports used in the project.
18
3.3.1
Altera DE2 Board
The hardware used for testing and implementing the project is Altera DE2
Educational Development Board.
Figure 3.2
The Altera DE2 board (source: http://www.terasic.com.tw/)
The Altera DE2 board provides everything needed to develop many advanced
digitaldesigns using Altera Cyclone II device, with using application software Altera
Quartus II. This development board is the first step to introduce and learn basic FPGA
devices easily, since it is accessible in the lab.It is suitable for a wide range of exercises
in courses on digital logic and computer organization, from simple tasks that illustrate
fundamental concepts to advanced designs.
19
3.3.2
Altera Quartus II
Figure 3.3
The Quartus II workbench environment
Altera Quartus II is a software tool produced by Altera for analysis and synthesis
of HDL designs, which enables the user to compile their designs, perform timing
analysis, examine RTL diagrams, simulate a design's reaction and configure the target
device with the programmer.
3.3.3
Nios II
Nios II is a soft processorincorporates many enhancements over the original
predecessor. Nios II processor comprises family of 3 configurable 32-bit Harvard
architecture cores; fast, economy and standard version. Nios II is the most widely used
soft processor and the most flexible for application processing needs
20
Figure 3.4
3.3.4
The Nios II workbench environment
Peripheral Devices
Other than Altera DE2 Board and software involved, there are several device use
inside the projects, among them are speakers and the VGA monitor.
Figure 3.5
The Video Graphic Accelerator (VGA) monitor
21
Figure 3.6
3.4
Speaker used in the project
Getting the SOPC Running
After the tools used for project is assembled, the project is planned, utilizing both
devices and software prepared. First, the hardware language part of the project is created.
Using the template released by Terasic Technologies Inc., the code is then modified and
implemented inside Quartus II version 9.1.
Before then, to understand the mechanism of SOPC building project, a lab
module is used to test the development of the Nios II-based embedded system. This lab
module is design as a student pack, includes step-by-step tutorial and guidelines on
using Quartus II, Nios II and SOPC Builder software. This tutorial is divided into three
22
sections: Quartus II software hardware design, creating the top module files, and
opening Nios II for software development. Based on the tutorial, the system is then
designed and generated.
In the first section, the development of hardware design is started by creating the
new project inside Quartus II, using New Project Wizard.
Figure 3.7
The New Project Wizard window
Then, after creating the new project, the next step is to create the simple Nios II
system by using SOPC Builder, then adding CPU and peripheral into the system.
23
Figure 3.8
Figure 3.9
Adding CPU in the system
Complete Nios II system
24
For the second section, the top-level file is created, by writing the code in
Verilog language. Most of the audio decoding programs on the net utilise the core
program developed by Altera Corporation as their basis in varieties of decoding projects,
named DE2_SD_Card_Audio. The code is provided in the Appendix A of this thesis.
From the codes provided, several modifications have been done in order to create a
decoder based on specific characteristics, most notably in MP3 format. Next, after the
code is created, pins are assigned to the DE2 board by using pin assignment menu.
Figure 3.10
The pin assignment window
Then, the module created is then compiled before the successfully compiled code
is then downloaded into Altera DE2 board using Programmer menu. The compilation
result of the code and the programmer window to download the design is shown as
follows.
25
Figure 3.11
Figure 3.12
The compilation report
The programmer window
26
The simplified designated hardware configuration for this project is illustrated in
the figure below.
Figure 3.13
3.5
The hardware architecture
Downloading the Decoder into DE2
The third part of the section is software development. This section includes
writing the C/C++ embedded system application and run on the system software. This
section will be conducted by implementing Nios II IDE system-on-programmable chip
(SOPC) environment created previously and download the design on the DE2 board.
27
Firstly, the new C/C++ application project is created in Nios II IDE software
using the new project menu. Most of the workspace project utilizes the template project
available in the mentioned software, specifically the “Hello World” project.
Figure 3.14
New C/C++ application project window
After the new project is created, the system library properties of the respected
project are configured.
28
Figure 3.15
The system library properties window
From the codes provided, several modifications have been done in order to create
a decoder, including a number of headers included in the main program name
hello_world.c, compiled together in the Appendix B of this thesis. Then, the written
code is run in the Nios II IDE workspace window. The code is then compiled and then
built. This is shown in the Nios II workspace window.
29
Figure 3.16
The NIOS II IDE workspace window
The setup of the project is shown below. This setup includes every tool used in
the project.
Figure 3.17
The setup of the decoding project
30
After the main program main program name hello_world.cis created, the header
files are created. There are several headers need to be created to run the software
development of the project. The list of the header files created is shown in the table
below.
Table 3.1
The header files created for software decoding process
File name
antialias.h
basics.h
Description
The antialiasing part of the decoder
Contains the definition of the MP3 file format used for
decoding process
dataheader.h
Contains the MP3 bitstreamdata table
dewindowarray.h
Includes subband synthesis table
float.h
Used for floating point operation
get_scalefactor.h
Used for scalefactor analysis
header_reader.h
Include codes for analyzing the header of the data
huffarray.h
huffman_decode.h
hybrid.h
For Huffman decoding
Creating functions to perform Huffman decoding
Performing IMDCT operation
joint_stereo.h
For stereo processing
reorder.h
For reordering process
requantize.h
For requantising section
subbandsynthesis.h
Used for performing subband synthesis process
syn_costable.h
Used for shifting and reducing the PCM sample
CHAPTER 4
RESULTS AND DISCUSSION
4.1
Introduction
This chapter discusses the result and experiment tested, experimented and
conducted to produce the results obtained and as targeted in the previous chapter. This
chapter also explains hindrances and predicament encounter throughout the entire
project process.
4.2
Observation and Analysis
When first implemented the MP3 decoding process on the DE2 board, the
decoding process is very slow. The analysis of the data is shown below.
32
Table 4.1
The analysed time for decoding process
Activity
Quartus II hardware compilation
Programmer Time
Time Taken
4 minutes 29 seconds
30 seconds
Nios II software running
14 minutes 49 seconds
TOTAL TIME
19 minutes 48 seconds
The output of the decoding is the series of data that represented in visual effects,
which looks like an equalizer in the music player.
Figure 4.1
The represented decoded data in “equalizer mode”
33
From the Quartus II full compilation report, the flow summary of the hardware
design is shown in the figure below.
Figure 4.2
4.3
The flow summary of Quartus II compilation
Discussion
It is clear that the most integral part in implementing the decoder is the software
part. This involves using Nios II software for compiling and running the decoder project.
There are many projects associated with audio decoding available in store, but the
implementation of the project is mostly restricted and prone to software version used.
Another problem faced during completion of the project is the FPGA board
version used. Most of the projects utilize Altera DE2 board, the most common board that
used in Altera University Program. However, due to the limited memory spaces, the
release of newer version and enhanced properties, there is consideration to use the new
board available, the Altera DE2-115. It is certain that the device is more advanced than
the previous predecessor, but the pin configuration, the board properties and the
34
processor performance are different. In addition, none of the completed projects have
been implemented in the new board.
However, after several revisions, it is decided that this project will stick to the
original plan; using the DE2 board, with several modification on the software coding. It
is also decided that the program will also stick to the original coding, with several
modification on the software setting. Thanks to the classic mode setting available in the
latest model, the problem faced in the initial segment of the project can be solved.
CHAPTER 5
CONCLUSIONS AND RECOMMENDATIONS
5.1
Chapter Overview
This chapter will elaborate the conclusion of this project and the
recommendation that can be implemented in the future to make the project better.
5.2
Recommendation
Several modifications have been made by finding the software compatible to the
program code modified specifically for the project. The test proved successful, but
several major modifications need to be implemented.
It is discovered that the new FPGA, the DE2-115 board is better in terms of
hardware specifications compared to the older version, DE2. For example, DE2-115
board is using the Altera Cyclone® IV 4CE115 FPGA, the newer version compared to
DE2 that useAltera Cyclone® II 2C35 FPGA. The DE2-115 also has bigger memory
36
space compare to the DE2 board. Therefore, a more advanced decoder design can be
implemented.
Next, it is recommended to alter the code to take advantage on the latest FPGA
features. This is due to the fact that newer version of the FPGA board have much
powerful performance. Furthermore, with the adaptation of new platform the system
builder will cause the new code to be incompatible with the old board. From the system
with the .ptf file generated, to the .sopc format file and now with the .qsys file extension,
there is an essential need to edit the code so it is compatible to the latest version of the
software. However, backward compatibility is not necessary to when upgrading to a new
board.
Upgrading the system to the FPGA with better processor is another
recommendation to improve performance of the project. For example, processor such as
ARM has several features not available in Nios such as the ability to run more operating
system. The bus architecture of the processor also plays an important role in increasing
the performance of the processor. For instance, the ARM bus architecture, called AMBA
can be design hierarchically, pipelined and multiplexed, while Altera bus architecture,
called Avalon, only available in multiplexed and pipelined architectures.
5.3
Conclusion
The objective of implementing the audio decoder on an FPGA board, along with
the peripheral needed is successful. By using the combination of hardware and software
co-design, the project achieves the first objective. From the successful design, the time
requirement of audio decoding process needed to produce the output can be assessed. By
using observation and time-clocking method, the analysis of the time consumption is
achieved. However, implementing the hardware decoder as a standalone intellectual
37
property (IP) core did not achieve its objective stated. To achieve the required objective
stated, the project experienced difficulties in converting the software code into hardware
description language (HDL), as well as lack of sources related to hardware audio
decoding.
This project is a highly difficult and challenging, yet there are many area of
knowledge discovered during the process of completing it. Aside from learning how to
implement SoC in FPGA, studying about the properties of audio decoding process,
particularly the MP3 file format, as well as the psychoacoustic theory of human hearing
really brought the new dimension in my studies. Since this project focuses on the reallife application to the consumer, the challenge of designing devices that is user-friendly
is another aspect of lesson learned throughout completing the project. The idea of
turning a proposed design to a prototype useful to the customer is now a trend in the
university final year projects, instead of focusing on the pure research project, in which
few of the general public generally understand and appreciate its application used in
daily life.
REFERENCES
Altera.(2013). DE2-115 User Manual. Terasic DE2-115 User Manual, www.terasic.com.
Altera.(2013). Nios II Performance Bookmarks. Data Sheet, Altera Corporation.
Altera.(2007). DE2 Development and Education Board User Manual.Version 1.4.1
Altera Corporation.
Bakhteri R. (2013). ECAD Problem Based Lab Student Pack – Altera DE2 Tutorial.
Fakulti Kejuruteraan Elektrik, Universiti Teknologi Malaysia, Kampus Skudai,
Johor.
Bhargav S., Yang B. (2008).MP3 decoding of an FPGA. CSEE 6847 Distributed
Embedded System. Columbia University.
Cai S., Xiao X., Zhang J. (2005). Embedded Network MP3 Playing System. Nios II
Embedded Processor Design Contest – Outstanding Designs 2005, Southern
Taiwan University of Technology.
Edstrom B. (2008). Let’s build an MP3-decoder! http://blog.bjrn.se/2008/10/lets-buildmp3-decoder.html
Faltman I., et. al (2003). A hardware implementation of an MP3 decoder. Digital ICProject, LTH, Sweden.
39
Hau Y, Hani M. (2012). SoC based Design: Avalon Bus Interface to User-Designed
Logic. veCAD Technical Report, Faculty of Electrical Engineering, Universiti
Teknologi Malaysia.
Hedberg H., Lenart T., Svensson H. (2005). A Complete MP3 Decoder on a
Chip.Proceeding of the 2005 IEEE International Conference on Microelectronic
System Education (MSE ’05).
Kalpana E., Sridhar V., Rajendra M. (2012).“MPEG-1/2 audio layer-3(MP3) on
theRISC based ARM Processor (ARM92SAM9263)”. International Journal of
Computer Science Engineering (IJSCE).
Ko H, Nicolici N. (2007).MAC_MP3: A Low Energy Implementation of an Audio
Decoder. McMaster University, Ontario.
Luka L. (2010). FPGA-based MP3 Player Project Report.
Mansour M. F. (2007). “Efficient Huffman Decoding with Table Lookup”. International
Conference of Acoustics, Speech and Signal Processing 2007 (ICASSP ’07),
IEEE.
Moslehpour S., Jenab K., Siliveri E. H. (2013). Design and Implementation of NIOS II
System for Audio Application. IACSIT International Journal of Engineering and
Technology, Vol. 5, No. 5.
Papakonstantinou A., et. al (2008). MP3 decoding on FPGA: a case study for floating
point acceleration.ECE Department, University of Illinois.
Raissi R. (2002). The Theory Behind MP3. www.mp3-tech.org.
Sharma M., Kumar D. (2012). “Wishbone Bus Architecture – A Survey and
Comparison”.International Journal of VLSI design and Communication System
(VLSICS),Vol 3, No. 2.
Shlien S. (1994). Guide to MPEG-1 Audio Standard. IEEE Transaction on Broadcasting,
Vol. 40, No. 4, December 1994.
40
Singh M,Shah N. R., Shankar R. (2008).player-I – An internet based muzik player.
CSEE W4840 Design, Columbia University.
Sripada P. (2006). MP3 DECODER in Theory and Practice. Master Thesis Report,
Blekinge Tekniska Högskola.
Thuong L, Vu C, Chien H (2005).FPGA Based Architecture of MP3 Decoding Core for
Multimedia Systems. Hochiminh City University of Technology.
Tsai T, Yang Y, Lui C (2005). A Hardware/Software Co-Design of MP3 Audio Decoder.
Journal of VLSI Signal Processing 41, 111-127.
Wong R, Santhanagopalan V (2010). Music Player.ECE 5760 - Final Project. Cornell
University
Zheng L, et. al (2010). MP3 Player. CSEE 4840 Spring 2010 Project Design, Columbia
University.
APPENDIX A
Source code for the hardware part top level design
// -------------------------------------------------------------------// Copyright (c) 2005 by Terasic Technologies Inc.
// -------------------------------------------------------------------//
// Permission:
//
//
Terasic grants permission to use and modify this code for use
//
in synthesis for all Terasic Development Boards and Altera Development
//
Kits made by Terasic.
//
,duplication, or modification of any portion is strictly prohibited.
Other use of this code, including the selling
//
// Disclaimer:
//
//
This VHDL/Verilog or C/C++ source code is intended as a design reference
//
which illustrates how these types of functions can be implemented.
//
It is the user's responsibility to verify their design for
//
consistency and functionality through the use of formal
//
verification methods.
//
or functionality of this code.
Terasic provides no warranty regarding the use
//
// -------------------------------------------------------------------//
//
Terasic Technologies Inc
//
356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//
HsinChu County, Taiwan
//
302
//
//
web: http://www.terasic.com/
//
email: [email protected]
//
// --------------------------------------------------------------------
42
//
// Major Functions:
DE2 NIOS Reference Design
//
// -------------------------------------------------------------------//
// Revision History :
// -------------------------------------------------------------------//
Ver
:| Author
//
V2.0 :| Johnny Chen
:| Mod.Date :| Changes Made:
:| 06/07/19
:|
Initial Revision
// --------------------------------------------------------------------
module DE2_SD_Card_Audio
(
////////////////////
Clock Input
////////////////////
CLOCK_27,
//
On Board 27
CLOCK_50,
//
On Board 50
EXT_CLOCK,
//
External Clock
MHz
MHz
////////////////////
Push Button
KEY,
////////////////////
////////////////////
//
DPDT Switch
Pushbutton[3:0]
////////////////////
SW,
//
Toggle
Switch[17:0]
////////////////////
7-SEG Dispaly
////////////////////
HEX0,
//
Seven Segment
HEX1,
//
Seven Segment
HEX2,
//
Seven Segment
HEX3,
//
Seven Segment
HEX4,
//
Seven Segment
HEX5,
//
Seven Segment
HEX6,
//
Seven Segment
HEX7,
//
Seven Segment
Digit 0
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7
////////////////////////
LED
////////////////////////
43
LEDG,
//
LED Green[8:0]
LEDR,
//
LED Red[17:0]
////////////////////////
UART
////////////////////////
UART_TXD,
//
UART
UART_RXD,
//
UART Receiver
Transmitter
////////////////////////
IRDA
////////////////////////
IRDA_TXD,
//
IRDA
IRDA_RXD,
//
IRDA Receiver
///////////////////// SDRAM Interface
////////////////
DRAM_DQ,
//
SDRAM Data bus
DRAM_ADDR,
//
SDRAM Address
DRAM_LDQM,
//
SDRAM Low-byte
DRAM_UDQM,
//
SDRAM High-
DRAM_WE_N,
//
SDRAM Write
DRAM_CAS_N,
//
SDRAM Column
DRAM_RAS_N,
//
SDRAM Row
DRAM_CS_N,
//
SDRAM Chip
DRAM_BA_0,
//
SDRAM Bank
DRAM_BA_1,
//
SDRAM Bank
DRAM_CLK,
//
SDRAM Clock
DRAM_CKE,
//
SDRAM Clock
Transmitter
16 Bits
bus 12 Bits
Data Mask
byte Data Mask
Enable
Address Strobe
Address Strobe
Select
Address 0
Address 1
Enable
////////////////////
Flash Interface
////////////////
FL_DQ,
//
FLASH Data bus
FL_ADDR,
//
FLASH Address
FL_WE_N,
//
FLASH Write
FL_RST_N,
//
FLASH Reset
FL_OE_N,
//
FLASH Output
8 Bits
bus 20 Bits
Enable
Enable
44
FL_CE_N,
//
FLASH Chip
Enable
////////////////////
SRAM Interface
////////////////
SRAM_DQ,
//
SRAM Data bus
SRAM_ADDR,
//
SRAM Address
SRAM_UB_N,
//
SRAM High-byte
SRAM_LB_N,
//
SRAM Low-byte
SRAM_WE_N,
//
SRAM Write
SRAM_CE_N,
//
SRAM Chip
SRAM_OE_N,
//
SRAM Output
16 Bits
bus 18 Bits
Data Mask
Data Mask
Enable
Enable
Enable
////////////////////
ISP1362 Interface
////////////////
OTG_DATA,
//
ISP1362 Data
OTG_ADDR,
//
ISP1362
OTG_CS_N,
//
ISP1362 Chip
OTG_RD_N,
//
ISP1362 Write
OTG_WR_N,
//
ISP1362 Read
OTG_RST_N,
//
ISP1362 Reset
OTG_FSPEED,
0 = Enable, Z = Disable
//
USB Full Speed,
OTG_LSPEED,
0 = Enable, Z = Disable
//
USB Low Speed,
OTG_INT0,
//
ISP1362
OTG_INT1,
//
ISP1362
OTG_DREQ0,
//
ISP1362 DMA
OTG_DREQ1,
//
ISP1362 DMA
bus 16 Bits
Address 2 Bits
Select
Interrupt 0
Interrupt 1
Request 0
Request 1
OTG_DACK0_N,
//
ISP1362 DMA
OTG_DACK1_N,
//
ISP1362 DMA
Acknowledge 0
Acknowledge 1
////////////////////
LCD_ON,
ON/OFF
LCD Module 16X2
////////////////
//
LCD Power
45
LCD_BLON,
//
LCD Back Light
//
LCD Read/Write
//
LCD Enable
//
LCD
//
LCD Data bus 8
ON/OFF
LCD_RW,
Select, 0 = Write, 1 = Read
LCD_EN,
LCD_RS,
Command/Data Select, 0 = Command, 1 = Data
LCD_DATA,
bits
////////////////////
SD_Card Interface
////////////////
SD_DAT,
//
SD Card Data
SD_DAT3,
//
SD Card Data 3
SD_CMD,
//
SD Card
SD_CLK,
//
SD Card Clock
Command Signal
////////////////////
USB JTAG link
////////////////////
TDI,
//
CPLD -> FPGA
TCK,
//
CPLD -> FPGA
TCS,
//
CPLD -> FPGA
//
FPGA -> CPLD
(Data in)
(Clock)
(CS)
TDO,
(Data out)
////////////////////
I2C
////////////////////////////
I2C_SDAT,
//
I2C Data
I2C_SCLK,
//
I2C Clock
////////////////////
PS2
////////////////////////////
PS2_DAT,
//
PS2 Data
PS2_CLK,
//
PS2 Clock
////////////////////
VGA
////////////////////////////
VGA_CLK,
//
VGA Clock
VGA_HS,
//
VGA H_SYNC
VGA_VS,
//
VGA V_SYNC
VGA_BLANK,
//
VGA BLANK
VGA_SYNC,
//
VGA SYNC
VGA_R,
//
VGA Red[9:0]
VGA_G,
//
VGA Green[9:0]
VGA_B,
//
VGA Blue[9:0]
////////////
Ethernet Interface
////////////////////////
46
ENET_DATA,
//
DM9000A DATA
//
DM9000A
ENET_CS_N,
//
DM9000A Chip
ENET_WR_N,
//
DM9000A Write
ENET_RD_N,
//
DM9000A Read
ENET_RST_N,
//
DM9000A Reset
ENET_INT,
//
DM9000A
ENET_CLK,
//
DM9000A Clock
bus 16Bits
ENET_CMD,
Command/Data Select, 0 = Command, 1 = Data
Select
Interrupt
25 MHz
////////////////
Audio CODEC
AUD_ADCLRCK,
////////////////////////
//
Audio CODEC ADC LR
Clock
AUD_ADCDAT,
//
Audio CODEC
ADC Data
AUD_DACLRCK,
//
Audio CODEC DAC LR
Clock
AUD_DACDAT,
//
Audio CODEC
//
Audio CODEC
//
Audio CODEC
DAC Data
AUD_BCLK,
Bit-Stream Clock
AUD_XCK,
Chip Clock
////////////////
TV Decoder
TD_DATA,
////////////////////////
//
TV Decoder Data bus 8
bits
TD_HS,
//
TV Decoder
TD_VS,
//
TV Decoder
TD_RESET,
//
TV Decoder
H_SYNC
V_SYNC
Reset
////////////////////
GPIO
////////////////////////////
GPIO_0,
//
GPIO
GPIO_1
//
GPIO
Connection 0
Connection 1
);
////////////////////////
input
Clock Input
CLOCK_27;
////////////////////////
//
On Board 27 MHz
47
input
CLOCK_50;
//
On Board 50 MHz
input
EXT_CLOCK;
//
External Clock
////////////////////////
input
[3:0]
////////////////////////
KEY;
//
////////////////////////
input
Push Button
DPDT Switch
Pushbutton[3:0]
////////////////////////
[17:0] SW;
//
////////////////////////
7-SEG Display
Toggle Switch[17:0]
////////////////////////
output [6:0]
HEX0;
//
Seven Segment Digit 0
output [6:0]
HEX1;
//
Seven Segment Digit 1
output [6:0]
HEX2;
//
Seven Segment Digit 2
output [6:0]
HEX3;
//
Seven Segment Digit 3
output [6:0]
HEX4;
//
Seven Segment Digit 4
output [6:0]
HEX5;
//
Seven Segment Digit 5
output [6:0]
HEX6;
//
Seven Segment Digit 6
output [6:0]
HEX7;
//
Seven Segment Digit 7
////////////////////////////
output [8:0]
LED
////////////////////////////
LEDG;
//
LED Green[8:0]
output [17:0] LEDR;
//
LED Red[17:0]
////////////////////////////
UART
////////////////////////////
output
UART_TXD;
//
UART Transmitter
input
UART_RXD;
//
UART Receiver
////////////////////////////
IRDA
////////////////////////////
output
IRDA_TXD;
//
IRDA Transmitter
input
IRDA_RXD;
//
IRDA Receiver
///////////////////////
inout
[15:0] DRAM_DQ;
output [11:0] DRAM_ADDR;
SDRAM Interface
////////////////////////
//
SDRAM Data bus 16 Bits
//
SDRAM Address bus 12 Bits
output
Mask
DRAM_LDQM;
//
SDRAM Low-byte Data
output
Mask
DRAM_UDQM;
//
SDRAM High-byte Data
output
DRAM_WE_N;
//
SDRAM Write Enable
output
Strobe
DRAM_CAS_N;
//
SDRAM Column Address
output
Strobe
DRAM_RAS_N;
//
SDRAM Row Address
output
DRAM_CS_N;
//
SDRAM Chip Select
output
DRAM_BA_0;
//
SDRAM Bank Address 0
48
output
DRAM_BA_1;
//
SDRAM Bank Address 0
output
DRAM_CLK;
//
SDRAM Clock
output
DRAM_CKE;
//
SDRAM Clock Enable
////////////////////////
inout
[7:0]
Flash Interface
FL_DQ;
output [21:0] FL_ADDR;
////////////////////////
//
FLASH Data bus 8 Bits
//
FLASH Address bus 22 Bits
output
FL_WE_N;
//
FLASH Write Enable
output
FL_RST_N;
//
FLASH Reset
output
FL_OE_N;
//
FLASH Output Enable
output
FL_CE_N;
//
FLASH Chip Enable
////////////////////////
inout
SRAM Interface ////////////////////////
[15:0] SRAM_DQ;
output [17:0] SRAM_ADDR;
//
SRAM Data bus 16 Bits
//
SRAM Address bus 18 Bits
output
Mask
SRAM_UB_N;
//
SRAM Low-byte Data
output
Mask
SRAM_LB_N;
//
SRAM High-byte Data
output
SRAM_WE_N;
//
SRAM Write Enable
output
SRAM_CE_N;
//
SRAM Chip Enable
output
SRAM_OE_N;
//
SRAM Output Enable
////////////////////
ISP1362 Interface
inout
[15:0] OTG_DATA;
output [1:0]
OTG_ADDR;
////////////////////////
//
ISP1362 Data bus 16 Bits
//
ISP1362 Address 2 Bits
output
OTG_CS_N;
//
ISP1362 Chip Select
output
OTG_RD_N;
//
ISP1362 Write
output
OTG_WR_N;
//
ISP1362 Read
output
OTG_RST_N;
//
ISP1362 Reset
output
OTG_FSPEED;
0 = Enable, Z = Disable
//
USB Full Speed,
output
OTG_LSPEED;
0 = Enable, Z = Disable
//
USB Low Speed,
input
OTG_INT0;
//
ISP1362 Interrupt 0
input
OTG_INT1;
//
ISP1362 Interrupt 1
input
OTG_DREQ0;
//
ISP1362 DMA Request 0
input
OTG_DREQ1;
//
ISP1362 DMA Request 1
output
OTG_DACK0_N;
//
ISP1362 DMA Acknowledge 0
output
OTG_DACK1_N;
//
ISP1362 DMA Acknowledge 1
////////////////////
LCD Module 16X2
////////////////////////////
49
inout
[7:0]
LCD_DATA;
//
LCD Data bus 8 bits
output
LCD_ON;
//
LCD Power ON/OFF
output
LCD_BLON;
//
LCD Back Light ON/OFF
output
0 = Write, 1 = Read
LCD_RW;
//
LCD Read/Write Select,
output
LCD_EN;
//
LCD Enable
output
LCD_RS;
Select, 0 = Command, 1 = Data
//
LCD Command/Data
////////////////////
SD Card Interface
inout
SD_DAT;
//
SD Card Data
inout
SD_DAT3;
//
SD Card Data 3
inout
Signal
SD_CMD;
//
SD Card Command
output
SD_CLK;
//
SD Card Clock
////////////////////////
I2C
////////////////////////
////////////////////////////////
inout
I2C_SDAT;
//
I2C Data
output
I2C_SCLK;
//
I2C Clock
////////////////////////
PS2
////////////////////////////////
input
PS2_DAT;
//
PS2 Data
input
PS2_CLK;
//
PS2 Clock
////////////////////
USB JTAG link
input
TDI;
// CPLD -> FPGA (data in)
input
TCK;
// CPLD -> FPGA (clk)
input
TCS;
// CPLD -> FPGA (CS)
output
TDO;
// FPGA -> CPLD (data out)
////////////////////////
////////////////////////////
VGA
////////////////////////////
output
VGA_CLK;
//
VGA Clock
output
VGA_HS;
//
VGA H_SYNC
output
VGA_VS;
//
VGA V_SYNC
output
VGA_BLANK;
//
VGA BLANK
output
VGA_SYNC;
//
VGA SYNC
output [9:0]
VGA_R;
//
VGA Red[9:0]
output [9:0]
VGA_G;
//
VGA Green[9:0]
output [9:0]
VGA_B;
//
VGA Blue[9:0]
////////////////
inout
Ethernet Interface
[15:0] ENET_DATA;
output
ENET_CMD;
Select, 0 = Command, 1 = Data
////////////////////////////
//
DM9000A DATA bus 16Bits
//
DM9000A Command/Data
50
output
ENET_CS_N;
//
DM9000A Chip Select
output
ENET_WR_N;
//
DM9000A Write
output
ENET_RD_N;
//
DM9000A Read
output
ENET_RST_N;
//
DM9000A Reset
input
ENET_INT;
//
DM9000A Interrupt
output
ENET_CLK;
//
DM9000A Clock 25 MHz
////////////////////
Audio CODEC
inout
AUD_ADCLRCK;
input
AUD_ADCDAT;
inout
AUD_DACLRCK;
output
AUD_DACDAT;
//
Audio CODEC DAC Data
inout
Stream Clock
AUD_BCLK;
//
Audio CODEC Bit-
output
Clock
AUD_XCK;
//
Audio CODEC Chip
////////////////////
TV Devoder
input
[7:0]
////////////////////////////
//
Audio CODEC ADC LR Clock
//
//
Audio CODEC ADC Data
Audio CODEC DAC LR Clock
////////////////////////////
TD_DATA;
//
TV Decoder Data bus 8 bits
input
TD_HS;
//
TV Decoder H_SYNC
input
TD_VS;
//
TV Decoder V_SYNC
output
TD_RESET;
//
TV Decoder Reset
////////////////////////
GPIO
////////////////////////////////
inout
[35:0] GPIO_0;
//
GPIO Connection 0
inout
[35:0] GPIO_1;
//
GPIO Connection 1
wire
CPU_CLK;
wire
CPU_RESET;
wire
CLK_18_4;
wire
CLK_25;
//wire vga_clk;
//
Flash
assign FL_RST_N
=
1'b1;
assign LCD_ON
=
1'b1;
//
LCD ON
assign LCD_BLON
=
1'b1;
//
LCD Back Light
//
//
16*2 LCD Module
All inout port turn to tri-state
51
assign SD_DAT
=
1'bz;
assign AUD_ADCLRCK
=
AUD_DACLRCK;
assign GPIO_0
=
36'hzzzzzzzzz;
assign GPIO_1
=
36'hzzzzzzzzz;
//
Disable USB speed select
assign OTG_FSPEED
=
1'bz;
assign OTG_LSPEED
=
1'bz;
//
Turn On TV Decoder
assign TD_RESET
//
=
1'b1;
Set SD Card to SD Mode
assign SD_DAT3
Reset_Delay
=
1'b1;
delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET));
Pll_ALL PLL1
(.areset(!CPU_RESET),.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK),.c2(CLK_18_4));
//actuall output a 11.2896Mhz
//vgapll
system_0
PLL2
u0
(.inclk0(CLOCK_27),.c0(vga_clk));
(
// 1) global signals:
.clk(CPU_CLK),
.clk_50(CLOCK_50),
.reset_n(CPU_RESET),
// the_Audio_0
.iCLK_18_4_to_the_Audio_0(CLK_18_4),
.oAUD_BCK_from_the_Audio_0(AUD_BCLK),
.oAUD_DATA_from_the_Audio_0(AUD_DACDAT),
.oAUD_LRCK_from_the_Audio_0(AUD_DACLRCK),
.oAUD_XCK_from_the_Audio_0(AUD_XCK),
.VGA_BLANK_from_the_de2_vga_raster_inst(VGA_BLANK),
.VGA_B_from_the_de2_vga_raster_inst(VGA_B),
.VGA_CLK_from_the_de2_vga_raster_inst(VGA_CLK),
52
.VGA_G_from_the_de2_vga_raster_inst(VGA_G),
.VGA_HS_from_the_de2_vga_raster_inst(VGA_HS),
.VGA_R_from_the_de2_vga_raster_inst(VGA_R),
.VGA_SYNC_from_the_de2_vga_raster_inst(VGA_SYNC),
.VGA_VS_from_the_de2_vga_raster_inst(VGA_VS),
// the_VGA_0
//
--
.VGA_BLANK_from_the_VGA_0(VGA_BLANK),
//
--
.VGA_B_from_the_VGA_0(VGA_B),
//
--
.VGA_CLK_from_the_VGA_0(VGA_CLK),
//
--
.VGA_G_from_the_VGA_0(VGA_G),
//
--
.VGA_HS_from_the_VGA_0(VGA_HS),
//
--
.VGA_R_from_the_VGA_0(VGA_R),
//
-- .VGA_SYNC_from_the_VGA_0(VGA_SYNC),
//
-- .VGA_VS_from_the_VGA_0(VGA_VS),
//
-- .iCLK_25_to_the_VGA_0(CLK_25),
//
//
// the_SD_CLK
//
-- .out_port_from_the_SD_CLK(SD_CLK),
//
//
// the_SD_CMD
//
-- .bidir_port_to_and_from_the_SD_CMD(SD_CMD),
//
//
//
// the_SD_DAT
//
.bidir_port_to_and_from_0the_SD_DAT(SD_DAT),
// the_SEG7_Display
.oSEG0_from_the_SEG7_Display(HEX0),
.oSEG1_from_the_SEG7_Display(HEX1),
.oSEG2_from_the_SEG7_Display(HEX2),
.oSEG3_from_the_SEG7_Display(HEX3),
.oSEG4_from_the_SEG7_Display(HEX4),
.oSEG5_from_the_SEG7_Display(HEX5),
.oSEG6_from_the_SEG7_Display(HEX6),
.oSEG7_from_the_SEG7_Display(HEX7),
// the_DM9000A
53
.ENET_CLK_from_the_DM9000A(ENET_CLK),
.ENET_CMD_from_the_DM9000A(ENET_CMD),
.ENET_CS_N_from_the_DM9000A(ENET_CS_N),
.ENET_DATA_to_and_from_the_DM9000A(ENET_DATA),
.ENET_INT_to_the_DM9000A(ENET_INT),
.ENET_RD_N_from_the_DM9000A(ENET_RD_N),
.ENET_RST_N_from_the_DM9000A(ENET_RST_N),
.ENET_WR_N_from_the_DM9000A(ENET_WR_N),
.iOSC_50_to_the_DM9000A(CLOCK_50),
// the_ISP1362
.OTG_ADDR_from_the_ISP1362(OTG_ADDR),
.OTG_CS_N_from_the_ISP1362(OTG_CS_N),
.OTG_DATA_to_and_from_the_ISP1362(OTG_DATA),
.OTG_INT0_to_the_ISP1362(OTG_INT0),
.OTG_INT1_to_the_ISP1362(OTG_INT1),
.OTG_RD_N_from_the_ISP1362(OTG_RD_N),
.OTG_RST_N_from_the_ISP1362(OTG_RST_N),
.OTG_WR_N_from_the_ISP1362(OTG_WR_N),
// the_button_pio
.in_port_to_the_button_pio(KEY),
// the_lcd_16207_0
.LCD_E_from_the_lcd_16207_0(LCD_EN),
.LCD_RS_from_the_lcd_16207_0(LCD_RS),
.LCD_RW_from_the_lcd_16207_0(LCD_RW),
.LCD_data_to_and_from_the_lcd_16207_0(LCD_DATA),
// the_led_green
.out_port_from_the_led_green(LEDG),
// the_led_red
.out_port_from_the_led_red(LEDR),
// the_sdram_0
.zs_addr_from_the_sdram_0(DRAM_ADDR),
54
.zs_ba_from_the_sdram_0({DRAM_BA_1,DRAM_BA_0}),
.zs_cas_n_from_the_sdram_0(DRAM_CAS_N),
.zs_cke_from_the_sdram_0(DRAM_CKE),
.zs_cs_n_from_the_sdram_0(DRAM_CS_N),
.zs_dq_to_and_from_the_sdram_0(DRAM_DQ),
.zs_dqm_from_the_sdram_0({DRAM_UDQM,DRAM_LDQM}),
.zs_ras_n_from_the_sdram_0(DRAM_RAS_N),
.zs_we_n_from_the_sdram_0(DRAM_WE_N),
// the_sram_0
.SRAM_ADDR_from_the_sram_0(SRAM_ADDR),
.SRAM_CE_N_from_the_sram_0(SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_0(SRAM_DQ),
.SRAM_LB_N_from_the_sram_0(SRAM_LB_N),
.SRAM_OE_N_from_the_sram_0(SRAM_OE_N),
.SRAM_UB_N_from_the_sram_0(SRAM_UB_N),
.SRAM_WE_N_from_the_sram_0(SRAM_WE_N),
// the_switch_pio
.in_port_to_the_switch_pio(SW),
// the_tri_state_bridge_0_avalon_slave
.select_n_to_the_cfi_flash_0(FL_CE_N),
.tri_state_bridge_0_address(FL_ADDR),
.tri_state_bridge_0_data(FL_DQ),
.tri_state_bridge_0_readn(FL_OE_N),
.write_n_to_the_cfi_flash_0(FL_WE_N),
// the_uart_0
.rxd_to_the_uart_0(UART_RXD),
.txd_from_the_uart_0(UART_TXD)
);
I2C_AV_Config
u1
(
//
Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[0]),
//
I2C Side
55
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT)
Endmodule
);
56
APPENDIX B
Source code for the software part C code for file “hello_world.c”
#define TESTFRAME 800
#include "basic_io.h"
#include "basic.h"
#include "header_reader.h"
#include "get_scalefactor.h"
#include "requantize.h"
#include "huffman_decode.h"
#include "reorder.h"
#include "joint_stereo.h"
#include "antialias.h"
#include "hybrid.h"
#include "subbandsynthesis.h"
#include "math.h"
#include "alt_types.h"
#include "io.h"
#include "system.h"
#include "stdio.h"
#define IOWR_LED_DATA(base, offset, data) \
IOWR_16DIRECT(base, (offset) * 2, data)
#define IORD_LED_DATA(base, offset) \
IORD_16DIRECT(base, (offset) * 2)
#define IOWR_LED_SPEED(base, data) \
IOWR_16DIRECT(base + 32, 0, data)
unsigned long F32ToHex(float valueF)
{
57
unsigned long* valueL = (unsigned long *) &valueF;
return *valueL;
}
inlineint gen_wave32 (float flt)
{
unsigned long
hex=0;
unsignedintexp,outcome;
unsigned long
fraction;
unsigned char sign_whole;
unsigned char sign_exp;
unsigned long result;
unsigned long result2;
hex=F32ToHex(flt);
fraction=hex&0x007FFFFF;
exp=127-((hex&0x7F800000)>>23);
//sign_exp=((exp&0x800)>>11);
//exp=exp&0x7FF;
sign_whole=(hex&0x80000000)>>31;
fraction=fraction|0x00800000;
result=(fraction<<7)>>(exp-1);
result&=0x00FF0000;
result>>=16;
// outcome=result;
return result;
}
void main()
{
unsigned char *address_of_first_frame;
unsigned char *index;
unsigned char valid[2]={1,1};
58
unsigned long intsycnword_count=0;
unsigned char ii=0; //This variable is used to denote the number of frame that are being
analyzed.
int clip=0;
intvga,vga_temp;
printf("OK start.\n");//test;
find_the_first_frame(&address_of_first_frame,&sycnword_count);
frame_stat=0;//test;
sycnword_count=sycnword_count-2;
block_type_0_count=0;//test;
//printf("address_of_first_frame is %d\n",address_of_first_frame data_header);//test;
index=address_of_first_frame;
si[0].main_data_end=0;si[1].main_data_end=0;
initialize_huffman();
for(frameNum=1;frameNum<TESTFRAME+1;frameNum++)
{
ii++;
if(ii>1) ii=0;
header_reader(&index,&sycnword_count,&header_info[ii],&si[ii],&si[bit_add(ii)],&main_data
_beg_bs[ii],&valid[ii]);
/*if((valid[1]==1)&&(valid[0]==1))
{
//printf("I have found the %dst frame starting at this
address:%d\n",frameNum,index-header_info[ii].frame_length-data_header);
}
else
{
//printf("bad frame detected.I quit.\n");exit(0);
}*/
59
intch,gr;
for(gr=0;gr<grNum;gr++)
{gr_global=gr;
for(ch=0;ch<stereo;ch++)
{
get_scale_factors(&si[ii],&scalefac,gr,ch,main_data_beg_bs[ii]);
//printf("start of huffman\n");
huffman_decode(is, &si[ii], ch, gr,&header_info[ii],&main_data_beg_bs[ii]);
main_data_beg_bs[ii].byte_idx_ptr+=(si[ii].ch[ch].gr[gr].part2_3_length/8);
if(main_data_beg_bs[ii].bit_idx>=(si[ii].ch[ch].gr[gr].part2_3_length%8))
{
main_data_beg_bs[ii].bit_idx-=(si[ii].ch[ch].gr[gr].part2_3_length%8);
}
else
{
main_data_beg_bs[ii].byte_idx_ptr++;
main_data_beg_bs[ii].bit_idx=main_data_beg_bs[ii].bit_idx+8si[ii].ch[ch].gr[gr].part2_3_length%8;
}
//printf("start of requantize\n");
requantize(&header_info[ii],&scalefac,&si[ii],is,ro[ch],gr,ch);
//printf("end of requantize\n");
//print_scalefac(frameNum, gr, ch, si[ii]);//test;
//print_requantize(frameNum,gr,ch,ro[ch]);//test;
}
//printf("start of stereo\n");
join_stereo(ro,lr,&scalefac,&(si[ii].ch[ch].gr[gr]),&header_info[ii]);
for(ch=0;ch<stereo;ch++)
{
ch_global=ch;
reorder (lr[ch],re,&(si[ii].ch[ch].gr[gr]),&header_info[ii]);
antialias(re, hybridIn, &(si[ii].ch[ch].gr[gr]), &header_info[ii]);
60
for(vga=0;vga<7;vga++){
vga_temp=(vga<<3)+vga;
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp,350gen_wave32(hybridIn[vga][1]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+1,350gen_wave32(hybridIn[vga][3]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+2,350gen_wave32(hybridIn[vga][5]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+3,350gen_wave32(hybridIn[vga][7]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+4,350gen_wave32(hybridIn[vga][9]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+5,350gen_wave32(hybridIn[vga][11]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+6,350gen_wave32(hybridIn[vga][13]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+7,350gen_wave32(hybridIn[vga][15]));
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, vga_temp+8,350gen_wave32(hybridIn[vga][17]));
}
IOWR_LED_DATA(DE2_VGA_RASTER_INST_BASE, 63,350-gen_wave32(hybridIn[7][7]));
unsigned char sb=0;
unsigned char ss=0;
for (sb=0; sb<SBLIMIT; sb++)
{
hybrid(hybridIn[sb], hybridOut[sb], sb, ch,
&(si[ii].ch[ch].gr[gr]),&header_info[ii]);
}
//printf("done.\n");
for (ss=0;ss<18;ss++)
for (sb=0; sb<SBLIMIT; sb++)
if ((ss%2) && (sb%2))
hybridOut[sb][ss] = -hybridOut[sb][ss];
//print_hybrid_output(frameNum,gr,ch,hybridOut);//test;
//printf("synthesis start\n");
for (ss=0;ss<18;ss++)
{
ss_global=ss;
61
for (sb=0; sb<SBLIMIT; sb++)
polyPhaseIn[sb] = hybridOut[sb][ss];
SubBandSynthesis (polyPhaseIn, ch,&(pcm_output[frameNum1][gr_global][ch_global][ss_global][0]));
}
//printf("synthesis done\n");
}
//print_pcm_sample(frameNum,gr,pcm_sample);//test;
//file_output(pcm_sample,fp,&sample_frames);
}
printf("%d ",frameNum);
}
printf("done\n");
while(1)
{
for(frameNum=0;frameNum<TESTFRAME;frameNum++)
{//printf("\nframe%d\n",frameNum);
for(gr_global=0;gr_global<2;gr_global++)
{//printf("\ngr%d\n",gr_global);
for(ch_global=0;ch_global<stereo;ch_global++)
{//printf("\nchannel%d\n",ch_global);
for (ss_global=0;ss_global<18;ss_global++)
{//printf("\nss%d\n",ss_global);
for(pcm_cnt_global=0;pcm_cnt_global<SBLIMIT;)
{
if(!IORD_16DIRECT(0x00681104,0))
{
usleep(13);
//
short monitor;
//
monitor=pcm_output[frameNum][gr_global][ch_global][ss_global][pcm_cnt_global];
//
printf(" %d
",pcm_output[frameNum][gr_global][ch_global][ss_global][pcm_cnt_global]);
IOWR_16DIRECT(0x00681104,0,(unsigned
short)pcm_output[frameNum][gr_global][ch_global][ss_global][pcm_cnt_global]);
pcm_cnt_global+=2;
62
}
}
}
}
}
}
}
//----------------------test information print out---------------------------;
/* printf("Frame_stat is %d\n",frame_stat);printf("bad_block_count
is %d\n",bad_block_count);
printf("big_value_0_count is %d\n",big_value_0_count);
printf("big_value_1_count is %d\n",big_value_1_count);
printf("block_type_0_count is %d\n",block_type_0_count);*/
//printf("index taken by next circulation is %d\n",index);
//printf("ptr in main_data_bs structure, bit_idx is %d, byte_idx(offset) is %d.\n",
main_data_bs.bit_idx, (unsigned long int)(main_data_bs.byte_idx_ptrdata_header));printf("\n");}
//byte_idx tells you the location of maindata in forms of
point of data_header
offset from the starting
/*printf("ht[33] info :---------------\n");
{
printf("table name is %s"
,ht[33].tablename);
printf("xlen is:%d
",ht[33].xlen);
printf("ylen is:%d
",ht[33].ylen);
printf("lintbis is:%d
",ht[33].linbits);
printf("treelen is:%d
",ht[33].treelen);
printf("the first
2 values are:0x%x 0x%x
",ht[33].val[0][0],ht[33].val[0][1]);
printf("the second 2 values are:0x%x 0x%x
",ht[33].val[1][0],ht[33].val[1][1]);
printf("the third
\n",ht[33].val[2][0],ht[33].val[2][1]);
}*/
}
2 values are:0x%x 0x%x