Coarse Grain Reconfigurable Architectures

Transcription

Reiner Hartenstein, University of Kaiserslautern, Germany
[email protected]
http://kressarray.de
Enabling Technologies for
Reconfigurable Computing
Schedule
Xputer Lab
July 8, 2002, ENST, Paris, France
University of Kaiserslautern
time
Reiner Hartenstein
University of
Kaiserslautern
Enabling Technologies for
Reconfigurable Computing and
Software / Configware Co-Design
Part 4:
Recent developments
Reconfigurable Computing (RC)
xx.00 – xx.30
coffee break
xx.30 – xx.00
Design / Compilation Techniques
xx.00 – xx.00
lunch break
xx.00 – xx.30
Resources for Data-Stream-based RC
xx.30 – xx.00
coffee break
xx.00 – xx.30
FPGAs: recent developments
Opportunities by new patent laws ?
• to clever guys being keen on patents:
• don‘t file for patent following details !
• everything shown in this presentation
has been published years ago
Xputer Lab
3
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
Configware heading for mainstream
4
bleeding edge designs
Xputer Lab
• Configware market taking off for mainstream
• FPGA-based designs more complex, even SoC
• No design productivity and quality without good
configware libraries (soft IP cores) from various
application areas.
• Growing no. of independent configware houses
(soft IP core vendors) and design services
• AllianceCORE & Reference Design Alliance
• Currently the top FPGA vendors are the key
innovators and meet most configware demand.
>> Configware Market
Xputer Lab
2
-.
Xputer Lab
slot
xx.30 – xx.00
5
• Infinite amount of gates not yet available on a chip
• 3 mio gates (10 mio in 2003 ?) far away from "infinite"
• Bleeding edge designs only with sophisticated EDA tools
• Excessive optimization needed
• Hardware epertise is inevitable for the designer.
• improve and simplify the design flow the user
• provide rich configware libraries of soft IP cores,
• control appl., networking, wireless telecommunication, data
communication, embedded and consumer markets.
Enabling Technologies for Reconfigurable Computing
and Software / Configware Co-Design,
ENST, Paris, 8 July 2002
#
6
Part 4:
Recent Developments
[email protected]
Xputer Lab
Configware (soft IP Products)
Xputer Lab
• For libraries, creation and reuse of configware
• Select EDA quality / productivity, not FPGA architectures
• EDA often has massive software quality problems
• Customer: highest priority EDA center of excellence
• To search for IPs see: List of all available IP
• The AllianceCORE program is a cooperation
between Xilinx and third-party core developers
–
–
–
–
–
• The Xilinx Reference Design Alliance Program
• The Xilinx University Program
• LogiCORE soft IP with LogiCORE PCI Interface.
7
OS for FPGAs
Xputer Lab
•Full design flow from Cadence, Mentor, & Synopsys
• separate EDA software market, comparable to
the compiler / OS market in computers,
•Xilinx Software AllianceEDA Program:
• Cadence, Mentor, Synopsys just jumped in.
–Alliance Series Development System.
• < 5% Xilinx / Altera income from EDA SW
• Changing EDA Tools Market
–Xilinx Foundation Series ISE (Integrated Synthesis Environment)
–free WebPOWERED SW w. WebFitter & WebPACK-ISE
Altera
Cadence
Mentor Graphics
Synopsys
Xilinx
9
–Foundation Series Development Systems.
• Major configware
EDA vendors
–
–
–
–
–
–StateCAD XE and HDL Bencher
–Foundation Base Express
–Foundation ISE Base Express
Foundation ISE Base Express
• ModelSim Xilinx Edition
(ModelSim XE)
• Chipscope ILA
• The Xilinx System
Generator
• XPower
10
Altera EDA
Xputer Lab
• Modular Design
EDA Software for Xilinx
Xputer Lab
• Forge Compiler
collecting EDA expertise and EDA user experience
to assemble best possible tool environments
for optimum support design teams
to cope with interoperability problems
to keep track with the EDA scene as a rapidly moving target
• being fabless, FPGA vendors spend most qualified manpower
in development of EDA, IP cores, applications , support
• Xilinx and Altera are morphing into EDA companies.
8
• Consultants
Xputer Lab
EDA as the Key Enabler (major EDA vendors)
• Altera was founded in June 1983
• JBits SDK
• EDA: synthesis, place & route, and, verification
• The Xilinx XtremeDSP
Initiative
• Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families
• MAX+PLUS II: FLEX, ACEX & MAX families
• MathWorks / Xilinx
Alliance
• Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity
deliver a design design software to support Altera SOPC solutions.
• Mentor: only EDA vendor w. complete design environment f. APEX
II incl. IP, design capture, simulation, synthesis, and h/s coverification
• System Generator
• Wind River / Xilinx
alliance
• Configware: Altera offers over a hundred IP cores
• Third party IP core design services and consultants
11
#
12
Part 4:
Recent Developments
[email protected]
Cadence
Xputer Lab
Mentor Graphics
Xputer Lab
• FPGA Designer: top-down FPGA design system,
• System Design and Verification.
• high-level mapping, architecture-specific optimization,
• PCB design and analysis:
• Verilog,VHDL, schematic-level design entry.
• IC Design and Verification
• Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer
• shifts ASIC design flow to FPGAs (Altera, Xilinx)
• FPGAs simulated by themselves using Cadence's VerilogXL or Leapfrog VHDL simulators and
–
–
–
–
• simulated w. rest of the system design w. Logic
Workbench board/system verification env‘ment.
• Libraries for the leading FPGA manufacturers.
13
14
Synopsys
Xputer Lab
by FPGA Advantage with IP support
by ModuleWare,
Xilinx CORE Generator
Altera MegaWizard integration,
>> FPGA Market
Xputer Lab
•
Configware Market
• FPGA Compiler II
•
FPGA Market
•
• Version of ASIC Design Compiler Ultra
•
•
• Block Level Incremental Synthesis (BLIS)
•
• ASIC <-> FPGA migration
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
• Actel, Altera, Atmel, Cypress, Lattice,
Lucent, Quicklogic, Triscend, Xilinx
15
Xputer Lab
Top 4 PLD Manufacturers 2000
Lattice
15%
Actel
6%
Source:
IC Insights Inc.
Xilinx
42%
Meanwhile,
Xilinx acquired
Philips' MOS PLD
business,
Altera
37%
FPGA market 1998 / 1999
Xputer Lab
16
Lattice
purchased Vantis.
.
$3.7 Bio
Top 4 PLD Manufacturers 2000
17
1999 rank
1
2
3
4
5
6
7
8
#
Xilinx
Altera
Lattice
Actel
Lucent
Cypress
Quicklogic
Atmel
18
global sales (mio $)
1998
1999
629
899
654
837
206
410
154
172
100
120
41
43
30
40
32
38
Part 4:
Recent Developments
[email protected]
Xputer Lab
.... into every application
Xputer Lab
.... going into every type of application
[Gordon Bell]
• [Dataquest] PLD market > $7 billion by 2003.
• „ fastest growing segment of semiconductor
market.“
• IP reuse and "pre-fabricated" components for
the efficiency of design and use for PLDs
• FPGAs are going into every type of application.
19
Xilinx
Xputer Lab
20
Xilinx Flexware
Xputer Lab
• fabless FPGA semi vendor, San Jose, Ca, founded 1984
• Virtex, Virtex-II, first w. 1 mio system gates.
– Virtex-E series > 3 mio system gates.
• key patents on FPGAs (expiring in a few years)
• Virtex-EM on a copper process & addit. on chip memory f. network switch appl.
• The Virtex XCV3200E > 3 million gates, 0.15-micron technology,
• Fortune 2001: No. 14 Best Company to work for in (intel:
no. 42, hp no. 64, TI no. 65).
• Spartan, Spartan-XL, Spartan-II
– for low-cost, high volume applications as ASIC replacements
– Multiple I/O standards, on-chip block RAM, digital delay lock loops
– eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers
• DARPA grant (Nov‘99) to develop Jbits API tools for
internet reconfigurable / upgradable logic (w. VT)
• XC4000XV, XC4000XL/XLA, CPLD: low-cost families
• Less brilliant early/mid 90ies (president Curt Wozniak):
1995 market share from 84% down to 62% [Dataquest]
– rapid development, longer system life, robust field upgradability
– support In-System Programming (ISP), in-board debugging,
– test during manufacturing, field upgrades, full JTAG compliant interface
• As designs get larger, Xilinx losed its advantage (bugfixes
did not require to burn new chips)
• CoolRunner: low power, high speed/density, standby mode.
• Military & Aerospace: QPRO high-reliability QML certified
• Configuration Storage Devices
• meanwhile, weeks of expensive debug time needed
21
Altera Flexware
Xputer Lab
22
Triscend CSoC
Xputer Lab
• Newer families: APEX 20KE, APEX 20KC, APEX II, MAX
7000B, ACEX 1K, Excalibur, Mercury families.
[Kean]
Configurable system logic
– Apex EP20K1500E (0.18-µ), up to 2.4 mio system gates,
ARM
– APEX II (all-copper 0.13-µ) f. data path applications, supports
many I/O standards. 1-Gbps True-LVDS performance
Digital Filter
Display Interface
Viterbi
A/D Interface
– wQ2001, an ARM-based Excalibur device
CSI Socket
• Altera mainstream: MAX 7000A, 3000A; FLEX 6000,
10KA, 10KE; APEX 20K families.
Configurable System Interconnect (CSI) Bus
• Mature and other : Classic, MAX 7000, 7000S, 9000;
FLEX 8000, 10K families.
23
Memory
#
Other System Resources
24
Part 4:
Recent Developments
[email protected]
>> Embedded Systems (Co-Design)
Xputer Lab
Xputer Lab
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
[à la S. Guccione]
25
Overcome traditional separate design flow
Xputer Lab
[à la S. Guccione]
Netlist
Route
Netlister
HDL
Place
and
JBits
API
Compiler
Schematics/
Netlister
Place
and
Netlist
Overcome traditional co-processing design
separate flow -> JBits Design Flow
[à la S. Guccione]
HDL
Netlister
26
Schematics/
HDL
Compiler
HLL
Schematics/
Bitstream
HLL
Xputer Lab
Goal: away from complex design flow
Netlist
Place
and
Route
User
Java
Code
Java
Compiler
Executable
.
.
Route
.
.
Bitstream
Bitstream
User
Code
Compiler
User
Code
Executable
27
Xputer Lab
Compiler
Executable
Embedded hardw. CPU & memory cores
on chip.
Xputer Lab
28
new directions in application development
• new directions in application development.
HLL
• aut. partitioning compilers: designer productivity
Compiler
• like CoDe-X (Jürgen Becker, Univ. of Karlsruhe),
• supports Run-Time Reconfiguration (RTR), a key
enabler of error handling and fault correction by
partial re-routing the FPGA at run time, as well as
remote patching for upgrading, remote debugging,
and remote repair by reconfiguration - even over
the internet.
FPGA core
HLL
Compiler
CPU Memory
core
core
[à la S. Guccione]
29
#
30
Part 4:
Recent Developments
[email protected]
>> Run-Time Reconfiguration (RTR)
Xputer Lab
Xputer Lab
• on-board microprocessor CPU is available
anyhow - even along with a little RTOS
• use this CPU for configuration management
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
RTR System Design
HLL
31
hard CPU & memory core on same chip
Xputer Lab
Xputer Lab
HLL
CPU use for configuration management
Compiler
32
Converging factors for RTR
• Converging factors make RTR based system design viable
• 1) million gate FPGA devices and co-processing with
standard microprocessors are commonplace
• direct implementation of complex algorithms in FPGAs.
• This alone has already
revolutionized FPGA design.
JBits
• 2) new tools like Xilinx Jbits
API
software tool suite directly
support coprocessing and RTR.
User
Compiler
FPGA core
RTR System Design
HLL
Compiler
33
CPU Memory
core
core
Java
Code
RTR
Xputer Lab
Executable
Run-time Mapping
Xputer Lab
• divides application into a series of sequentially executed stages, each
implemented as a separate execution module.
• Partial RTR partitions these stages into finer-grain sub-modules to be
swapped in as needed.
• Without RTR, all conf. platforms just ASIC emulators.
• needs a new kind of application development environments.
• directly support development and debugging of RTR appl.
• essential for the advancement of configurable computing
• will also heavily influence the future system organization
• Xilinx, VT, BYU work on run-time kernels, run-time support, RTR
debugging tools and other associated tools.
• smaller, faster circuits, simplified hardware interfacing, fewer IOBs;
smaller, cheaper packages, simplified software interfaces.
34
Java
Compiler
35
• run-time reconfigurable are: Xilinx VIRTEX FPGA family
• RAs being part of Chameleon CS2000 series systems
• Using such devices changes many of the basic assumptions
in the HW/SW co-design process:
• host/RL interaction is dynamic, needs a tiny OS like eBIOS,
also to organize RL reconfiguration under host control
• typical goal is minimization of reconfiguration latency
(especially important in communication processors), to hide
configuration loading latency, and,
• Scheduling to find ’best’ schedule for eBIOS calls (C~side).
#
36
Part 4:
Recent Developments
[email protected]
>> Rapid Prototyping & ASIC Emulation
Xputer Lab
Xputer Lab
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
• ASIC emulation / Rapid Prototyping: to replace simulation
• Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor)
• from rack to board to chip (from other vendors, e. g.
Virtex and VirtexE family (emulate up to 3 million gates)
• Easy configuration using SmartMedia FLASH cards
• ASIC emulators will become obsolete within years
37
• By RTR: in-circuit execution debugging instead of emulation
38
>> Evolvable Hardware (EH)
Xputer Lab
ASIC emulation: a new business model ?
EH, EM, ...
Xputer Lab
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
39
• "Evolvable Hardware" (EH), "Evolutionary Methods" (EM),
„digital DANN“, "Darwinistic Methods", and biologically
inspired electronic systems
• new research area, also a new application area of FPGAs
• revival of cybernetics or bionics: stimulated by technology
• „evolutionary“ and „DNA“ metaphor create awareness
• EM sucks, also thru mushrooming funds in the EU, in
Japan, Korea, and the USA
• EM-related international conference series are in their
stormy visionary phase, like EH, ICES, EuroGP, GP, CEC,
GECCO, EvoWorkshops, MAPLD, ICGA
40
EH, EM, ...
Xputer Lab
• Shake-out phenomena expected, like in the past with
„Artificial Intelligence“
• should be considered as a specialized EDA scene,
focusing on theoretical issues.
• Genetic algorithms suck - often replacable by more
efficient ones from EDA
• It is recommendable to set-up an interwoven competence
in both scenes, EM scene and the highly commercialized
EDA scene
• EH should be done by EDA people, rather than EM freaks.
>> Academic Expertise
Xputer Lab
41
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
#
42
Part 4:
Recent Developments
[email protected]
BRASS (1)
Xputer Lab
BRASS (2)
Xputer Lab
• UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek
• HSRA. new FPGA (& related tools) supports pipelining, w.
retiming capable CLB architecture, implemented in a 0.4um
DRAM process supporting 250MHz operation
• The Pleiades Project, Prof. Jan Rabaey, ultra-low power highperformance multimedia computing through reconfiguration
of heterogeneous system modules, reducing energy by
overhead elimination, programmability at just right
granularity, parallellism, pipelining, dynamic voltage scaling.
• OOCG. Object Oriented Circuit-Generators in Java
• MESCAL (GSRC), the goal is: to provide a programmer's
model and software development environment for efficient
implementation of an interesting set of applications onto a
family of fully-programmable architectures /
microarchitectures.
• Garp integrates processor and FPGA; dev. in parallel w.
compiler - software compile techniques (VLIW SW
pipelining): simple pipelining schema f. broad class of loops.
• SCORE, a stream-based computation model - a unifying
computational model. Fast Mapping for Datapaths: by a treeparsing compiler tool for datapath module mapping
43
Berkeley claiming (1)
Xputer Lab
44
Berkeley claiming (2)
Xputer Lab
• SCORE, a stream-based computation model: the BRASS group claims
having solved the problem of primary impediment to wide-spread
reconfigurable computing, by a unifying computational model.
• Remark: The DPSS (Data Path Synthesis System) using
tree covering simultanous datapath placement and routing
has been published in 1995 by Rainer Kress
• Remark: clean stream-based model introduced ~1980: Systolic Array
• „Chip-in-a-Da2 Bee Project. Prof. Dr. Bob Broderson‘s
„radical rethink of the ASIC design flow aimed at
shortening design time, relying on stream-based DPU
arrays.“ [published in 2000]
• 1995: Rainer Kress. Introduces reconfigurable stream-based model
• Fast Mapping for Datapaths (SCORE): BRASS claims having
introduced 1998 the first tree-parsing compiler tool for datapath
module mapping ." Further, it is the first work to integrate
simultaneous placement with module mapping in a way that preserves
linear time complexity."
Xputer Lab
45
• Remark: the KressArray, a scalable rDPU array [1995] is
stream-based
.... Stream Processors - MSP-3
Xputer Lab
Berkeley: „Chip-in-a-Day“ Bee Project
• 3rd Workshop on Media and Stream Processors (MSP-3)
• Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting
a radical rethink of the ASIC design flow aimed at shortening
design time. Relying on stream-based DPU arrays (not rDPU and
related EDA tools. Davis: „ „... 50x decrease in power requ. over
typical TI C64X design.“
• http://www.pdcl.eng.wayne.edu/msp01
• in conj. w. 34th Int‘l Symp. on Microarchitecture (MICRO-34)
• http://www.microarch.org/micro34
• Austin, Texas, December 1-2, 2001
• Topics of interest include, but are not limited to:
• New design flow to break up the highly iterative EDA process,
allowing designers to spend more time defining the device and
far less time implementing it in silicon. „... developers to start by
creating data flow graphs rather than C code,„
– Hardware/Compiler techniques for improving memory
performance of media and stream-based processing
– Application-specific hardware architectures for graphics, video,
audio, communications, and other media and streaming
applications
– System-on-a-chip architectures for media & stream processors
– Hardware/Software Co-Design of media and stream processors
– and others ....
46
47
• It is stream-based computing by DPU array (hardwired DPA)
• For hardwired and reconfigurable DPU array and rDPU array
#
48
http://www.microarch.org/micro34
Part 4:
Recent Developments
[email protected]
Stanford thru BYU
Xputer Lab
Toronto thru Karlsruhe
Xputer Lab
• Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs.
• no activities seen other than YAFA (yet another FPGA application)
• UCLA: Prof. Jason Cong, expert on FPGA architectures and R& P
algorithms. 9 projects, mult. sponsors under California MICRO Program
• Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs„, a new
routing architecture, architecture-aware CAD, IP-aware SPS compiler
• USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable
computing: MAARC project, DRIVE project and Efficient SelfReconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation of
scalable multiprocessors.
• DEFACTO proj.: compilation - architecture-independent at all levels
• MIT. MATRIX web pages removed `99. „RAW project“: a conglomerate
• VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w.
Prof. Brad Hutchings, BYU on programming approaches for RTR Systems
• BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware
49 of JHDL sources
© Description
2002, [email protected]
Language) and compilation
into FPGAs.
• U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg.
• The group has dev. Transmogrifier C, a C compiler creating netlist for
Xilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs.
• Founder of Right Track CAD Corporation acquired by Altera in 1999
• Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff
Arnold) – Project Streams-C: programming FPGAs from C sources.
• Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins,
methods for MPEG-4 like multimedia applications on dynamically
reconfigurable platforms, & on reconf. instruction set processors.
• University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker:
hardware/software co-design, reconfigurable architectures & rel.
synthesis for future mobile communication systems & synthesis w.
• distributed internet-based CAD methods, partitioning co-compilers
>> ASICs dead ?
Xputer Lab
Xputer Lab
50
(When) Will FPGAs Kill ASICs?
[Jonathan Rose]
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead ?
•
Soft CPU
•
HLLs
•
Xputer Lab
51
ASICs Are Already Dead
My Position
[Jonathan Rose]
They Just Don’t Know It Yet!
Why? [Jonathan Rose]
Xputer Lab
•
•
•
•
•
•
•
1. You have to fabricate an ASIC
 Very hard, getting harder
2. An FPGA is pre-fabricated
 A standard part
 immense economic advantages
53
#
Making ASICs is Damn Difficult
[Jonathan Rose]
Testing
Yield
Cross Talk
Noise
Leakage
Clock Tree Design
Horrible very deep submicron effects we
don’t even know about yet
52
54
Part 4:
Recent Developments
[email protected]
Xputer Lab
Did I Mention Inventory? [Jonathan Rose]
[Jonathan Rose] FPGAs Give You
Xputer Lab
• ASIC users must predict # parts
– 2 or 3 months in advance!
• Instant Fabrication
• Never guess the Right Amount
– Get to Market Fast
– Fix ‘em quick
– Make Too Many – You Pay holding costs
– Make Too Few – Competitor gets the Sale
• Zero NRE Charges
– Low Risk
– Low Cost at good volume
55
Xputer Lab
[Jonathan Rose]
56
FPGAs: “Too Pricey & Too Slow ?”
What’s Wrong with This Picture?
Xputer Lab
[Jonathan Rose]
Embedded
FPGA Fabric
What About PLD
Cores on ASICs ?
• 9 Times Out of 10
– You make can the thing fast by breaking it
into multiple parallel slower pieces
[Jonathan Rose]
1. Still Have to Make the Chip
2. Need Two Sets of Software to Build It
• Custom IC Designer Can Make Logic
– 20x Faster,
– 20x Smaller than Programmable
– The ASIC Flow
– The PLD Flow
3. Have No Idea What to Connect the PLD Pins to
Xputer Lab
57
– Chances Are, You Are Going to Get It Wrong!
58
What’s Right with This Picture!
Embedded
CPU Serial Link,
Analog, “etc.”
[Jonathan Rose]
1. Pre-Fabricated
2. One CAD Tool Flow!
3. Can Connect Anything to Anything
 PLDs are built for general connectivity
>> Soft CPU
Xputer Lab
59
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
#
60
Part 4:
Recent Developments
[email protected]
Free 32 bit processor core
Xputer Lab
Processors in PLDs: Excalibur
Xputer Lab
Dual-Port
RAM
Single-Port
RAM
ARM 922T
Core
•High-Speed
Processors
Integrated
with PLDs
General Purpose
PLD
[Jonathan Rose]
61
Soft CPU: new job for compilers
Xputer Lab
62 Today!
Available
Some soft CPU core examples
Xputer Lab
FPGA
HLL
Xputer Lab
soft
CPU
Compiler
63
Memory
core
FPGA
architecture
32 bit
standard RISC
32 reg. by 32
LUT RAMbased reg.
Xilinx up to
100 on one
FPGA
platform
Nios
16-bit
instr. set
Altera
Mercury
Nios
50 MHz
32-bit
instr. set
Altera
22 D-MIPS
Nios
8 bit
Altera –
Mercury
gr1040
16-bit
gr1050
32-bit
My80
i8080A
FLEX10K30
or EPF6016
DSPuva16
16 bit DSP
Spartan-II
Nios Architecture (Altera)
core
architecture
platform
Leon
25 Mhz
SPARC
ARM7 clone
ARM
uP1232 8-bit
CISC, 32 reg.
200 XC4000E
CLBs
REGIS
8 bits Instr. +
ext. ROM
2 XILINX
3020 LCA
Reliance-1
12 bit DSP
Lattice
4 isp30256,
4 isp1016
1Popcorn-1
8 bit CISC
Altera, Lattice,
Xilinx
Acorn-1
Xputer Lab
1 Flex 10K20
YARD-1A
16-bit RISC,
2 opd. Instr.
xr16
RISC integer C
64
core
MicroBlaze
125 MHz 70
D-MIPS
old Xilinx FPGA
Board
SpartanXL
free DSP or Processor Cores
65
CPU core
Description
Language
Implementation
Reliance 1
12bit DSP and peripherals
Schematic
Viewlogic 7 Lattice CPLDs
PopCorn 1
small 8 bit CISC
Verilog
1 Lattice CPLD isp3256-90
Acorn 1
small 8 bit CISC
VHDL
Max2PlusII+ 1 Altera 10k20
16-bit DSP
A 16-bit Harvard DSP with
5 pipeline stages.
VHDL
Xilinx XC4000
Free-6502
6502 compatible core
VHDL
DLX
Generic 32-bit RISC CPU
VHDL
DLX2
Generic 32-bit RISC CPU
VHDL
GL85
i8085 clone
VHDL
AMD 2901
AMD 2901 4-bit slice
VHDL
AMD 2910
AMD 2910 bit slice
VHDL
i8051
8-bit micro-controller
VHDL
Synopsys
i8051
another i8051 clone
VHDL
Mentor Graphics
#
66
Synopsys
Part 4:
Recent Developments
[email protected]
FPGA CPUs in teaching and
academic research
Xputer Lab
• Michigan State
• Universidad de
Valladolid, Spain
• Virginia Tech
• Washington
University, St. Louis
• New Mexico Tech
• UC Riverside
• Tokai University,
Japan
• UCSC: 1990!
• Märaldalen University,
Eskilstuna, Sweden
• Chalmers University,
Göteborg, Sweden
• Cornell University
• Gray Research
• Georgia Tech
• Hiroshima City
University, Japan
67
Xilinx 10Mg, 500Mt, .12 mic
Xputer Lab
Soft rDPA feasible ?
Xputer Lab
Array I/O examples
data streams, or, from / to
embedded memory banks
Performance
1000
µProc
60%/yr..
100
1
1980
[à la S. Guccione]
DRAM
1990
2000
[à la S. Guccione]
69
HLL 2 Soft Array
Xputer Lab
DRAM
7%/yr..
data
streams,
or,
from / to
embedded
memory
banks
70
HLL 2 „flex“ rDPA
Xputer Lab
miscellanous
miscellanous
Compiler
soft CPU
HLL
Memory
[à la S. Guccione]
Processor-Memory
Performance Gap:
(grows 50% / year)
CPU
10
Xputer Lab
HLL
68
Compiler
CPU
Memory
[à la S. Guccione]
71
#
72
Part 4:
Recent Developments
[email protected]
>> HLLs
Xputer Lab
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
HLL
HLL
[à la S. Guccione]
Compiler
RTR System Design
74
HLLs for Hardware Design vs.
System Design vs. RTR System
Design
Xputer Lab
Compiler
System Design
73
HLL
Design
Xputer Lab
CPU and memory on Chip
Xputer Lab
Compiler
HLL
Compiler
HLL
HLL
[à la S. Guccione]
75
Jbit Environment
Xputer Lab
JRoute
API
CPU Memory
core
core
76
Design
Xputer Lab
RTP Core
Library
Compiler
[à la S. Guccione]
[à la S. Guccione]
FPGA core
HLL
Compiler
RTR System Design
Compiler
RTR System Design
System Design
JBits
API
User
Code
HLL
BoardScope
Debugger
Compiler
XHWIF
HLL
TCP/IP
Device
Simulator
77
Compiler
System Design
[à la S. Guccione]
#
78
Part 4:
Recent Developments
[email protected]
Embedded System Design
Xputer Lab
Xputer Lab
FPGA core
HLL
Compiler
CPU Memory
core
core
FPGA
HLL
Compiler
soft
CPU
[à la S. Guccione]
Xputer Lab
Memory
core
79
FPGA
>> Problems to be solved
•
Configware Market
•
FPGA Market
•
•
•
•
•
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
80
Why Can’t Reconfig. Software Survive?
>>> Coarse Grain
Xputer Lab
• Resource constraints/sizes are exposed:
– to programmer
– in low-level representation (netlist)
- END -
• Design revolves around device size
– Algorithmic structure
– Exploited parallelism
81
82
Schedule
Schedule
Xputer Lab
Xputer Lab
time
slot
08.30 – 10.00
10.00 – 10.30
coffee break
10.30 – 12.00
Stream-based Computing for RC
12.00 – 14.00
lunch break
14.00 – 15.30
Resources for RC
15.30 – 16.00
coffee break
16.00 – 17.30
17.30
end of seminar: thank you for attending
83
time
slot
08.30 – 10.00
10.00 – 10.30
coffee break
10.30 – 12.00
Stream-based Computing for RC
12.00 – 14.00
lunch break
14.00 – 15.30
Resources for RC
15.30 – 16.00
coffee break
16.00 – 17.30
#
84
Part 4:
Recent Developments

Coarse Grain Reconfigurable Architectures

Transcription

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