AnaPass, Inc.

Confidential
AnaPass
fast Mobile Serial Link
TM
AnaPass, Inc.
Jan. 2006
1
Confidential
2
AnaPass, Inc.
‰ Company Profile
– AnaPass, Inc. is a fabless semiconductor company founded in 2003, which
designs, develops, and markets cost-effective and innovative mixed-mode IC and IP
solutions focused on high-speed serial link technology specialized in display
and handset market.
– Employees
• Totally 29, including 18 engineers, all who hold MS/Ph.D degree from Seoul
National University, and have a work-experience at Samsung, LG, Hynix.
– Technology:
• Since the middle of 1990s, AnaPass has developed state of the art Serial Link
Technology. Based on a prior experience, AnaPass has introduced innovative
LVDS/TCON solutions for large flat panel display applications, and Mobile
Serial Link solutions for mobile handset applications. Also, AnaPass has
developed various LCD Driver/Controller solutions for mobile display
applications.
Confidential
Business Area/Product Portfolio
ANA3XXX
ANA3XXX
LVDS/TCON
LVDS/TCON
for Flat Panel Display of LCD Monitor,
for Flat Panel Display of LCD Monitor,
LCD TV, Notebook
LCD TV, Notebook
ANA5XXX
ANA5XXX
Mobile
MobileSerial
SerialLink
Link
ANA30XX
LVDS Core
AiPi Core
ANA33XX/34XX
LVDS Tx/Rx
ANA50XX
f-MSL Core
ANA5XXX
f-MSL Tx/Rx
for Multimedia
Mobile Application
for Multimedia Mobile Application
for Multimedia Mobile Application
ANA6XXX
ANA6XXX
LCD
Driver/Controller
LCD
Driver/Controller
for TFT-LCD Display Panel
for TFT-LCD Display Panel
ANA62XX
LDI w/ f-MSL
for Mobile Display
ANA35XX~38XX
TCON for FPD
3
Confidential
‰
‰ f-MSL
f-MSL for
for Mobile
Mobile Applications
Applications
4
Confidential
Multimedia Mobile Handset Application
5
6
Confidential
Serial Link for Mobile Handset Application
Conventional Parallel Line
Conventional Parallel Line
Flash
Flash
f MSL3
MSL1
LCD
SDRAM
SDRAM
Tx
Main
Proposed Serial Line
f MSL2
MSL3
Video Processor/
Application Processor
CPU
Video
Processor
Proposed Serial Line
f MSL3
MSL1
f MSL2
MSL3
Rx
Tx
Audio
I/F
USB
UART
I2C
GPIO
LCD
Rx
LCD I/F
(TFT)
Camera I/F
(CCD/CIS)
Camera module
Sub
Storage DMB
BB
I/F
I/F
Modem
(NAND,
(TS,
I/F
SD/MMC) CAS)
LCD module
Sub
Display
Main
Display
f-MSL1
f-MSL2
f-MSL3
f-MSL1
f-MSL2
f-MSL3
BB Modem
or AP
RF Transceiver
Base Band Modem
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7
Camera Data Transmission Rate
12bit bus
Transmission
12bit bus
Transmission
Data Rate
(Mbps)
700
30fps
15fps
15fps
8bit bus
YUV Transmission
600
5fps
500
400
300
5fps
200
100
0.3M
VGA
(480x640)
1M
SXGA
(1280x1024)
2M
UXGA
(1600x1200)
3M
QXGA
(2048x1536)
Pixels
Resolution
Confidential
8
LCD Image Data Transmission Rate
Data Rate
(Mbps)
24bit color
60fps
400
18bit color
60fps
300
200
18bit color
30fps
100
QCIF
QCIF+
QVGA
(132x176 (176x240 (240x320
)
)
)
Resolution
QCIF(132X176)
HVGA
(320x480
)
Color(Bit)
Frame(fps
)
16
30
Data
Rate(Mbps)
11.2
QCIF+(176X240
)
QVGA(240X320)
16
30
20.3
18
30
41.5
HVGA(320X480)
18
30
83.0
VGA(480X640)
18
30
165.9
VGA(480X640)
18
60
331.8
VGA(480X640)
24
60
442.4
Resolution
VGA
(480x640
)
Confidential
Advantage of Serial Link for Mobile Apps.
‰ The necessity of Serial Link interface
– Higher LCD Resolution/Larger Camera Image
• Image Data Size Increase
– Faster Data Rate required
• Wider bus (PCB size, FPC size, Connector, Wiring of hinge)
• Difficulty in mechanical design, Stress of FPC
• Higher cost of FPC, Connector & Camera/LCD Module
– EMI, Power Consumption Increase
• Degradation of RF Performance
• High drivability I/O required
• Limit of lower operation voltage
‰ The main benefits of Serial Link interface
– High-speed data transmission
– Reduced data transmission lines, Simple interface
• Lower Gate count, PCB size, FPC size, Connector
• Flexible Design
– Low voltage swing
• Lower power consumption
• Lower EMI noise
– Total BOM Reduction
Æ High speed serial link will be indispensable and mandatory !!!
9
Confidential
Advantage of Serial Link for Mobile Apps.
‰ Less number of wiring
Interface
Legacy Interface
Active Signals
f- MSL Active Signals
YUV 8-bit Camera
12
4
3:1
RGB 18-bit display
21
4
5.3: 1
RGB 24-bit display
28
4
7:1
16-bit CPU
22
4
5.5 : 1
‰ Lower EMI Noise
– Serial Link Interface
(2 differential pairs)
vs.
Savings Ratio
CMOS Interface
10
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Mobile Serial Link Comparison (I)
Product / Scheme / Applications
MIPI
/SMIA
Standard
VESA
Standard
Samsung
MC
NEC
MCMADS
Throughput
per channel
Total
Throughput
Power
Etc
DC: 3~4mA
AC: 2.5~3.5uA/MHz
Supply: 1.4~1.95V
Logic: 1.0~1.95V
Mar/’04
CSI ver1.0: Camera
Serial Interface
2kinds/2chips for Tx,
Rx
Sub LVDS, 1way
1 data: 8bit, V/H SYNC
1 clock: ~208MHz
208Mbps/ch
208Mbps /w 1ch
CSI ver2.0: Camera
Serial Interface
On-going
670Mbps/ch
670Mbps /w 1ch
DSI ver1.0,2.0: Display
Serial Interface
On-going
TBD
TBD
MDDI :LVDS-like,
Differential
2kinds/2chips for Host,
Client
Data: Bi-directional
Strobe: Host to Client
Types I/II/III/IV:
1 Strobe pair plus
1/2/4/8 data pairs
400Mbps/ch
TI:400Mbps/1ch
TII:800Mbps/2ch
TIII:1.6Gbps/4ch
TIV:3.2Gbps/8ch
MC4: Media
coprocessor, LCD
Ctrl for QVGA/QCIF,
/w Frame buffer
(230KB), 16bit GPIO,
32bit AMBA, 4ch
PWM, SPI
Type-1 MDDI Display
Client Serial interface
Half-Duplex /w
Differential & Bidirectional
1 data: 18bit
1 strobe: Host to Client
150Mbps/ch
50MHz(AHB
bus)
uPD161451: LCD
(RGB I/F mode)
Interface, Bridge IC
uPD161832/33: Low
Temperature p-Si TFT
LCD Driver IC
Current Mode
Differential Signaling
Half-Duplex /w
Differential & unidirectional
1 data: 16/18bit
1 clock: ~62.5MHz
125Mbps/ch
Serial interface
between MSM6150,
6550, 7XXX
150Mbps /w 1ch
Internal: 1.40~1.60V
External: 2.70~3.00V
5 PD_mode: Gated
clock
0.13um LP Process,
MP @ 4Q/’04
100-pin FBGA
(8mmX8mm),
96-pin COF
(4.24mm X 4.14mm)
125Mbps /w 1ch
250Mbps /w 2ch
DC: 1.2mA @60Mbps
Internal: 1.5V
interface: 1.85V
62.5 MHz Max
(4mmX4mm),
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12
Mobile Serial Link Comparison (II)
Product / Scheme / Applications
NS
MPL
LM2501: Camera
1kind/2chips
configurable as a
Serializer or
Deserializer
LM2502: LCD Display
1kind/2chips pin
selectable as a Master
or Slave
Fairchild
µSerDes
Rohm
MSDL
SeikoEpson/
Renesas
MVI
Anapass
f-MSL
Current-mode/Single
ended, Unidirectional,
Half duplex
1 data: 8bit, V/H SYNC
1 clock for PCLK
(4~16MHz)
1 WCLK (4~28MHz)
Current-mode/Single
ended, Bi-directional,
Half duplex
2 data: 16bit, CPU mode
1 clock: PCLK
Throughput per
channel/ Total
Power
Etc
160Mbps/ch
160Mbps /w 1ch
650uA/ch
PD-mode: ~10uA
Supply: 1.7~3.1V & 2.9~3.1V
Logic: 1.8~3.0V
3.5mm X 4.5mm X
0.6mm
24-Lead Ultra Thin
CSP
160Mbps/ch
320Mbps /w 2ch
650uA/ch
PD-mode: ~10uA
Supply: 1.7~3.3V & 2.9~3.3V
Logic: 2.9~3.3V
4.0mm X 4.0mm X
1.0mm, 0.5mm pitch
49(40) Lead FBGA
style
Data: 780MB/s
typical operating
conditions: 5mA
Standby mode: 100nA
3.5mm X 3.5mm
BGA
6mm X 6mm MLP
5.0mm X 5.0mm X
1.0mm, 0.5mm pitch
VBGA063T050
FIN12A(C):12bit SerDes
FIN22A(C) 22bit SerDes
FIN24(C):24bit SerDes
LpLVDS/CTL
1 data
1 clock
BU7280GLU:
1kind/2chips
configurable as a
Serializer or
Deserializer
Current-mode/Differential,
Bi-directional, Half duplex
2 data
1 clock: ~10MHz
1st: 100Mbps/ch
2nd: 200Mbps/ch
1st: 200Mbps /w 2ch
2nd: 200Mbps /w 1ch
IO: 2mA, Core:5mA @ 6MHz
PD-mode: ~10uA
H-sink: 600uA, V-sink:250uA
Supply: 1.70~2.05V
Logic: 2.55~3.15V
1kind/2chips Full duplex
SERDES for
Camera/Display
Sub LVDS, Full-/Half- duplex
1f-data,1clock : ~200MHz
1 r-data,1 strobe clock
1st: 200Mbps/ch
2nd: 400Mbps/ch
1st: 400Mbps /w 2ch
2nd: 800Mbps /w 4ch
1.4mA/ch (2.85V)
H-sink: 500uA
V-sink:100uA
ANA5321/5331: LCD
Display Interface
2kind/2chips for Tx or Rx
Sub LVDS, Unidirectional,
1 data: 16/18/24bit
1 clock: ~800MHz
I2C for CPU mode
ANA5521: Camera/LCD
Display 1kind/2chips for
SERDES configurable
Sub LVDS, Full-/Half- duplex
1f-data,1clock : ~800MHz
1 r-data,1 strobe clock
800Mbps/ch
800Mbps/w 1ch
1.0mA/ch
PD-mode: ~10uA
UMC 0.25um, 2.5V
Wide bandwidth,
Ultra fast mode,
Low Power, Low EMI,
Slim Architecture
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AnaPass fast Mobile Serial Link (fMSL)
ffast
ffast
MSL3 :
Mobile Serial Link
for Camera/LCD Module
MSL1 :
Mobile Serial Link
for Camera Module
b
Su lay
sp
Di
f-MSL1
Tx
Video
Processor
n
ai y
M pla
s
Di
Sub
Display
2
SL
M
f- Rx
Main
Display
f-MSL3
Ser/Des
o r
de sso
i
V e
L2
oc
S
r
P
f-M x
f-MSL3
Ser/Des
T
f-MSL1
Rx
Video
Processor
f -MSL2 : fast Mobile Serial Link
for LCD Module
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AnaPass fast Mobile Serial Link(f-MSL)
‰ Features
– Ultra fast mode Operation(Wide-bandwidth/High-speed)
• Up to 800Mbps with single channel
– Sub-LVDS type, Full/Half Duplex, 2 channels
• 4 lanes = 2 lanes for Data + 2 lanes for Clock
• Master/Slave Selectable
• 50~100mV Swing, 2.5V/3.3V, 0.25um Process
– Lower Power, Lower EMI noise
• Multi lanes for speed-up will multiply the link power by # of channels.
• Multi lanes for speed-up will bring much higher EMI noise.
Competitors
200Mbps
200Mbps
200Mbps
200Mbps
Clock
AnaPass f-MSL
800Mbps
Clock
1mA x4 + 1mA = 5mA
1mA x1 + 1mA = 2mA
– Supporting Clock Deskew, Spread Spectrum Clocking
• More timing margin for high speed operation, in case that PCB trace doesn’t match
– Packet based
• Byte synchronization is embedded with HSYNC and VSYNC.
• False synchronization protection algorithm (MIPI-like)
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AnaPass f-MSL2 for LCD Module Interface
‰ ANA5351
AP/BB with f-MSL
R/W#
AD
CS1#
CS2#
PD[17:0]
PD[17:0]
ANA5351
ANA5351
f-f-MSL2
MSL2
Transmitter
Transmitter
LCD Driver IC with f-MSL
2 channels by different signal
Up to 800Mbps
Transfer data/clock information
data
clock
Serial Line (Proposed Scheme)
• Low EMI by small-swing different signal
• Low Cost with small lines
• Small Size with small lines
R/W#
ANA5351
ANA5351
f-f-MSL2
MSL2
Receiver
Receiver
AD
CS1#
CS2#
PD[17:0]
PD[17:0]
LCD
LCD
Module
Module
(LDI
(LDI++
Main/Sub
Main/SubLCD)
LCD)
Parallel Line (Conventional Scheme)
• High EMI by full-swing signal as high frequency
• High Cost with parallel lines
• Large Size with parallel lines
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AnaPass f-MSL2 for LCD Module Interface
‰ ANA5351
– SERDES one chip for LCD module interface
• Master/Slave selectable
• Bi-directional
– RGB Interface / CPU Interface
– Highest data throughput with single channel
• Slow mode: up to 100Mbps for QVGA/HVGA, 18bit @ 30fps
• Normal mode: up to 200Mbps for VGA, 18bit @ 30fps
• Fast mode: up to 500Mbps for VGA, 24bit @ 60fps
– 0.25um Mixed CMOS process (2.5V/1.8V)
– BGA 48 (4 X 4 X 0.5 X 1.0 mm) /TAPP 48 (5 X 5 X 0.5 X 0.8 mm)
– Sample available @ May/’05
WR
RD
A/D(LRS)
D[17:0]
CS2
CS1
LDP
Parallel to
Serial
LDN
Serial to
Parallel
Serial to
Parallel
Parallel to
Serial
GPIO[3:0]
WR
RD
A/D(LRS)
D[17:0]
CS2
CS1
GPIO[3:0]
LCP
BBP
or
APP
LCLK
PDb
RSTb
M/S
TE
PLL
RGB
MUL
SW
PLL
Divider
LCN
LCLK
PDb
RSTb
M/S
TE
PLL
RGB
MUL
SW
Primary
Display
Sub
Display
16
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AnaPass f-MSL2 for LCD Module Interface
‰ ANA5351
A
WR
RD
A/D
CS1
LCLK
RSTb
GNDP
B
GPIO3
GPIO0
GPIO1
D2
PDb
PLL
LDP
C
D1
D0
VDDD
CS2
GNDO
VDDP
LDN
D
D3
GPIO2
MUL
SW
VDDA
GNDA
E
D4
D5
GNDD
VDDO
RGB
TE
LCN
F
D6
D7
D11
D13
D15
M/S
LCP
G
D8
D9
D10
D12
D14
D16
D17
1
2
3
4
5
6
7
Pin Name
I/O Type
f-MSL PINS (4)
LDP, LDN
I/O
LCP, LCN
I/O
Parallel Interface (24)
D0~D17
I/O
WR
I/O
RD
I/O
A/D
I/O
CS1,CS2
I/O
LCLK
I/O
Configuration (12)
M/S
I
RSTb
I
PDb
I
PLL
I
RGB
I
MUL
I
TE
I
SW
I
GPIO[3:0]
I/O
POWER/GROUND PINS(8)
VDDA, GNDA
PWR, GND
VDDP, GNDP
PWR, GND
VDDD, GNDD
PWR, GND
VDDO, GNDO
PWR, GND
Description
LCD positive/negative data
LCD positive/negative clock
18 bit LCD data bus
Write strobe
Read Strobe
Address/Data selection signal for LCD interface
Chip select 1, 2 for LCD interface
PLL input clock for CPU mode/LCD PCLK for RGB mode
Master/Slave selection (L: Master, H: Slave)
LCD reset signal input (L: reset enable)
LCD power down
PLL range configuration
(L: High frequency , H: Low frequency)
CPU/RGB mode selection (L:CPU mode, H:RGB mode)
Multiplying factor of LCLK (L:1x, H:1.5x) (Master)
WR strobe extension (L:2 clock, H:3 clock) (Slave)
Test mode enable
Swing range configuration (L:100mV, H:150mV)
GPIO signals
Power for transmitter and receiver
Power for PLL
Power for digital circuitry
Power for LCD I/O
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AnaPass f-MSL3 for Camera/LCD Interface
‰ ANA5551
Ref Clock
I2C-SCK
I2C-SDA
AP/BB with fAP/BB
-MSL
PCLK
Camera
Camera
Module
Module
(CIS/CCD)
(CIS/CCD)
Data[7:0]
Data[7:0]
VSYNC
HSYNC
clock
ANA5551
ANA5551
f-f-MSL3
MSL3
2 channels by different signal
Up to 800Mbps
Transfer data/clock information
SerDes
SerDes
HSYNC
(LDI
(LDI++
Main/Sub
Main/SubLCD)
LCD)
VSYNC
data
HSYNC
DOTCLK
LCD
LCD
Module
Module
PCLK
VSYNC
ANA5551
ANA5551
Data[7:0]
Data[7:0]
f-f-MSL3
MSL3
DOTCLK
SerDes
SerDes
VSYNC
HSYNC
data
ENABLE
ENABLE
clock
PD[17:0]
PD[17:0]
Parallel Line (Conventional Scheme)
• High EMI by full-swing signal
• High Cost with parallel lines
• Large Size with parallel lines
PD[17:0]
PD[17:0]
Serial Line (Proposed Scheme)
• Low EMI by small-swing different signal
• Low Cost with small lines
• Small Size with small lines
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AnaPass f-MSL3 for Camera/LCD Interface
‰ ANA5551
– SERDES one chip for Camera/LCD module interface
• Master/Slave selectable
• Bi-directional
– Support RGB Interface / CPU Interface for LCD
– Highest data throughput with single channel
•
•
•
•
Slow mode: up to 100Mbps for 0.3Mega Pixel @ 15fps
Normal mode: up to 250Mbps for 1Mega Pixel @ 15fps
Fast mode: up to 500Mbps for 2Mega Pixel @ 15fps
Ultra fast mode: up to 800Mbps for 3Mega Pixel @ 15fps, 1Mega Pixel @ 30fps
– 0.25um Mixed CMOS process (2.5V/1.8V)
– BGA 64 (5 X 5 X 0.5 X 1.0 mm) /TAPP 64 (5 X 5 X 0.4X 0.8 mm)
– Sample available @ May/’05
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20
AnaPass f-MSL3 for Camera/LCD Interface
WR
‰ ANA5551
– RGB Interface
(TBR)
A/D
LD[17:0]
CS2
CS1
LCLK
LRSTb
RGB
LPDb
M/S
LPCLK
TDP
Parallel to
Serial
PLL
TDN
LDP
LDN
RDP
RDN
TCP
LCP
RCP
TCN
LCN
RCN
Serial to
Parallel
Divider
YUV[7:0]
PCLK
LCLK
LRSTb
RGB
RDP
CDP
TDP
RDN
CDN
TDN
RCP
CCP
TCP
RCN
CCN
TCN
Divider
YUV[7:0]
Parallel to
Serial
VSYNC
HSYNC
PCLK
PLL
R/F
VA
Camera
R/F
VA
CPDb
CPDb
E
MCP
MCLK
MCLK
CLK
– CPU Interface
Parallel to
Serial
LCLK
LRSTb
RGB
PLL
ANA5551 Slave
TDP
LDP
RDP
TDN
LDN
RDN
TCP
LCP
RCP
TCN
LCN
RCN
Serial to
Parallel
Divider
LPDb
M/S
YUV[7:0]
VSYNC
HSYNC
PCLK
WR
A/D
LD[17:0]
CS2
CS1
LCLK
LRSTb
RGB
Primary
Display
LPDb
Sub
Display
M/S
TE
PLL
SW
MUL
TE
PLL
SW
MUL
BBP
or
APP
I2C
SCL
SDA
MCN
ANA5551 Master
WR
A/D
LD[17:0]
CS2
CS1
RGB
Display
LPCLK
LPDb
Serial to
Parallel
VSYNC
HSYNC
LDEN
RGB[666]
LHSYNC
LVSYNC
M/S
TE
PLL
SW
MUL
TE
PLL
SW
MUL
BBP
or
APP
WR
A/D
LD[17:0]
CS2
CS1
Serial to
Parallel
Divider
RDP
CDP
TDP
RDN
CDN
TDN
RCP
CCP
TCP
RCN
CCN
TCN
YUV[7:0]
Parallel to
Serial
VSYNC
HSYNC
PCLK
PLL
Camera
R/F
R/F
VA
CPDb
VA
CPDb
E
MCP
MCLK
MCLK
MCN
ANA5551 Master
ANA5551 Slave
CLK
I2C
SCL
SDA
LDEN
RGB[666]
LHSYNC
LVSYNC
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21
AnaPass f-MSL3 for Camera/LCD Interface
‰ ANA5551
A
MCLK
CD7
CD6
CD4
CD2
PCLK
TDP
TDN
B
CPDb
GNDC
CD5
CD3
HSYNC
VSYNC
VDDC
TCP
C
VA
MUL
M/S
CD1
CD0
VDDA
GNDA
TCN
D
LCLK
LRSTb
GNDL
R/F
RGB
VDDL
PLL
MCP
E
CS1
LPDb
CS2
GNDD
SW
TE
VDDD
MCN
F
WR
LD0
A/D
LD7
LD8
LD11
LD12
RCN
G
LD1
LD2
LD5
LD9
LD13
LD14
LD16
RCP
H
LD3
LD4
LD6
LD10
LD15
LD17
RDP
RDN
1
2
3
4
5
6
7
8
Pin Name
I/O Type
f-MSL Interface (10)
TDP, TDN
O
TCP, TCN
O
RDP, RDN
I
RCP, RCN
I
MCP, MCN
I/O
LCD Interface (23)
LD0~LD17
I/O
WR
I/O
A/D
I/O
CS1,CS2
I/O
LCLK
I/O
Camera Interface (12)
CD0~CD7
I/O
VSYNC
I/O
HSYNC
I/O
PCLK
I/O
MCLK
I/O
Configuration (11)
M/S
I
LRSTb
I
RGB
I
LPDb
I
R/F
I
VA
I
CPDb
I
TE
I
PLL
I
SW
I
MUL
I
Power/Ground (8)
VDDA, GNDA
PWR, GND
VDDD, GNDD
PWR, GND
VDDL, GNDL
PWR, GND
VDDC, GNDC
PWR, GND
Description
Positive/negative data transmitter
Positive/negative clock transmitter
Positive/negative data receiver
Positive/negative clock receiver
Camera positive/negative main clock
18 bit LCD data bus
Write strobe for LCD interface
Address/Data selection signal for LCD interface
Chip select 1, 2 for LCD interface
PLL reference clock for CPU mode/LCD PCLK for RGB mode
8 bit camera data bus
VSYNC for camera interface
HSYNC for camera interface
Pixel clock for camera interface
Main clock for camera interface
Master/Slave selection (L: Master, H: Slave)
LCD reset signal input (L: Reset enable)
RGB/CPU mode selection (L: CPU mode, H: RGB mode)
LCD power down
Clock triggering edge selection (L: Rising, H: Falling)
VSYNC active mode selection (L: Low, H: High)
Camera power down
Test mode enable
PLL range configuration (L: High frequency, H: Low frequency)
Swing range configuration (L: Small swing, H: Large swing)
Internal clock multiplier configuration (L: 1x, H: 1.5x)
Power for analog circuitry
Power for digital circuitry
Power for LCD I/O
Power for Camera I/O
Confidential
22
Evaluation & Demonstration
Module
‰ Demo Kit
Module
Camera
ISP
Camera
ISP
LCD
LCD
LDI w/ RAM
f-MSL SerDes
LDI w/ RAM
Main PCB
Main PCB
AP
RF
Base
Band
f-MSL SerDes
Memory
AP
Memory
Base
Band
Memory
Memory
RF
Confidential
Evaluation & Demonstration
‰ f-MSL3 Demo Kit (Camera/LCD module interface)
Camera
Module
USB Ctrl
AP
LCD
Module
23
Confidential
24
Evaluation & Demonstration
‰ f-MSL3 Demo Kit (Camera/LCD module interface)
Serial Link Data
f-MSL3
f-MSL3
SerDes
SerDes
Parallel Data
Confidential
Evaluation & Demonstration
‰ f-MSL3 Demo Kit (Camera/LCD module interface)
25
Confidential
26
Evaluation & Demonstration
‰ f-MSL3 Demo Kit (Camera/LCD module interface)
f-MSL3
Serial Link Data
SerDes
Camera
Module
LCD
Module
f-MSL3
AP
SerDes
Confidential
27
Thank you !
AnaPass, Inc.
KFSB Bld. 3F
16-2, Yoido Dong, Youngdeungpo Gu, Seoul 150-740, Korea
Tel. 82-2-761-2491
Fax. 82-2-761-2492
Web: http://www.anapass.com/
Email: [email protected]