asic and fpga design flow - Gujarat Technological University

THREE DAYS W O R K S H O P
ON
ASIC AND FPGA DESIGN FLOW
ON
28 Sep to 30th Sep , 2016
ABOUT CENTERS
th
About GTU
Gujarat Technological University (GTU) is a technological university established by Government of Gujarat vides Act
No. 20/2007. The university caters the entire field of Engineering, Pharmacy, Business studies (MBA) and Computer
Applications (MCA) in Gujarat. Today the university has about 5, 00,000 plus students, 500 affiliated colleges and
17000 faculties and a large number of Master's programs and 67 master's program and a robust doctoral programs.
The University is working with all the Colleges to sensitize them to the need for high quality of education. India's
largest sensitization and support programs in IPR, Innovation, Start-ups and co-creation activities. Fourteen PG
Research Centers and Schools in the advanced field of Technology, Policy and Skills.It is today the largest University in
Gujarat.
GTU is running Post Graduate Degree awarding programs in collaboration/affiliation M.E. program in collaboration
with C-DAC, ACTS and BISAG,Gandhinagar following courses with.
1. M.E. in Computer Engineering (Network Security) with 40 seats intake
2. M.E. in Computer Engineering (Wireless & Mobile Computing) with 40 seats intake
3. M.E. in Computer Engineering (High Performance Computing) with 40 seats intake
4. M.E. in Electronics and Communication (VLSI & Embedded Systems) with 60 seats intake
About C-DAC Advanced Computing Training School (ACTS)
C-DAC has set up the Advanced Computing Training School (ACTS) to meet the ever-increasing skilled manpower
requirements of the IT industry as well as supplement its intellectual resource base for cutting edge research and
development. C-DAC's Advanced Computing Training School (ACTS) is dedicated to creating high quality manpower
through the designing and delivering various Post Graduate Diploma courses and Post Graduate Degree Awarding
Courses. C-DAC is committed to nation building through its Advanced Computing Training School (ACTS) and is the
first Government Lab that has expanded its horizons globally, extending its high quality training services to countries
like Mauritius, Ghana, Uzbekistan, Tajikistan, Dubai Tanzania, Myanmar, Armenia, Belarus, Cambodia, Lesotho,
Seychelles, Graneda, Dominican Republic, Kazakshthan, Vietnam and Japan. Presently, ACTS is offering its courses
through a network of over fifty training centres spread across the country wherein thousands of students and
professionals are being trained to enhance their skills, and equipped with the latest methodologies in advanced
computing to enable them to make their mark in the Information and Communication Technology (ICT) industry.
Around quarter million students passed out since inception in last seventeen years. They are today successful
employees of many Multinational and Premier Indian IT companies, and many of them have become successful
entrepreneurs.
About CoreEL Technologies
CoreEL Technologies is a Customer Application Specific Product & Solutions (CASPS) company offering INNOVATIVE
solutions, which ranges across Intellectual Property (IP) cores, Design & Development, Bespoke System Design &
Prototype Development, Next-Gen Digital products, Integrated solutions, Low Volume Manufacturing, System
Upgrades and Obsolescence management, EDA tools, COTS products, Semiconductor solutions and Technology
Training. CoreEL is a leading developer of advanced electronic system level products and solutions to three primary
markets - Aerospace & Defence, Digital Media Broadcast and Universities & Institutions of higher learning.
About CoreEL University Program
CoreEL University Program focuses on bringing high end electronics design and embedded computing platforms to
the labs of colleges and university enhancing the experience of technical education and real time practice on world
beating technologies. The induction of latest technology platforms offers an immersive learning experience to
students and trainers ensures that forthcoming industry needs are met with. CoreEL enables the academia to push
the barriers of Industrial learning thanks to the substantive support of its technology partners and solution providers.
About BISAG
BISAG, formerly known as Remote Sensing and Communication Centre (RESECO), has been renamed after the great
Indian Mathematician of the 12th century, "Bhaskaracharya" BISAG is a State level nodal agency to facilitate the use
of spatial and geo-spatial technologies for the planning and developmental activities pertaining to Agriculture, Land
and Water Resource Management, Wasteland/Watershed Development, Forestry, Disaster Management,
Infrastructure and Education. The Institute started its operations in April 1997 and was renamed as "Bhaskaracharya
Institute for Space Applications and Geo-informatics" in December 2003.
ABOUT THE PROGRAM
OBJECTIVES
Awareness to the faculties with the Industry level ASIC and FPGA design flow
 ASIC Design Flow using Industry standard tools
 Explain the various steps involved in ASIC design flow using GDK130nm
 Analyze the role of FPGA Design and test bench in functional simulation environment
 Steps of Designing Application for FPGA.
 Interpret the concepts of physical verification
 Steps of real time Embedded system design flow
PRE-REQUISITES:
 Knowledge of Digital logic circuits
 Awareness of HDL (VHDL/Verilog HDL)
WHO SHOULD ATTEND?
This comprehensive training and certification program will be of specific interest to:
 VLSI Specialists
 Innovation Specialists & Entrepreneurs in VLSI Domain
 Academics, and other people interested in VLSI
 Faculties from different colleges
 ME students (Should be limited seats)
GTU CERTIFICATE
All participants of the workshop on “ASIC AND FPGA DESIGN FLOW” will be awarded a GTU certificate on
successful completion of the programme.
HOW TO APPLY
LAST DATE TO REGISTER ON WEBSITE: 22nd SEPTEMBER, 2016.
FREE REGISTRATION
Google Docs Link: https://goo.gl/forms/ySubezY9JsgCRUtw2
DATE AND VENUE OF THE PROGRAM
DATE: 28th SEPTEMBER 2016, TO 30th SEPTEMBER, 2016 (THREE DAYS)
TIMINGS: 10.00 AM TO 6.30 PM
VENUE: BISAG - Bhaskaracharya Institute for Space Applications and Geo-informatics, 4th floor,
Near CH '0' Circle, Indulal Yagnik Marg, Gandhinagar-Ahmedabad Highway, Gandhinagar-382 007
SCHEDULE OF THE PROGRAM
Day 1: (28th September 2016)
 Xilinx Seven Series FPGA architecture and Vivado Design flow ,Zynq Architecture and Vivado IP integrator
design flow
Lab1: Getting started with Vivado design flow using Artix-7 FPGA ,Hardware debugging using ILA core
Lab2:Inseration of ILA core in design and debugging using logic analyzer ,Embedded design flow on Zynq
Lab3: Implementation of Acortex-9 processor design on Zynq
Day2: (29th September 2016)
 Discuss Full custom and semi-custom design flow
 Discuss the Pyxis tool flow for CMOS Design
Lab4:Create NAND schematic using mentor graphics pyxis schematic tool with GDK130nm ,Simulation using
ELDO simulator and viewing waveform on EZwave ,Lab for DC and transient analysis using pyxis and Ezwave
Lab5:Generating layout from schematic using Pyxis layout tool with GDK90nm,Remove all DRC errors and
create GDS II file
Day3: (30th September 2016)
 Discuss Layout Design rule ,Learn Design rule check and parasitic extraction ,Discuss deep sub-micron
condition of MOSFET ,Discuss effects using 60nm and 45nm technology
Lab6:Removing DRC error in layout with the help of Calibre tool,Perform Layout versus Schematic with
calibre tool, Perform Parasitic extraction and generate pex file
Lab7:Create a schematic of Common Source amplifier using Pyxis schematic,Perform DC and AC analysis
using ELDO and EZ wave, Generate physical layout of Common Source amplifier using Pyxis Layout,Perform
physical verification using Calibre tool, Create GDS II file and verify the layout using Calibre tool
Organizing Committee
Chief Patron
Dr. RAJUL K GAJJAR
Dr. J. C. LILANI
Vice Chancellor (I/c), GTU
Registrar (I/c), GTU
Ms. DARSHANA CHAUAHN
Chief Conveners
Mr. Suresh Sikka
Mr. Gardas Naresh Kumar
STO, CDAC-ACTS
Program Co-ordinator, CDAC-ACTS
OSD, GTU
Patrons
Mr. Aditya Kumar Sinha
PTO, CDAC-ACTS, Pune|
Conveners
Mr. DARSHAN PATEL
Mr. BHADRESH GOHIL
Assistant Professor
Assistant Professor
Mr. HARISH VAGHELA
Resource Persons
Mr.Mayur Deshmukh
Mr. Prasad.Y
Senior Application Engineer
CoreEL Technologies (I) Pvt Ltd
Application Engineer
CoreEL Technologies (I) Pvt Ltd
Contact us
GUJARAT TECHNOLOGICAL UNIVERSITY
(Established Under Gujarat Act. No. 20 of 2007)
CHANDKHEDA CAMPUS
Nr.Vishwakarma Government Engineering College,
Visat - Gandhinagar Highway, Chandkheda,
Ahmedabad – 382424 – Gujarat.
[email protected]
79-23267588,9909944891, 9712942969