USB MSD board V3.0 User Manual

USB MSD board
V3.0
User Manual
05/26/14
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Table of Contents
1. Features............................................................................................................. 3 2. Implementations ............................................................................................ 3 3. Device Overview ............................................................................................. 4 4. System Description ........................................................................................ 6 5. FPGA interface................................................................................................. 7 6. MSD demonstration....................................................................................... 9 7. Application example .................................................................................... 10 8. Assembly ........................................................................................................ 11 9. Electrical specifications ............................................................................... 12 10. Revision history ............................................................................................ 12 11. Disclaimer ....................................................................................................... 12 05/26/14
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1. Features







Data width 8 bits
Data file’s size up to 4GBytes.
USB 2.0 Full-speed connectivity
No software drivers required
Powered by USB or external +5V source
Perfectly fits to Papilio FPGA development boards
Compatible with Windows XP, Vista, 7.
2. Implementations





Digital data logging
Digital data acquisition
Video application
Audio application
Debug/testing
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3. Device Overview
Present MSD is a full-speed USB device used for transferring the digital data from
embedded electronic system to the PC.
Figure 1 shows top and bottom view of the device.
Figure 1. Top and bottom view
Figure 2 identifies the some components.
Figure 2. Some components identifications
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The Table 1 shows the data connector J1 pins description.
Table 1
Pin# Signal Name
Signal Description
Signal Direction
1- 8
DATA_0-7
Input data bit 0-7
in
9
DATA_RDY
Input data gate
in
10
DATA_ENB
Input data enable
in
11
DATA_REQ_N
Input data request. Active Low
12
RESET_N
Reset of MSD. Active Low
out
in
The Table 2 shows the +5V/Gnd connector J2 pins description.
Table 2
Pin# Signal Name
Signal Description
1
Gnd
Common
2
NU
Not using
3
NU
Not using
4
+5V
External +5V input supply
The Table 3 shows the programming connector J5 pins description.
Table 3
Pin# Signal Name
Signal Description
1
GND
Common
2
C2CK
Programming and debugging interface clock signal
3
C2D
Programming and debugging interface bi-directional data signal
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The Table 4 shows the power selection connector J4 pins description.
Table 4
Pin# Signal Name
Signal Description
1
+5V USB
+5V from USB connector.
2
+5V
+5V to MCU. Connect to pin 1 to select +5v USB, pin 3 to select
+5V Ext.
3
+5V Ext
+5V from External supply (Connector J2,pin 4).
4. System Description
Figure 3 shows a possible system with MSD implementation. System consists of
Embedded module, MSD board and PC.
Figure 3. MSD implementation
The system is functioning according Timing diagram on Figure 4.
Embedded module has an external port for interfacing to MSD board. Embedded
module sends the RESET_N and DATA_RDY signal to the MSD board , then sends 4
bytes of data length, starting from MSB, and sends data bytes to the MSD board by
request DATA_REQ_N signal. The amount of data bytes to be send must equal to data
length.
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Figure 4. MSD timing diagram.
5. FPGA interface
For interfacing FPGA with the MSD board, the VHDL component msd_wing_rd_v0.vhd
was designed. This component allows read data From FPGA memory and then transfer
data to PC via MSD board.
The Table 5 shows the msd_wing_rd_v0.vhd component signal description.
Table 5
Signal Name
Signal Description
Direction
reset
System Reset.
in
mclk
Clock. Clock’s period duration must be no less
than SRAM’s read cycle duration
in
mclk_180
Inverted Clock.
in
data_out_format
Output data format. Two format available: ‘0’ –
Binary raw data; ‘1’- Hex data format as
“HexHex\n”.
in
sram_last_addr
Memory Last address.
in
sram_rd_start
msd_data_req
o_msd_data_rdy
05/26/14
Start pulse for transferring memory data to PC.
Transferring is starting after pulse become
non-active.
Data request signal from MSD board. Active
level is Zero.
Data is ready. This signal is sending to MSD.
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in
in
out
7
o_msd_data_enb
o_msd_data
o_msd_reset_n
o_sram_rd_gate
Data Enable. This signal is sending to MSD.
8 bits output data. This signal is sending to
MSD.
Reset of MSD board. Active low. Duration must
be at least 20usec. By this signal, the MSD
board starts to receive and transfer data to PC.
This signal stays high during reading data from
memory.
out
out
out
out
o_sram_rd_addr
Memory read address.
out
o_sram_re_n
Memory read enable pulse. Active low.
out
sram_data
Memory output data
in
The Table 6 shows the msd_wing_rd_v0.vhd component constant description.
Table 6
Constant Name
Constant Description
SRAM_DATA_WIDTH
Memory Data bus width. Must be 8 bits.
SRAM_ADDR_WIDTH
Memory Address bus width. Max width is 31.
MSD_RESET_LENGTH_WIDTH
MSD board reset pulse duration. This constant value must
provide a pulse duration at least 20usec.
MSD_DATA_REQ_ACTIVE_LEVEL
Data request signal active level. Must be ‘0’.
For testing the interface component msd_wing_rd_v0.vhd on the Papilo One 500k
board, other FPGA project msd_wing_ifc.zip was developed. Project directory includes
all components VHDL source code and constraint file. For manual reset, the reset
switch on OV7670 adapter module is using (Figure 5).
Figure 5. OV7670 adapter module.
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6. MSD demonstration
Upon connecting MSD board very 1st time to the PC, the operating system will detect
the new hardware, recognize it as a standard USB Mass Storage Device (MSD), and
install appropriate drivers automatically. At the end of this process (also at power up
of MSD board) you should also see a Removable Disk and file mdata.txt in Windows
Explorer. See Figure 7.
Figure 7. MSD on Windows Explorer after power up.
Some remarks:
 File name appears as mdata.txt always.
 File data modified appears as 1/19/2014 7:42 AM always.
 File size 4,194,304KB appears due power up only.
During the data transfer, the actual file is created as shown on Figure 8.
Figure 8. Created file on Windows Explorer.
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File can be viewed, copied or moved using Windows Explorer. See Figure 9.
Figure 9. Viewing file on Windows Explorer.
7. Application example
Figure 10 shows video application example.
Figure 10. Video application example.
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8. Assembly
We provide the assembly kits only with content of:
 Raw PCB module.
 MCU C8051F342-GQ with pre-installed firmware.
Figure 11 shows assembly drawing.
Figure 11. Assembly drawing.
The Table 7 shows the BOM of components, except MCU and PCB.
Table 7
Manufacturer
Component
Amount
Reference
Value
Package
Capacitor SMT
2
C1,C2
1UF 16V 10%
0603
any
Capacitor SMT
2
C4,C5
0.1UF 16V 10%
0603
any
Resistor SMT
2
R1,R2
1k 5%
0603
any
Resistor SMT
1
R3
470 5%
0603
any
TVS Diode
Arrays
1
D1
SOT143-4
Littelfuse
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Manufacturer
part number
F2715CT-ND
11
2V, 5mA
any
LED SMT
1
D2
0603
USB Mini B
connector
1
J3
Header
1
J1
0.1'',one row, 12pos
any
Header
1
J2
0.1'', one row, 4pos
any
Header
2
J4,J5
0.1'', one row, 3pos
any
On Shore
Technology Inc
USB-M26FTR
9. Electrical specifications
Symbol
Parameter
Vil
Input Low voltage
Vih
Input High voltage
Ta
Ambient temperature
Min.
Max.
Standard
Unit
0.8
LVTTL33
V
LVTTL33
V
--
Degree C
2.0
0
50
10. Revision history
Date
Description
Version
5/16/14
1.0
Original
5/24/14
2.0
Added section “FPGA interface”
5/26/14
3.0
Added section “MSD demonstration”
11. Disclaimer
We expressly disclaims any liability arising out of the application or use of the MSD.
We reserve the right to make changes, at any time, to the MSD as deemed desirable in
the sole discretion of ours. We assume no obligation to correct any errors contained
herein or to advise you of any correction if such be made. We will not assume any
liability for the accuracy or correctness of any engineering or technical support or
assistance provided to you in connection with the MSD.
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THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS
FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE
THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR
ADVICE, WHETHER GIVEN BY US, OR OUR AGENTS OR EMPLOYEES. WE MAKE NO
OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE
DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
The MSD is not designed or intended for use in the development of on-line control
equipment in hazardous environments requiring fail-safe controls, such as in the
operation of nuclear facilities, aircraft navigation or communications systems, air traffic
control, life support, or weapons systems (“High-Risk Applications”). We specifically
disclaim any express or implied warranties of fitness for such High-Risk Applications.
You represent that use of the MSD in such High-Risk Applications is fully at your risk.
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