Posim> LAB

Cell-Based Training LAB
< Posim>
LAB
Aug. 2008
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Cell-Based Training LAB
Copy <CPU_CHIP.gds> from [SOC] to [ADD_LVS]
Copy <RAM_64B.vclef> from [MEM] to [ADD_LVS]
Add LVS Label and On-Line DRC Using <Virtuoso> & <Calibre>
File preparations:
CPU_CHIP.gds (i.e. from SOC encounter)
0.18um_Virtuoso4.4.tf (i.e. from CIC Design Kit)
tsmc18_core.gds (i.e. from CIC Design Kit)
tsmc18_io_final.gds3 (i.e. from CIC Design Kit)
t18abs2lay.ile (i.e. from CIC Design Kit)
display.drf (i.e. from CIC Design Kit)
T18drc_13a25a.drc (i.e. DRC rules and from CIC Design Kit)
RAM_64B.vclef (i.e. from Artisan)
Stream In Design
(CIW) File Import Stream…
Input File: CPU_CHIP.gds
Top Cell Name: CPU_CHIP
Library Name: CPU_CHIP
ASCII Technology File Name: 0.18um_Virtuoso4.4.tf
OK
Stream In Standard Cells
(CIW) File Import Stream…
Input File: tsmc18_core.gds
Library Name: CPU_CHIP
ASCII Technology File Name: 0.18um_Virtuoso4.4.tf
Clear the Top Cell Name
OK
(CIW) File Import Stream…
Input File: tsmc18_io_final.gds3
Library Name: CPU_CHIP
ASCII Technology File Name: 0.18um_Virtuoso4.4.tf
OK
Stream In LEF Files
(CIW) File Import LEF…
LEF File Name: RAM_64B.vclef
Target Library Name: CPU_CHIP
OK
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Cell-Based Training LAB
(CIW command line) load(“t18abs2lay.ile”)
LVS Tools for UMC18 copy Abs to Lay
Library Name: CPU_CHIP
Cell Name: RAM_64B
OK
(Library Manager) View Refresh
(Library Manager) Library: CPU_ CHIP; Cell: CPU_CHIP; View: layout
Open
You can use hot key “Shift+F” to show all the layers
Fig. Virtuoso layout view
You can check:
Whether all pins of hard blocks are connected?
Whether the power lines are in the correct layers? (i.e. vertical: METAL4;
horizontal: METAL5)
If not, maybe your “streamOut.map” file using in the P&R is not
correct.
(CIW) File Export Stream
Library: CPU_CHIP; Cell: CPU_CHIP; View: layout
Output File: CPU_CHIP_01.gds
OK
On-line DRC
Calibre
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Cell-Based Training LAB
Load Runset File: CPU_CHIP_01.gds
Press “Rules”: T18drc_13a25a.drc
Press “Inputs” Select “Flat”
Press “Run DRC”
Because of the P&R tool is not too smart, some DRC violations may occur.
If there are few errors occur, we can fix them by ourselves. But if the error count
is high, you may do something wrong in the P&R procedure. You should re-do
the P&R.
Finally, there are 7 errors remained since that the deficiency of metal coverage
before standard cell layout replacement (LPE).
Fig. On-line DRC
(LSW) Select “METAL2/pn”
Hot key “l” to create label
Add label “VDD” to all PADs of “PVDD1DGZ”
Add label “VSS” to all PADs of “PVSS1DGZ”
Add label “DVDD” to all PADs of “PVDD2DGZ”
Add label “DVSS” to all PADs of “PVSS2DGZ”
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Cell-Based Training LAB
Fig. PADs and labels
Design Save
(CIW) File Export Stream
Library: CPU_CHIP; Cell: CPU_CHIP; View: layout
Output File: CPU_CHIP_01.gds
OK
Off-Line DRC Using <Calibre>
File preparations:
T18drc_13a25a.drc (i.e. DRC rules and from CIC Design Kit)
Open < T18drc_13a25a.drc > and modify it as follows:
unix> caliber –drc T18drc_13a25a.drc
After the DRC done, you can check the DRC.rep as follows:
RULECHECK PO.R.3 ............ TOTAL Result Count = 1
RULECHECK M1.R.1 ............ TOTAL Result Count = 1
RULECHECK M2.R.1 ............ TOTAL Result Count = 1
RULECHECK M3.R.1 ............ TOTAL Result Count = 1
RULECHECK M4.R.1 ............ TOTAL Result Count = 1
RULECHECK M5.R.1 ............ TOTAL Result Count = 1
……
RULECHECK _M6T.R.1 .......... TOTAL Result Count = 1
……
--- SUMMARY
--TOTAL CPU Time:
TOTAL REAL Time:
339
340
TOTAL Original Layer Geometries: 11373297
TOTAL DRC RuleChecks Executed:
322
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Cell-Based Training LAB
TOTAL DRC Results Generated:
7
Copy <CPU_CHIP.v> from [SOC] to [LVS]
Block-Box LVS Using <Calibre>
File preparations:
CPU_CHIP.v (i.e. from SOC encounter)
Calibre-lvs-cur_soce (i.e. LVS rules, from CIC Design Kit)
RAM_64B.v (i.e. just I/O definitions, user edit)
RAM_64B.spi (i.e. just I/O definitions, user edit)
tsmc18_lvs.spi (i.e. standard cell SPICE files, from CIC Design Kit)
tsmc18_lvs.v (i.e. standard cell Verilog files, from CIC Design Kit)
General LVS performs the comparison between the “Layout” and the
“Schematic”. In the cell based design, there is no “real Schematic” exist. Instead,
the “Schematic” in the cell base design is converted from the “gate-level Verilog
netlist”. The converting tool references “SPICE” template files, and then
converts the entire “cells” in the Verilog files into “sub circuits”.
In the CIC design flow, the layout of the Artisan memories and standard cells can
not be seen. However, any standard cells and hard blocks should already be
passed through the LVS checking. Therefore, only the inter-connections are
needed to be verified, not the cells and hard blocks layouts – they are blocked!
That’s why we called Block Box LVS.
2 files are compared:
layout.spi (i.e. generated from the layout file – CPU_CHIP_01.gds)
source.spi (i.e. converted from the Verilog files – CPU_CHIP.v and
RAM_64B.v)
RAM_64B.v and RAM_64B.spi are shown bellow: (i.e. all the hard blocks
should be treated in the same way)
Edit these files by sourself
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Cell-Based Training LAB
Fig. Hard block templates
unix> v2lvs –v CPU_CHIP.v –l tsmc18_lvs.v –l RAM_64B.v –o
source.spi –s tsmc18_lvs.spi –s RAM_64B.spi –s1 VDD –s0 VSS
be sure that the “source.spi” is generated
Revise the “Calibre-lvs-cur_soce”
LAYOUT PRIMARY “CPU_CHIP”
LAYOUT PATH “../ADD_LVS/CPU_CHIP_01.gds”
LAYOUT CASE YES
SOURCE PRIMARY “CPU_CHIP”
SOURCE PATH “source.spi”
SOURCE CASE YES
Add the following contents in the last line:
LVS BOX RAM_64B
Blocking the following lines:
//LVS BOX PADIZ40
//LVS BOX PADOZ40
//LVS BOX PCORNERDG
//LVS BOX PCORNERDG_L
//LVS BOX PVDD1DGZ
//LVS BOX PVSS1DGZ
//LVS BOX PVSS2DGZ
//LVS BOX PVSS3DGZ
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Cell-Based Training LAB
unix> caliber –lvs –spice layout.spi –hier –auto Calibre-lvs-cur_soce
you can check the lvs.rep
Fig. LVS result
---------The following steps should be performed on CIC server--------LPE (Replace Layout and RC Extraction)
File preparations:
CPU_CHIP_01.gds (i.e. from Virtuoso)
RAM_64B.spec (i.e. from Artisan)
unix> ssh –l username 140.126.24.14
(connecting to CIC server)
queue>
create a new folder for LPE and get into it
ftp cae18.ee.ncu.edu.tw
ftp> get CPU_CHIP_01.gds
ftp> get RAM_64B.spec
ftp> by
Also, you can use your FTP tool by using the “SSH2” mode
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Cell-Based Training LAB
Fig. FTP in SSH2 mode
queue> Qentry –M LPE –tech TSMC18 –f CPU_CHIP_01.gds –T
CPU_CHIP –s RAM_64B.spec –t t18ra1shd –c TSMC18 –i TSMC18 –o
CHIP.netlist
Another method: (If you have a huge number of memories, the number of
command bits may exceed the PVS constraint.)
Edit the file: command.run
! " # # $ % & ! " # ' % & ! ' # ' % & ! ' # # $ % & ! $ $ # $ % & ! $ $ ' % & ! ( $ $ % & ! ( $ # % & ! # $ $ % & ! # $ # % ) & * + , * queue/cicq78a> chmod 755 command.run
queue/cicq78a> ./command.run
Post-Layout Simulation Using <Nanosim>
File preparations:
Warning: the patterns should be
applied at negative edge !!
CHIP.vec (i.e. user edit)
CHIP.cfg (i.e. user edit)
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Cell-Based Training LAB
CHIP.netlist (i.e. from LPE)
spice.header (i.e. from LPE)
Generate your nanosim test benches from the Verilog-XL simulation:
Copy <tcpu.v>, <cpu.v>, <RAM_64B.v> from [RTL] to
[POSIM/PATTERN/GEN]
Modify the time scale in <tcpu.v> and <RAM_64B.v>
Modify <tcpu.v>
negative edge !!
Warning: the patterns should be applied at
Test pins declarations:
The values of test pins should be assigned
Add the test benche generation functions as follows:
Fig. NANOSIM testbenches generation
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Cell-Based Training LAB
verilog tcpu.v
generate the file <cpu.dat>
then, copy all the patterns and paste them in the file <CHIP.vec> (in
[POSIM])
Example of CHIP.cfg:
Fig. Example of CHIP.cfg
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Cell-Based Training LAB
queue>
create a new folder for NANOSIM and get into it
queue> Qentry –M NANOSIM –nspice CHIP.netlist spice.header –nvec
CHIP.vec –m CPU_CHIP –c CHIP.cfg –o CHIP –out fsdb –t 12000
Finally, download the “CHIP.fsdb” and “nanosim.log” to check the po-sim
waveforms and powers.
Fig. Po-sim waveforms
Fig. Average power in nanosim.log
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